2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
27 #include "r600_pipe_common.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
40 #include <sys/utsname.h>
46 struct r600_multi_fence
{
47 struct pipe_reference reference
;
48 struct pipe_fence_handle
*gfx
;
49 struct pipe_fence_handle
*sdma
;
51 /* If the context wasn't flushed at fence creation, this is non-NULL. */
53 struct r600_common_context
*ctx
;
59 * shader binary helpers.
61 void radeon_shader_binary_init(struct radeon_shader_binary
*b
)
63 memset(b
, 0, sizeof(*b
));
66 void radeon_shader_binary_clean(struct radeon_shader_binary
*b
)
73 FREE(b
->global_symbol_offsets
);
75 FREE(b
->disasm_string
);
76 FREE(b
->llvm_ir_string
);
86 * \param event EVENT_TYPE_*
87 * \param event_flags Optional cache flush flags (TC)
88 * \param data_sel 1 = fence, 3 = timestamp
90 * \param va GPU address
91 * \param old_value Previous fence value (for a bug workaround)
92 * \param new_value Fence value to write for this event.
94 void r600_gfx_write_event_eop(struct r600_common_context
*ctx
,
95 unsigned event
, unsigned event_flags
,
97 struct r600_resource
*buf
, uint64_t va
,
98 uint32_t old_fence
, uint32_t new_fence
)
100 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
101 unsigned op
= EVENT_TYPE(event
) |
105 if (ctx
->chip_class
== CIK
||
106 ctx
->chip_class
== VI
) {
107 /* Two EOP events are required to make all engines go idle
108 * (and optional cache flushes executed) before the timestamp
111 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0));
114 radeon_emit(cs
, ((va
>> 32) & 0xffff) | EOP_DATA_SEL(data_sel
));
115 radeon_emit(cs
, old_fence
); /* immediate data */
116 radeon_emit(cs
, 0); /* unused */
119 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0));
122 radeon_emit(cs
, ((va
>> 32) & 0xffff) | EOP_DATA_SEL(data_sel
));
123 radeon_emit(cs
, new_fence
); /* immediate data */
124 radeon_emit(cs
, 0); /* unused */
127 r600_emit_reloc(ctx
, &ctx
->gfx
, buf
, RADEON_USAGE_WRITE
,
131 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen
*screen
)
135 if (screen
->chip_class
== CIK
||
136 screen
->chip_class
== VI
)
139 if (!screen
->info
.has_virtual_memory
)
145 void r600_gfx_wait_fence(struct r600_common_context
*ctx
,
146 uint64_t va
, uint32_t ref
, uint32_t mask
)
148 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
150 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
151 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
| WAIT_REG_MEM_MEM_SPACE(1));
153 radeon_emit(cs
, va
>> 32);
154 radeon_emit(cs
, ref
); /* reference value */
155 radeon_emit(cs
, mask
); /* mask */
156 radeon_emit(cs
, 4); /* poll interval */
159 void r600_draw_rectangle(struct blitter_context
*blitter
,
160 int x1
, int y1
, int x2
, int y2
, float depth
,
161 enum blitter_attrib_type type
,
162 const union pipe_color_union
*attrib
)
164 struct r600_common_context
*rctx
=
165 (struct r600_common_context
*)util_blitter_get_pipe(blitter
);
166 struct pipe_viewport_state viewport
;
167 struct pipe_resource
*buf
= NULL
;
171 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
172 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
176 /* Some operations (like color resolve on r6xx) don't work
177 * with the conventional primitive types.
178 * One that works is PT_RECTLIST, which we use here. */
181 viewport
.scale
[0] = 1.0f
;
182 viewport
.scale
[1] = 1.0f
;
183 viewport
.scale
[2] = 1.0f
;
184 viewport
.translate
[0] = 0.0f
;
185 viewport
.translate
[1] = 0.0f
;
186 viewport
.translate
[2] = 0.0f
;
187 rctx
->b
.set_viewport_states(&rctx
->b
, 0, 1, &viewport
);
189 /* Upload vertices. The hw rectangle has only 3 vertices,
190 * I guess the 4th one is derived from the first 3.
191 * The vertex specification should match u_blitter's vertex element state. */
192 u_upload_alloc(rctx
->uploader
, 0, sizeof(float) * 24, 256, &offset
, &buf
, (void**)&vb
);
212 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
213 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
214 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
218 util_draw_vertex_buffer(&rctx
->b
, NULL
, buf
, blitter
->vb_slot
, offset
,
219 R600_PRIM_RECTANGLE_LIST
, 3, 2);
220 pipe_resource_reference(&buf
, NULL
);
223 static void r600_dma_emit_wait_idle(struct r600_common_context
*rctx
)
225 struct radeon_winsys_cs
*cs
= rctx
->dma
.cs
;
227 /* NOP waits for idle on Evergreen and later. */
228 if (rctx
->chip_class
>= CIK
)
229 radeon_emit(cs
, 0x00000000); /* NOP */
230 else if (rctx
->chip_class
>= EVERGREEN
)
231 radeon_emit(cs
, 0xf0000000); /* NOP */
233 /* TODO: R600-R700 should use the FENCE packet.
234 * CS checker support is required. */
238 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
,
239 struct r600_resource
*dst
, struct r600_resource
*src
)
241 uint64_t vram
= ctx
->dma
.cs
->used_vram
;
242 uint64_t gtt
= ctx
->dma
.cs
->used_gart
;
245 vram
+= dst
->vram_usage
;
246 gtt
+= dst
->gart_usage
;
249 vram
+= src
->vram_usage
;
250 gtt
+= src
->gart_usage
;
253 /* Flush the GFX IB if DMA depends on it. */
254 if (radeon_emitted(ctx
->gfx
.cs
, ctx
->initial_gfx_cs_size
) &&
256 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
, dst
->buf
,
257 RADEON_USAGE_READWRITE
)) ||
259 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
, src
->buf
,
260 RADEON_USAGE_WRITE
))))
261 ctx
->gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
263 /* Flush if there's not enough space, or if the memory usage per IB
266 * IBs using too little memory are limited by the IB submission overhead.
267 * IBs using too much memory are limited by the kernel/TTM overhead.
268 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
270 * This heuristic makes sure that DMA requests are executed
271 * very soon after the call is made and lowers memory usage.
272 * It improves texture upload performance by keeping the DMA
273 * engine busy while uploads are being submitted.
275 num_dw
++; /* for emit_wait_idle below */
276 if (!ctx
->ws
->cs_check_space(ctx
->dma
.cs
, num_dw
) ||
277 ctx
->dma
.cs
->used_vram
+ ctx
->dma
.cs
->used_gart
> 64 * 1024 * 1024 ||
278 !radeon_cs_memory_below_limit(ctx
->screen
, ctx
->dma
.cs
, vram
, gtt
)) {
279 ctx
->dma
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
280 assert((num_dw
+ ctx
->dma
.cs
->current
.cdw
) <= ctx
->dma
.cs
->current
.max_dw
);
283 /* Wait for idle if either buffer has been used in the IB before to
284 * prevent read-after-write hazards.
287 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma
.cs
, dst
->buf
,
288 RADEON_USAGE_READWRITE
)) ||
290 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma
.cs
, src
->buf
,
291 RADEON_USAGE_WRITE
)))
292 r600_dma_emit_wait_idle(ctx
);
294 /* If GPUVM is not supported, the CS checker needs 2 entries
295 * in the buffer list per packet, which has to be done manually.
297 if (ctx
->screen
->info
.has_virtual_memory
) {
299 radeon_add_to_buffer_list(ctx
, &ctx
->dma
, dst
,
301 RADEON_PRIO_SDMA_BUFFER
);
303 radeon_add_to_buffer_list(ctx
, &ctx
->dma
, src
,
305 RADEON_PRIO_SDMA_BUFFER
);
308 /* this function is called before all DMA calls, so increment this. */
309 ctx
->num_dma_calls
++;
312 static void r600_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
316 void r600_preflush_suspend_features(struct r600_common_context
*ctx
)
318 /* suspend queries */
319 if (!LIST_IS_EMPTY(&ctx
->active_queries
))
320 r600_suspend_queries(ctx
);
322 ctx
->streamout
.suspended
= false;
323 if (ctx
->streamout
.begin_emitted
) {
324 r600_emit_streamout_end(ctx
);
325 ctx
->streamout
.suspended
= true;
329 void r600_postflush_resume_features(struct r600_common_context
*ctx
)
331 if (ctx
->streamout
.suspended
) {
332 ctx
->streamout
.append_bitmask
= ctx
->streamout
.enabled_mask
;
333 r600_streamout_buffers_dirty(ctx
);
337 if (!LIST_IS_EMPTY(&ctx
->active_queries
))
338 r600_resume_queries(ctx
);
341 static void r600_flush_from_st(struct pipe_context
*ctx
,
342 struct pipe_fence_handle
**fence
,
345 struct pipe_screen
*screen
= ctx
->screen
;
346 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
347 struct radeon_winsys
*ws
= rctx
->ws
;
349 struct pipe_fence_handle
*gfx_fence
= NULL
;
350 struct pipe_fence_handle
*sdma_fence
= NULL
;
351 bool deferred_fence
= false;
353 if (flags
& PIPE_FLUSH_END_OF_FRAME
)
354 rflags
|= RADEON_FLUSH_END_OF_FRAME
;
355 if (flags
& PIPE_FLUSH_DEFERRED
)
356 rflags
|= RADEON_FLUSH_ASYNC
;
358 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
360 rctx
->dma
.flush(rctx
, rflags
, fence
? &sdma_fence
: NULL
);
362 if (!radeon_emitted(rctx
->gfx
.cs
, rctx
->initial_gfx_cs_size
)) {
364 ws
->fence_reference(&gfx_fence
, rctx
->last_gfx_fence
);
365 if (!(rflags
& RADEON_FLUSH_ASYNC
))
366 ws
->cs_sync_flush(rctx
->gfx
.cs
);
368 /* Instead of flushing, create a deferred fence. Constraints:
369 * - The state tracker must allow a deferred flush.
370 * - The state tracker must request a fence.
371 * Thread safety in fence_finish must be ensured by the state tracker.
373 if (flags
& PIPE_FLUSH_DEFERRED
&& fence
) {
374 gfx_fence
= rctx
->ws
->cs_get_next_fence(rctx
->gfx
.cs
);
375 deferred_fence
= true;
377 rctx
->gfx
.flush(rctx
, rflags
, fence
? &gfx_fence
: NULL
);
381 /* Both engines can signal out of order, so we need to keep both fences. */
383 struct r600_multi_fence
*multi_fence
=
384 CALLOC_STRUCT(r600_multi_fence
);
388 multi_fence
->reference
.count
= 1;
389 /* If both fences are NULL, fence_finish will always return true. */
390 multi_fence
->gfx
= gfx_fence
;
391 multi_fence
->sdma
= sdma_fence
;
393 if (deferred_fence
) {
394 multi_fence
->gfx_unflushed
.ctx
= rctx
;
395 multi_fence
->gfx_unflushed
.ib_index
= rctx
->num_gfx_cs_flushes
;
398 screen
->fence_reference(screen
, fence
, NULL
);
399 *fence
= (struct pipe_fence_handle
*)multi_fence
;
403 static void r600_flush_dma_ring(void *ctx
, unsigned flags
,
404 struct pipe_fence_handle
**fence
)
406 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
407 struct radeon_winsys_cs
*cs
= rctx
->dma
.cs
;
408 struct radeon_saved_cs saved
;
410 (rctx
->screen
->debug_flags
& DBG_CHECK_VM
) &&
411 rctx
->check_vm_faults
;
413 if (!radeon_emitted(cs
, 0)) {
415 rctx
->ws
->fence_reference(fence
, rctx
->last_sdma_fence
);
420 radeon_save_cs(rctx
->ws
, cs
, &saved
);
422 rctx
->ws
->cs_flush(cs
, flags
, &rctx
->last_sdma_fence
);
424 rctx
->ws
->fence_reference(fence
, rctx
->last_sdma_fence
);
427 /* Use conservative timeout 800ms, after which we won't wait any
428 * longer and assume the GPU is hung.
430 rctx
->ws
->fence_wait(rctx
->ws
, rctx
->last_sdma_fence
, 800*1000*1000);
432 rctx
->check_vm_faults(rctx
, &saved
, RING_DMA
);
433 radeon_clear_saved_cs(&saved
);
438 * Store a linearized copy of all chunks of \p cs together with the buffer
441 void radeon_save_cs(struct radeon_winsys
*ws
, struct radeon_winsys_cs
*cs
,
442 struct radeon_saved_cs
*saved
)
447 /* Save the IB chunks. */
448 saved
->num_dw
= cs
->prev_dw
+ cs
->current
.cdw
;
449 saved
->ib
= MALLOC(4 * saved
->num_dw
);
454 for (i
= 0; i
< cs
->num_prev
; ++i
) {
455 memcpy(buf
, cs
->prev
[i
].buf
, cs
->prev
[i
].cdw
* 4);
456 buf
+= cs
->prev
[i
].cdw
;
458 memcpy(buf
, cs
->current
.buf
, cs
->current
.cdw
* 4);
460 /* Save the buffer list. */
461 saved
->bo_count
= ws
->cs_get_buffer_list(cs
, NULL
);
462 saved
->bo_list
= CALLOC(saved
->bo_count
,
463 sizeof(saved
->bo_list
[0]));
464 if (!saved
->bo_list
) {
468 ws
->cs_get_buffer_list(cs
, saved
->bo_list
);
473 fprintf(stderr
, "%s: out of memory\n", __func__
);
474 memset(saved
, 0, sizeof(*saved
));
477 void radeon_clear_saved_cs(struct radeon_saved_cs
*saved
)
480 FREE(saved
->bo_list
);
482 memset(saved
, 0, sizeof(*saved
));
485 static enum pipe_reset_status
r600_get_reset_status(struct pipe_context
*ctx
)
487 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
488 unsigned latest
= rctx
->ws
->query_value(rctx
->ws
,
489 RADEON_GPU_RESET_COUNTER
);
491 if (rctx
->gpu_reset_counter
== latest
)
492 return PIPE_NO_RESET
;
494 rctx
->gpu_reset_counter
= latest
;
495 return PIPE_UNKNOWN_CONTEXT_RESET
;
498 static void r600_set_debug_callback(struct pipe_context
*ctx
,
499 const struct pipe_debug_callback
*cb
)
501 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
506 memset(&rctx
->debug
, 0, sizeof(rctx
->debug
));
509 static void r600_set_device_reset_callback(struct pipe_context
*ctx
,
510 const struct pipe_device_reset_callback
*cb
)
512 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
515 rctx
->device_reset_callback
= *cb
;
517 memset(&rctx
->device_reset_callback
, 0,
518 sizeof(rctx
->device_reset_callback
));
521 bool r600_check_device_reset(struct r600_common_context
*rctx
)
523 enum pipe_reset_status status
;
525 if (!rctx
->device_reset_callback
.reset
)
528 if (!rctx
->b
.get_device_reset_status
)
531 status
= rctx
->b
.get_device_reset_status(&rctx
->b
);
532 if (status
== PIPE_NO_RESET
)
535 rctx
->device_reset_callback
.reset(rctx
->device_reset_callback
.data
, status
);
539 static void r600_dma_clear_buffer_fallback(struct pipe_context
*ctx
,
540 struct pipe_resource
*dst
,
541 uint64_t offset
, uint64_t size
,
544 ctx
->clear_buffer(ctx
, dst
, offset
, size
, &value
, 4);
547 bool r600_common_context_init(struct r600_common_context
*rctx
,
548 struct r600_common_screen
*rscreen
,
549 unsigned context_flags
)
551 slab_create_child(&rctx
->pool_transfers
, &rscreen
->pool_transfers
);
553 rctx
->screen
= rscreen
;
554 rctx
->ws
= rscreen
->ws
;
555 rctx
->family
= rscreen
->family
;
556 rctx
->chip_class
= rscreen
->chip_class
;
558 if (rscreen
->chip_class
>= CIK
)
559 rctx
->max_db
= MAX2(8, rscreen
->info
.num_render_backends
);
560 else if (rscreen
->chip_class
>= EVERGREEN
)
565 rctx
->b
.invalidate_resource
= r600_invalidate_resource
;
566 rctx
->b
.transfer_map
= u_transfer_map_vtbl
;
567 rctx
->b
.transfer_flush_region
= u_transfer_flush_region_vtbl
;
568 rctx
->b
.transfer_unmap
= u_transfer_unmap_vtbl
;
569 rctx
->b
.texture_subdata
= u_default_texture_subdata
;
570 rctx
->b
.memory_barrier
= r600_memory_barrier
;
571 rctx
->b
.flush
= r600_flush_from_st
;
572 rctx
->b
.set_debug_callback
= r600_set_debug_callback
;
573 rctx
->dma_clear_buffer
= r600_dma_clear_buffer_fallback
;
575 /* evergreen_compute.c has a special codepath for global buffers.
576 * Everything else can use the direct path.
578 if ((rscreen
->chip_class
== EVERGREEN
|| rscreen
->chip_class
== CAYMAN
) &&
579 (context_flags
& PIPE_CONTEXT_COMPUTE_ONLY
))
580 rctx
->b
.buffer_subdata
= u_default_buffer_subdata
;
582 rctx
->b
.buffer_subdata
= r600_buffer_subdata
;
584 if (rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
>= 43) {
585 rctx
->b
.get_device_reset_status
= r600_get_reset_status
;
586 rctx
->gpu_reset_counter
=
587 rctx
->ws
->query_value(rctx
->ws
,
588 RADEON_GPU_RESET_COUNTER
);
591 rctx
->b
.set_device_reset_callback
= r600_set_device_reset_callback
;
593 r600_init_context_texture_functions(rctx
);
594 r600_init_viewport_functions(rctx
);
595 r600_streamout_init(rctx
);
596 r600_query_init(rctx
);
597 cayman_init_msaa(&rctx
->b
);
599 rctx
->allocator_zeroed_memory
=
600 u_suballocator_create(&rctx
->b
, rscreen
->info
.gart_page_size
,
601 0, PIPE_USAGE_DEFAULT
, true);
602 if (!rctx
->allocator_zeroed_memory
)
605 rctx
->uploader
= u_upload_create(&rctx
->b
, 1024 * 1024,
606 PIPE_BIND_INDEX_BUFFER
|
607 PIPE_BIND_CONSTANT_BUFFER
, PIPE_USAGE_STREAM
);
611 rctx
->ctx
= rctx
->ws
->ctx_create(rctx
->ws
);
615 if (rscreen
->info
.has_sdma
&& !(rscreen
->debug_flags
& DBG_NO_ASYNC_DMA
)) {
616 rctx
->dma
.cs
= rctx
->ws
->cs_create(rctx
->ctx
, RING_DMA
,
619 rctx
->dma
.flush
= r600_flush_dma_ring
;
625 void r600_common_context_cleanup(struct r600_common_context
*rctx
)
629 /* Release DCC stats. */
630 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
631 assert(!rctx
->dcc_stats
[i
].query_active
);
633 for (j
= 0; j
< ARRAY_SIZE(rctx
->dcc_stats
[i
].ps_stats
); j
++)
634 if (rctx
->dcc_stats
[i
].ps_stats
[j
])
635 rctx
->b
.destroy_query(&rctx
->b
,
636 rctx
->dcc_stats
[i
].ps_stats
[j
]);
638 r600_texture_reference(&rctx
->dcc_stats
[i
].tex
, NULL
);
641 if (rctx
->query_result_shader
)
642 rctx
->b
.delete_compute_state(&rctx
->b
, rctx
->query_result_shader
);
645 rctx
->ws
->cs_destroy(rctx
->gfx
.cs
);
647 rctx
->ws
->cs_destroy(rctx
->dma
.cs
);
649 rctx
->ws
->ctx_destroy(rctx
->ctx
);
651 if (rctx
->uploader
) {
652 u_upload_destroy(rctx
->uploader
);
655 slab_destroy_child(&rctx
->pool_transfers
);
657 if (rctx
->allocator_zeroed_memory
) {
658 u_suballocator_destroy(rctx
->allocator_zeroed_memory
);
660 rctx
->ws
->fence_reference(&rctx
->last_gfx_fence
, NULL
);
661 rctx
->ws
->fence_reference(&rctx
->last_sdma_fence
, NULL
);
668 static const struct debug_named_value common_debug_options
[] = {
670 { "tex", DBG_TEX
, "Print texture info" },
671 { "compute", DBG_COMPUTE
, "Print compute info" },
672 { "vm", DBG_VM
, "Print virtual addresses when creating resources" },
673 { "info", DBG_INFO
, "Print driver information" },
676 { "fs", DBG_FS
, "Print fetch shaders" },
677 { "vs", DBG_VS
, "Print vertex shaders" },
678 { "gs", DBG_GS
, "Print geometry shaders" },
679 { "ps", DBG_PS
, "Print pixel shaders" },
680 { "cs", DBG_CS
, "Print compute shaders" },
681 { "tcs", DBG_TCS
, "Print tessellation control shaders" },
682 { "tes", DBG_TES
, "Print tessellation evaluation shaders" },
683 { "noir", DBG_NO_IR
, "Don't print the LLVM IR"},
684 { "notgsi", DBG_NO_TGSI
, "Don't print the TGSI"},
685 { "noasm", DBG_NO_ASM
, "Don't print disassembled shaders"},
686 { "preoptir", DBG_PREOPT_IR
, "Print the LLVM IR before initial optimizations" },
687 { "checkir", DBG_CHECK_IR
, "Enable additional sanity checks on shader IR" },
688 { "nooptvariant", DBG_NO_OPT_VARIANT
, "Disable compiling optimized shader variants." },
690 { "testdma", DBG_TEST_DMA
, "Invoke SDMA tests and exit." },
693 { "nodma", DBG_NO_ASYNC_DMA
, "Disable asynchronous DMA" },
694 { "nohyperz", DBG_NO_HYPERZ
, "Disable Hyper-Z" },
695 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
696 { "noinvalrange", DBG_NO_DISCARD_RANGE
, "Disable handling of INVALIDATE_RANGE map flags" },
697 { "no2d", DBG_NO_2D_TILING
, "Disable 2D tiling" },
698 { "notiling", DBG_NO_TILING
, "Disable tiling" },
699 { "switch_on_eop", DBG_SWITCH_ON_EOP
, "Program WD/IA to switch on end-of-packet." },
700 { "forcedma", DBG_FORCE_DMA
, "Use asynchronous DMA for all operations when possible." },
701 { "precompile", DBG_PRECOMPILE
, "Compile one shader variant at shader creation." },
702 { "nowc", DBG_NO_WC
, "Disable GTT write combining" },
703 { "check_vm", DBG_CHECK_VM
, "Check VM faults and dump debug info." },
704 { "nodcc", DBG_NO_DCC
, "Disable DCC." },
705 { "nodccclear", DBG_NO_DCC_CLEAR
, "Disable DCC fast clear." },
706 { "norbplus", DBG_NO_RB_PLUS
, "Disable RB+ on Stoney." },
707 { "sisched", DBG_SI_SCHED
, "Enable LLVM SI Machine Instruction Scheduler." },
708 { "mono", DBG_MONOLITHIC_SHADERS
, "Use old-style monolithic shaders compiled on demand" },
709 { "noce", DBG_NO_CE
, "Disable the constant engine"},
710 { "unsafemath", DBG_UNSAFE_MATH
, "Enable unsafe math shader optimizations" },
711 { "nodccfb", DBG_NO_DCC_FB
, "Disable separate DCC on the main framebuffer" },
713 DEBUG_NAMED_VALUE_END
/* must be last */
716 static const char* r600_get_vendor(struct pipe_screen
* pscreen
)
721 static const char* r600_get_device_vendor(struct pipe_screen
* pscreen
)
726 static const char* r600_get_chip_name(struct r600_common_screen
*rscreen
)
728 switch (rscreen
->info
.family
) {
729 case CHIP_R600
: return "AMD R600";
730 case CHIP_RV610
: return "AMD RV610";
731 case CHIP_RV630
: return "AMD RV630";
732 case CHIP_RV670
: return "AMD RV670";
733 case CHIP_RV620
: return "AMD RV620";
734 case CHIP_RV635
: return "AMD RV635";
735 case CHIP_RS780
: return "AMD RS780";
736 case CHIP_RS880
: return "AMD RS880";
737 case CHIP_RV770
: return "AMD RV770";
738 case CHIP_RV730
: return "AMD RV730";
739 case CHIP_RV710
: return "AMD RV710";
740 case CHIP_RV740
: return "AMD RV740";
741 case CHIP_CEDAR
: return "AMD CEDAR";
742 case CHIP_REDWOOD
: return "AMD REDWOOD";
743 case CHIP_JUNIPER
: return "AMD JUNIPER";
744 case CHIP_CYPRESS
: return "AMD CYPRESS";
745 case CHIP_HEMLOCK
: return "AMD HEMLOCK";
746 case CHIP_PALM
: return "AMD PALM";
747 case CHIP_SUMO
: return "AMD SUMO";
748 case CHIP_SUMO2
: return "AMD SUMO2";
749 case CHIP_BARTS
: return "AMD BARTS";
750 case CHIP_TURKS
: return "AMD TURKS";
751 case CHIP_CAICOS
: return "AMD CAICOS";
752 case CHIP_CAYMAN
: return "AMD CAYMAN";
753 case CHIP_ARUBA
: return "AMD ARUBA";
754 case CHIP_TAHITI
: return "AMD TAHITI";
755 case CHIP_PITCAIRN
: return "AMD PITCAIRN";
756 case CHIP_VERDE
: return "AMD CAPE VERDE";
757 case CHIP_OLAND
: return "AMD OLAND";
758 case CHIP_HAINAN
: return "AMD HAINAN";
759 case CHIP_BONAIRE
: return "AMD BONAIRE";
760 case CHIP_KAVERI
: return "AMD KAVERI";
761 case CHIP_KABINI
: return "AMD KABINI";
762 case CHIP_HAWAII
: return "AMD HAWAII";
763 case CHIP_MULLINS
: return "AMD MULLINS";
764 case CHIP_TONGA
: return "AMD TONGA";
765 case CHIP_ICELAND
: return "AMD ICELAND";
766 case CHIP_CARRIZO
: return "AMD CARRIZO";
767 case CHIP_FIJI
: return "AMD FIJI";
768 case CHIP_POLARIS10
: return "AMD POLARIS10";
769 case CHIP_POLARIS11
: return "AMD POLARIS11";
770 case CHIP_POLARIS12
: return "AMD POLARIS12";
771 case CHIP_STONEY
: return "AMD STONEY";
772 default: return "AMD unknown";
776 static const char* r600_get_name(struct pipe_screen
* pscreen
)
778 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
780 return rscreen
->renderer_string
;
783 static float r600_get_paramf(struct pipe_screen
* pscreen
,
784 enum pipe_capf param
)
786 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
789 case PIPE_CAPF_MAX_LINE_WIDTH
:
790 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
791 case PIPE_CAPF_MAX_POINT_WIDTH
:
792 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
793 if (rscreen
->family
>= CHIP_CEDAR
)
797 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
799 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
801 case PIPE_CAPF_GUARD_BAND_LEFT
:
802 case PIPE_CAPF_GUARD_BAND_TOP
:
803 case PIPE_CAPF_GUARD_BAND_RIGHT
:
804 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
810 static int r600_get_video_param(struct pipe_screen
*screen
,
811 enum pipe_video_profile profile
,
812 enum pipe_video_entrypoint entrypoint
,
813 enum pipe_video_cap param
)
816 case PIPE_VIDEO_CAP_SUPPORTED
:
817 return vl_profile_supported(screen
, profile
, entrypoint
);
818 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
820 case PIPE_VIDEO_CAP_MAX_WIDTH
:
821 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
822 return vl_video_buffer_max_size(screen
);
823 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
824 return PIPE_FORMAT_NV12
;
825 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
827 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
829 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
831 case PIPE_VIDEO_CAP_MAX_LEVEL
:
832 return vl_level_supported(screen
, profile
);
838 const char *r600_get_llvm_processor_name(enum radeon_family family
)
881 case CHIP_TAHITI
: return "tahiti";
882 case CHIP_PITCAIRN
: return "pitcairn";
883 case CHIP_VERDE
: return "verde";
884 case CHIP_OLAND
: return "oland";
885 case CHIP_HAINAN
: return "hainan";
886 case CHIP_BONAIRE
: return "bonaire";
887 case CHIP_KABINI
: return "kabini";
888 case CHIP_KAVERI
: return "kaveri";
889 case CHIP_HAWAII
: return "hawaii";
892 case CHIP_TONGA
: return "tonga";
893 case CHIP_ICELAND
: return "iceland";
894 case CHIP_CARRIZO
: return "carrizo";
896 return HAVE_LLVM
>= 0x0308 ? "fiji" : "carrizo";
898 return HAVE_LLVM
>= 0x0308 ? "stoney" : "carrizo";
900 return HAVE_LLVM
>= 0x0309 ? "polaris10" : "carrizo";
902 case CHIP_POLARIS12
: /* same as polaris11 */
903 return HAVE_LLVM
>= 0x0309 ? "polaris11" : "carrizo";
909 static int r600_get_compute_param(struct pipe_screen
*screen
,
910 enum pipe_shader_ir ir_type
,
911 enum pipe_compute_cap param
,
914 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
916 //TODO: select these params by asic
918 case PIPE_COMPUTE_CAP_IR_TARGET
: {
921 if (rscreen
->family
<= CHIP_ARUBA
) {
924 if (HAVE_LLVM
< 0x0400) {
927 triple
= "amdgcn-mesa-mesa3d";
930 switch(rscreen
->family
) {
931 /* Clang < 3.6 is missing Hainan in its list of
932 * GPUs, so we need to use the name of a similar GPU.
935 gpu
= r600_get_llvm_processor_name(rscreen
->family
);
939 sprintf(ret
, "%s-%s", gpu
, triple
);
941 /* +2 for dash and terminating NIL byte */
942 return (strlen(triple
) + strlen(gpu
) + 2) * sizeof(char);
944 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
946 uint64_t *grid_dimension
= ret
;
947 grid_dimension
[0] = 3;
949 return 1 * sizeof(uint64_t);
951 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
953 uint64_t *grid_size
= ret
;
954 grid_size
[0] = 65535;
955 grid_size
[1] = 65535;
956 grid_size
[2] = 65535;
958 return 3 * sizeof(uint64_t) ;
960 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
962 uint64_t *block_size
= ret
;
963 if (rscreen
->chip_class
>= SI
&& HAVE_LLVM
>= 0x309 &&
964 ir_type
== PIPE_SHADER_IR_TGSI
) {
965 block_size
[0] = 2048;
966 block_size
[1] = 2048;
967 block_size
[2] = 2048;
974 return 3 * sizeof(uint64_t);
976 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
978 uint64_t *max_threads_per_block
= ret
;
979 if (rscreen
->chip_class
>= SI
&& HAVE_LLVM
>= 0x309 &&
980 ir_type
== PIPE_SHADER_IR_TGSI
)
981 *max_threads_per_block
= 2048;
983 *max_threads_per_block
= 256;
985 return sizeof(uint64_t);
986 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
988 uint32_t *address_bits
= ret
;
989 address_bits
[0] = 32;
990 if (rscreen
->chip_class
>= SI
)
991 address_bits
[0] = 64;
993 return 1 * sizeof(uint32_t);
995 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
997 uint64_t *max_global_size
= ret
;
998 uint64_t max_mem_alloc_size
;
1000 r600_get_compute_param(screen
, ir_type
,
1001 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
1002 &max_mem_alloc_size
);
1004 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1005 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1006 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1007 * make sure we never report more than
1008 * 4 * MAX_MEM_ALLOC_SIZE.
1010 *max_global_size
= MIN2(4 * max_mem_alloc_size
,
1011 MAX2(rscreen
->info
.gart_size
,
1012 rscreen
->info
.vram_size
));
1014 return sizeof(uint64_t);
1016 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
1018 uint64_t *max_local_size
= ret
;
1019 /* Value reported by the closed source driver. */
1020 *max_local_size
= 32768;
1022 return sizeof(uint64_t);
1024 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
1026 uint64_t *max_input_size
= ret
;
1027 /* Value reported by the closed source driver. */
1028 *max_input_size
= 1024;
1030 return sizeof(uint64_t);
1032 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
1034 uint64_t *max_mem_alloc_size
= ret
;
1036 *max_mem_alloc_size
= rscreen
->info
.max_alloc_size
;
1038 return sizeof(uint64_t);
1040 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
1042 uint32_t *max_clock_frequency
= ret
;
1043 *max_clock_frequency
= rscreen
->info
.max_shader_clock
;
1045 return sizeof(uint32_t);
1047 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
1049 uint32_t *max_compute_units
= ret
;
1050 *max_compute_units
= rscreen
->info
.num_good_compute_units
;
1052 return sizeof(uint32_t);
1054 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
1056 uint32_t *images_supported
= ret
;
1057 *images_supported
= 0;
1059 return sizeof(uint32_t);
1060 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
1062 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
1064 uint32_t *subgroup_size
= ret
;
1065 *subgroup_size
= r600_wavefront_size(rscreen
->family
);
1067 return sizeof(uint32_t);
1068 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
1070 uint64_t *max_variable_threads_per_block
= ret
;
1071 if (rscreen
->chip_class
>= SI
&& HAVE_LLVM
>= 0x309 &&
1072 ir_type
== PIPE_SHADER_IR_TGSI
)
1073 *max_variable_threads_per_block
= SI_MAX_VARIABLE_THREADS_PER_BLOCK
;
1075 *max_variable_threads_per_block
= 0;
1077 return sizeof(uint64_t);
1080 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
1084 static uint64_t r600_get_timestamp(struct pipe_screen
*screen
)
1086 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1088 return 1000000 * rscreen
->ws
->query_value(rscreen
->ws
, RADEON_TIMESTAMP
) /
1089 rscreen
->info
.clock_crystal_freq
;
1092 static void r600_fence_reference(struct pipe_screen
*screen
,
1093 struct pipe_fence_handle
**dst
,
1094 struct pipe_fence_handle
*src
)
1096 struct radeon_winsys
*ws
= ((struct r600_common_screen
*)screen
)->ws
;
1097 struct r600_multi_fence
**rdst
= (struct r600_multi_fence
**)dst
;
1098 struct r600_multi_fence
*rsrc
= (struct r600_multi_fence
*)src
;
1100 if (pipe_reference(&(*rdst
)->reference
, &rsrc
->reference
)) {
1101 ws
->fence_reference(&(*rdst
)->gfx
, NULL
);
1102 ws
->fence_reference(&(*rdst
)->sdma
, NULL
);
1108 static boolean
r600_fence_finish(struct pipe_screen
*screen
,
1109 struct pipe_context
*ctx
,
1110 struct pipe_fence_handle
*fence
,
1113 struct radeon_winsys
*rws
= ((struct r600_common_screen
*)screen
)->ws
;
1114 struct r600_multi_fence
*rfence
= (struct r600_multi_fence
*)fence
;
1115 struct r600_common_context
*rctx
=
1116 ctx
? (struct r600_common_context
*)ctx
: NULL
;
1117 int64_t abs_timeout
= os_time_get_absolute_timeout(timeout
);
1120 if (!rws
->fence_wait(rws
, rfence
->sdma
, timeout
))
1123 /* Recompute the timeout after waiting. */
1124 if (timeout
&& timeout
!= PIPE_TIMEOUT_INFINITE
) {
1125 int64_t time
= os_time_get_nano();
1126 timeout
= abs_timeout
> time
? abs_timeout
- time
: 0;
1133 /* Flush the gfx IB if it hasn't been flushed yet. */
1135 rfence
->gfx_unflushed
.ctx
== rctx
&&
1136 rfence
->gfx_unflushed
.ib_index
== rctx
->num_gfx_cs_flushes
) {
1137 rctx
->gfx
.flush(rctx
, timeout
? 0 : RADEON_FLUSH_ASYNC
, NULL
);
1138 rfence
->gfx_unflushed
.ctx
= NULL
;
1143 /* Recompute the timeout after all that. */
1144 if (timeout
&& timeout
!= PIPE_TIMEOUT_INFINITE
) {
1145 int64_t time
= os_time_get_nano();
1146 timeout
= abs_timeout
> time
? abs_timeout
- time
: 0;
1150 return rws
->fence_wait(rws
, rfence
->gfx
, timeout
);
1153 static void r600_query_memory_info(struct pipe_screen
*screen
,
1154 struct pipe_memory_info
*info
)
1156 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1157 struct radeon_winsys
*ws
= rscreen
->ws
;
1158 unsigned vram_usage
, gtt_usage
;
1160 info
->total_device_memory
= rscreen
->info
.vram_size
/ 1024;
1161 info
->total_staging_memory
= rscreen
->info
.gart_size
/ 1024;
1163 /* The real TTM memory usage is somewhat random, because:
1165 * 1) TTM delays freeing memory, because it can only free it after
1168 * 2) The memory usage can be really low if big VRAM evictions are
1169 * taking place, but the real usage is well above the size of VRAM.
1171 * Instead, return statistics of this process.
1173 vram_usage
= ws
->query_value(ws
, RADEON_REQUESTED_VRAM_MEMORY
) / 1024;
1174 gtt_usage
= ws
->query_value(ws
, RADEON_REQUESTED_GTT_MEMORY
) / 1024;
1176 info
->avail_device_memory
=
1177 vram_usage
<= info
->total_device_memory
?
1178 info
->total_device_memory
- vram_usage
: 0;
1179 info
->avail_staging_memory
=
1180 gtt_usage
<= info
->total_staging_memory
?
1181 info
->total_staging_memory
- gtt_usage
: 0;
1183 info
->device_memory_evicted
=
1184 ws
->query_value(ws
, RADEON_NUM_BYTES_MOVED
) / 1024;
1186 if (rscreen
->info
.drm_major
== 3 && rscreen
->info
.drm_minor
>= 4)
1187 info
->nr_device_memory_evictions
=
1188 ws
->query_value(ws
, RADEON_NUM_EVICTIONS
);
1190 /* Just return the number of evicted 64KB pages. */
1191 info
->nr_device_memory_evictions
= info
->device_memory_evicted
/ 64;
1194 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
1195 const struct pipe_resource
*templ
)
1197 if (templ
->target
== PIPE_BUFFER
) {
1198 return r600_buffer_create(screen
, templ
, 256);
1200 return r600_texture_create(screen
, templ
);
1204 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
1205 struct radeon_winsys
*ws
)
1207 char llvm_string
[32] = {}, kernel_version
[128] = {};
1208 struct utsname uname_data
;
1210 ws
->query_info(ws
, &rscreen
->info
);
1212 if (uname(&uname_data
) == 0)
1213 snprintf(kernel_version
, sizeof(kernel_version
),
1214 " / %s", uname_data
.release
);
1217 snprintf(llvm_string
, sizeof(llvm_string
),
1218 ", LLVM %i.%i.%i", (HAVE_LLVM
>> 8) & 0xff,
1219 HAVE_LLVM
& 0xff, MESA_LLVM_VERSION_PATCH
);
1222 snprintf(rscreen
->renderer_string
, sizeof(rscreen
->renderer_string
),
1223 "%s (DRM %i.%i.%i%s%s)",
1224 r600_get_chip_name(rscreen
), rscreen
->info
.drm_major
,
1225 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
,
1226 kernel_version
, llvm_string
);
1228 rscreen
->b
.get_name
= r600_get_name
;
1229 rscreen
->b
.get_vendor
= r600_get_vendor
;
1230 rscreen
->b
.get_device_vendor
= r600_get_device_vendor
;
1231 rscreen
->b
.get_compute_param
= r600_get_compute_param
;
1232 rscreen
->b
.get_paramf
= r600_get_paramf
;
1233 rscreen
->b
.get_timestamp
= r600_get_timestamp
;
1234 rscreen
->b
.fence_finish
= r600_fence_finish
;
1235 rscreen
->b
.fence_reference
= r600_fence_reference
;
1236 rscreen
->b
.resource_destroy
= u_resource_destroy_vtbl
;
1237 rscreen
->b
.resource_from_user_memory
= r600_buffer_from_user_memory
;
1238 rscreen
->b
.query_memory_info
= r600_query_memory_info
;
1240 if (rscreen
->info
.has_uvd
) {
1241 rscreen
->b
.get_video_param
= rvid_get_video_param
;
1242 rscreen
->b
.is_video_format_supported
= rvid_is_format_supported
;
1244 rscreen
->b
.get_video_param
= r600_get_video_param
;
1245 rscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
1248 r600_init_screen_texture_functions(rscreen
);
1249 r600_init_screen_query_functions(rscreen
);
1252 rscreen
->family
= rscreen
->info
.family
;
1253 rscreen
->chip_class
= rscreen
->info
.chip_class
;
1254 rscreen
->debug_flags
= debug_get_flags_option("R600_DEBUG", common_debug_options
, 0);
1256 slab_create_parent(&rscreen
->pool_transfers
, sizeof(struct r600_transfer
), 64);
1258 rscreen
->force_aniso
= MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1259 if (rscreen
->force_aniso
>= 0) {
1260 printf("radeon: Forcing anisotropy filter to %ix\n",
1261 /* round down to a power of two */
1262 1 << util_logbase2(rscreen
->force_aniso
));
1265 util_format_s3tc_init();
1266 pipe_mutex_init(rscreen
->aux_context_lock
);
1267 pipe_mutex_init(rscreen
->gpu_load_mutex
);
1269 if (rscreen
->debug_flags
& DBG_INFO
) {
1270 printf("pci_id = 0x%x\n", rscreen
->info
.pci_id
);
1271 printf("family = %i (%s)\n", rscreen
->info
.family
,
1272 r600_get_chip_name(rscreen
));
1273 printf("chip_class = %i\n", rscreen
->info
.chip_class
);
1274 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen
->info
.gart_size
, 1024*1024));
1275 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen
->info
.vram_size
, 1024*1024));
1276 printf("max_alloc_size = %i MB\n",
1277 (int)DIV_ROUND_UP(rscreen
->info
.max_alloc_size
, 1024*1024));
1278 printf("has_virtual_memory = %i\n", rscreen
->info
.has_virtual_memory
);
1279 printf("gfx_ib_pad_with_type2 = %i\n", rscreen
->info
.gfx_ib_pad_with_type2
);
1280 printf("has_sdma = %i\n", rscreen
->info
.has_sdma
);
1281 printf("has_uvd = %i\n", rscreen
->info
.has_uvd
);
1282 printf("me_fw_version = %i\n", rscreen
->info
.me_fw_version
);
1283 printf("pfp_fw_version = %i\n", rscreen
->info
.pfp_fw_version
);
1284 printf("ce_fw_version = %i\n", rscreen
->info
.ce_fw_version
);
1285 printf("vce_fw_version = %i\n", rscreen
->info
.vce_fw_version
);
1286 printf("vce_harvest_config = %i\n", rscreen
->info
.vce_harvest_config
);
1287 printf("clock_crystal_freq = %i\n", rscreen
->info
.clock_crystal_freq
);
1288 printf("drm = %i.%i.%i\n", rscreen
->info
.drm_major
,
1289 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
);
1290 printf("has_userptr = %i\n", rscreen
->info
.has_userptr
);
1292 printf("r600_max_quad_pipes = %i\n", rscreen
->info
.r600_max_quad_pipes
);
1293 printf("max_shader_clock = %i\n", rscreen
->info
.max_shader_clock
);
1294 printf("num_good_compute_units = %i\n", rscreen
->info
.num_good_compute_units
);
1295 printf("max_se = %i\n", rscreen
->info
.max_se
);
1296 printf("max_sh_per_se = %i\n", rscreen
->info
.max_sh_per_se
);
1298 printf("r600_gb_backend_map = %i\n", rscreen
->info
.r600_gb_backend_map
);
1299 printf("r600_gb_backend_map_valid = %i\n", rscreen
->info
.r600_gb_backend_map_valid
);
1300 printf("r600_num_banks = %i\n", rscreen
->info
.r600_num_banks
);
1301 printf("num_render_backends = %i\n", rscreen
->info
.num_render_backends
);
1302 printf("num_tile_pipes = %i\n", rscreen
->info
.num_tile_pipes
);
1303 printf("pipe_interleave_bytes = %i\n", rscreen
->info
.pipe_interleave_bytes
);
1308 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
)
1310 r600_perfcounters_destroy(rscreen
);
1311 r600_gpu_load_kill_thread(rscreen
);
1313 pipe_mutex_destroy(rscreen
->gpu_load_mutex
);
1314 pipe_mutex_destroy(rscreen
->aux_context_lock
);
1315 rscreen
->aux_context
->destroy(rscreen
->aux_context
);
1317 slab_destroy_parent(&rscreen
->pool_transfers
);
1319 rscreen
->ws
->destroy(rscreen
->ws
);
1323 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
1326 switch (processor
) {
1327 case PIPE_SHADER_VERTEX
:
1328 return (rscreen
->debug_flags
& DBG_VS
) != 0;
1329 case PIPE_SHADER_TESS_CTRL
:
1330 return (rscreen
->debug_flags
& DBG_TCS
) != 0;
1331 case PIPE_SHADER_TESS_EVAL
:
1332 return (rscreen
->debug_flags
& DBG_TES
) != 0;
1333 case PIPE_SHADER_GEOMETRY
:
1334 return (rscreen
->debug_flags
& DBG_GS
) != 0;
1335 case PIPE_SHADER_FRAGMENT
:
1336 return (rscreen
->debug_flags
& DBG_PS
) != 0;
1337 case PIPE_SHADER_COMPUTE
:
1338 return (rscreen
->debug_flags
& DBG_CS
) != 0;
1344 bool r600_extra_shader_checks(struct r600_common_screen
*rscreen
, unsigned processor
)
1346 return (rscreen
->debug_flags
& DBG_CHECK_IR
) ||
1347 r600_can_dump_shader(rscreen
, processor
);
1350 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
1351 uint64_t offset
, uint64_t size
, unsigned value
)
1353 struct r600_common_context
*rctx
= (struct r600_common_context
*)rscreen
->aux_context
;
1355 pipe_mutex_lock(rscreen
->aux_context_lock
);
1356 rctx
->dma_clear_buffer(&rctx
->b
, dst
, offset
, size
, value
);
1357 rscreen
->aux_context
->flush(rscreen
->aux_context
, NULL
, 0);
1358 pipe_mutex_unlock(rscreen
->aux_context_lock
);