src/gallium/drivers/radeon/r600_pipe_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 #include "r600_pipe_common.h"
  28 #include "r600_cs.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_format_s3tc.h"
  32 #include "util/u_upload_mgr.h"
  33 #include "vl/vl_decoder.h"
  34 #include "vl/vl_video_buffer.h"
  35 #include "radeon/radeon_video.h"
  36 #include <inttypes.h>
  37
  38 /*
  39  * pipe_context
  40  */
  41
  42 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
  43 {
  44         /* The number of dwords we already used in the DMA so far. */
  45         num_dw += ctx->rings.dma.cs->cdw;
  46         /* Flush if there's not enough space. */
  47         if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
  48                 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  49         }
  50 }
  51
  52 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
  53 {
  54 }
  55
  56 void r600_preflush_suspend_features(struct r600_common_context *ctx)
  57 {
  58         /* Disable render condition. */
  59         ctx->saved_render_cond = NULL;
  60         ctx->saved_render_cond_cond = FALSE;
  61         ctx->saved_render_cond_mode = 0;
  62         if (ctx->current_render_cond) {
  63                 ctx->saved_render_cond = ctx->current_render_cond;
  64                 ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
  65                 ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
  66                 ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
  67         }
  68
  69         /* suspend queries */
  70         ctx->nontimer_queries_suspended = false;
  71         if (ctx->num_cs_dw_nontimer_queries_suspend) {
  72                 r600_suspend_nontimer_queries(ctx);
  73                 ctx->nontimer_queries_suspended = true;
  74         }
  75
  76         ctx->streamout.suspended = false;
  77         if (ctx->streamout.begin_emitted) {
  78                 r600_emit_streamout_end(ctx);
  79                 ctx->streamout.suspended = true;
  80         }
  81 }
  82
  83 void r600_postflush_resume_features(struct r600_common_context *ctx)
  84 {
  85         if (ctx->streamout.suspended) {
  86                 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
  87                 r600_streamout_buffers_dirty(ctx);
  88         }
  89
  90         /* resume queries */
  91         if (ctx->nontimer_queries_suspended) {
  92                 r600_resume_nontimer_queries(ctx);
  93         }
  94
  95         /* Re-enable render condition. */
  96         if (ctx->saved_render_cond) {
  97                 ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
  98                                           ctx->saved_render_cond_cond,
  99                                           ctx->saved_render_cond_mode);
 100         }
 101 }
 102
 103 static void r600_flush_from_st(struct pipe_context *ctx,
 104                                struct pipe_fence_handle **fence,
 105                                unsigned flags)
 106 {
 107         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 108         unsigned rflags = 0;
 109
 110         if (flags & PIPE_FLUSH_END_OF_FRAME)
 111                 rflags |= RADEON_FLUSH_END_OF_FRAME;
 112
 113         if (rctx->rings.dma.cs) {
 114                 rctx->rings.dma.flush(rctx, rflags, NULL);
 115         }
 116         rctx->rings.gfx.flush(rctx, rflags, fence);
 117 }
 118
 119 static void r600_flush_dma_ring(void *ctx, unsigned flags,
 120                                 struct pipe_fence_handle **fence)
 121 {
 122         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 123         struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
 124
 125         if (!cs->cdw) {
 126                 return;
 127         }
 128
 129         rctx->rings.dma.flushing = true;
 130         rctx->ws->cs_flush(cs, flags, fence, 0);
 131         rctx->rings.dma.flushing = false;
 132 }
 133
 134 bool r600_common_context_init(struct r600_common_context *rctx,
 135                               struct r600_common_screen *rscreen)
 136 {
 137         util_slab_create(&rctx->pool_transfers,
 138                          sizeof(struct r600_transfer), 64,
 139                          UTIL_SLAB_SINGLETHREADED);
 140
 141         rctx->screen = rscreen;
 142         rctx->ws = rscreen->ws;
 143         rctx->family = rscreen->family;
 144         rctx->chip_class = rscreen->chip_class;
 145         rctx->max_db = rscreen->chip_class >= EVERGREEN ? 8 : 4;
 146
 147         rctx->b.transfer_map = u_transfer_map_vtbl;
 148         rctx->b.transfer_flush_region = u_default_transfer_flush_region;
 149         rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
 150         rctx->b.transfer_inline_write = u_default_transfer_inline_write;
 151         rctx->b.memory_barrier = r600_memory_barrier;
 152         rctx->b.flush = r600_flush_from_st;
 153
 154         r600_init_context_texture_functions(rctx);
 155         r600_streamout_init(rctx);
 156         r600_query_init(rctx);
 157
 158         rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
 159                                                                0, PIPE_USAGE_DEFAULT, TRUE);
 160         if (!rctx->allocator_so_filled_size)
 161                 return false;
 162
 163         rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
 164                                         PIPE_BIND_INDEX_BUFFER |
 165                                         PIPE_BIND_CONSTANT_BUFFER);
 166         if (!rctx->uploader)
 167                 return false;
 168
 169         if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
 170                 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA,
 171                                                          r600_flush_dma_ring,
 172                                                          rctx, NULL);
 173                 rctx->rings.dma.flush = r600_flush_dma_ring;
 174         }
 175
 176         return true;
 177 }
 178
 179 void r600_common_context_cleanup(struct r600_common_context *rctx)
 180 {
 181         if (rctx->rings.gfx.cs) {
 182                 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
 183         }
 184         if (rctx->rings.dma.cs) {
 185                 rctx->ws->cs_destroy(rctx->rings.dma.cs);
 186         }
 187
 188         if (rctx->uploader) {
 189                 u_upload_destroy(rctx->uploader);
 190         }
 191
 192         util_slab_destroy(&rctx->pool_transfers);
 193
 194         if (rctx->allocator_so_filled_size) {
 195                 u_suballocator_destroy(rctx->allocator_so_filled_size);
 196         }
 197 }
 198
 199 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 200 {
 201         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 202         struct r600_resource *rr = (struct r600_resource *)r;
 203
 204         if (r == NULL) {
 205                 return;
 206         }
 207
 208         /*
 209          * The idea is to compute a gross estimate of memory requirement of
 210          * each draw call. After each draw call, memory will be precisely
 211          * accounted. So the uncertainty is only on the current draw call.
 212          * In practice this gave very good estimate (+/- 10% of the target
 213          * memory limit).
 214          */
 215         if (rr->domains & RADEON_DOMAIN_GTT) {
 216                 rctx->gtt += rr->buf->size;
 217         }
 218         if (rr->domains & RADEON_DOMAIN_VRAM) {
 219                 rctx->vram += rr->buf->size;
 220         }
 221 }
 222
 223 /*
 224  * pipe_screen
 225  */
 226
 227 static const struct debug_named_value common_debug_options[] = {
 228         /* logging */
 229         { "tex", DBG_TEX, "Print texture info" },
 230         { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
 231         { "compute", DBG_COMPUTE, "Print compute info" },
 232         { "vm", DBG_VM, "Print virtual addresses when creating resources" },
 233         { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
 234
 235         /* features */
 236         { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
 237
 238         /* shaders */
 239         { "fs", DBG_FS, "Print fetch shaders" },
 240         { "vs", DBG_VS, "Print vertex shaders" },
 241         { "gs", DBG_GS, "Print geometry shaders" },
 242         { "ps", DBG_PS, "Print pixel shaders" },
 243         { "cs", DBG_CS, "Print compute shaders" },
 244
 245         { "hyperz", DBG_HYPERZ, "Enable Hyper-Z" },
 246         /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
 247         { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
 248
 249         DEBUG_NAMED_VALUE_END /* must be last */
 250 };
 251
 252 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 253 {
 254         return "X.Org";
 255 }
 256
 257 static const char* r600_get_name(struct pipe_screen* pscreen)
 258 {
 259         struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
 260
 261         switch (rscreen->family) {
 262         case CHIP_R600: return "AMD R600";
 263         case CHIP_RV610: return "AMD RV610";
 264         case CHIP_RV630: return "AMD RV630";
 265         case CHIP_RV670: return "AMD RV670";
 266         case CHIP_RV620: return "AMD RV620";
 267         case CHIP_RV635: return "AMD RV635";
 268         case CHIP_RS780: return "AMD RS780";
 269         case CHIP_RS880: return "AMD RS880";
 270         case CHIP_RV770: return "AMD RV770";
 271         case CHIP_RV730: return "AMD RV730";
 272         case CHIP_RV710: return "AMD RV710";
 273         case CHIP_RV740: return "AMD RV740";
 274         case CHIP_CEDAR: return "AMD CEDAR";
 275         case CHIP_REDWOOD: return "AMD REDWOOD";
 276         case CHIP_JUNIPER: return "AMD JUNIPER";
 277         case CHIP_CYPRESS: return "AMD CYPRESS";
 278         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 279         case CHIP_PALM: return "AMD PALM";
 280         case CHIP_SUMO: return "AMD SUMO";
 281         case CHIP_SUMO2: return "AMD SUMO2";
 282         case CHIP_BARTS: return "AMD BARTS";
 283         case CHIP_TURKS: return "AMD TURKS";
 284         case CHIP_CAICOS: return "AMD CAICOS";
 285         case CHIP_CAYMAN: return "AMD CAYMAN";
 286         case CHIP_ARUBA: return "AMD ARUBA";
 287         case CHIP_TAHITI: return "AMD TAHITI";
 288         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 289         case CHIP_VERDE: return "AMD CAPE VERDE";
 290         case CHIP_OLAND: return "AMD OLAND";
 291         case CHIP_HAINAN: return "AMD HAINAN";
 292         case CHIP_BONAIRE: return "AMD BONAIRE";
 293         case CHIP_KAVERI: return "AMD KAVERI";
 294         case CHIP_KABINI: return "AMD KABINI";
 295         case CHIP_HAWAII: return "AMD HAWAII";
 296         case CHIP_MULLINS: return "AMD MULLINS";
 297         default: return "AMD unknown";
 298         }
 299 }
 300
 301 static float r600_get_paramf(struct pipe_screen* pscreen,
 302                              enum pipe_capf param)
 303 {
 304         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 305
 306         switch (param) {
 307         case PIPE_CAPF_MAX_LINE_WIDTH:
 308         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 309         case PIPE_CAPF_MAX_POINT_WIDTH:
 310         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 311                 if (rscreen->family >= CHIP_CEDAR)
 312                         return 16384.0f;
 313                 else
 314                         return 8192.0f;
 315         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 316                 return 16.0f;
 317         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 318                 return 16.0f;
 319         case PIPE_CAPF_GUARD_BAND_LEFT:
 320         case PIPE_CAPF_GUARD_BAND_TOP:
 321         case PIPE_CAPF_GUARD_BAND_RIGHT:
 322         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 323                 return 0.0f;
 324         }
 325         return 0.0f;
 326 }
 327
 328 static int r600_get_video_param(struct pipe_screen *screen,
 329                                 enum pipe_video_profile profile,
 330                                 enum pipe_video_entrypoint entrypoint,
 331                                 enum pipe_video_cap param)
 332 {
 333         switch (param) {
 334         case PIPE_VIDEO_CAP_SUPPORTED:
 335                 return vl_profile_supported(screen, profile, entrypoint);
 336         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 337                 return 1;
 338         case PIPE_VIDEO_CAP_MAX_WIDTH:
 339         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 340                 return vl_video_buffer_max_size(screen);
 341         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 342                 return PIPE_FORMAT_NV12;
 343         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 344                 return false;
 345         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 346                 return false;
 347         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 348                 return true;
 349         case PIPE_VIDEO_CAP_MAX_LEVEL:
 350                 return vl_level_supported(screen, profile);
 351         default:
 352                 return 0;
 353         }
 354 }
 355
 356 const char *r600_get_llvm_processor_name(enum radeon_family family)
 357 {
 358         switch (family) {
 359         case CHIP_R600:
 360         case CHIP_RV630:
 361         case CHIP_RV635:
 362         case CHIP_RV670:
 363                 return "r600";
 364         case CHIP_RV610:
 365         case CHIP_RV620:
 366         case CHIP_RS780:
 367         case CHIP_RS880:
 368                 return "rs880";
 369         case CHIP_RV710:
 370                 return "rv710";
 371         case CHIP_RV730:
 372                 return "rv730";
 373         case CHIP_RV740:
 374         case CHIP_RV770:
 375                 return "rv770";
 376         case CHIP_PALM:
 377         case CHIP_CEDAR:
 378                 return "cedar";
 379         case CHIP_SUMO:
 380         case CHIP_SUMO2:
 381                 return "sumo";
 382         case CHIP_REDWOOD:
 383                 return "redwood";
 384         case CHIP_JUNIPER:
 385                 return "juniper";
 386         case CHIP_HEMLOCK:
 387         case CHIP_CYPRESS:
 388                 return "cypress";
 389         case CHIP_BARTS:
 390                 return "barts";
 391         case CHIP_TURKS:
 392                 return "turks";
 393         case CHIP_CAICOS:
 394                 return "caicos";
 395         case CHIP_CAYMAN:
 396         case CHIP_ARUBA:
 397                 return "cayman";
 398
 399         case CHIP_TAHITI: return "tahiti";
 400         case CHIP_PITCAIRN: return "pitcairn";
 401         case CHIP_VERDE: return "verde";
 402         case CHIP_OLAND: return "oland";
 403 #if HAVE_LLVM <= 0x0303
 404         default:
 405                 fprintf(stderr, "%s: Unknown chipset = %i, defaulting to Southern Islands\n",
 406                         __func__, family);
 407                 return "SI";
 408 #else
 409         case CHIP_HAINAN: return "hainan";
 410         case CHIP_BONAIRE: return "bonaire";
 411         case CHIP_KABINI: return "kabini";
 412         case CHIP_KAVERI: return "kaveri";
 413         case CHIP_HAWAII: return "hawaii";
 414         case CHIP_MULLINS:
 415 #if HAVE_LLVM >= 0x0305
 416                 return "mullins";
 417 #else
 418                 return "kabini";
 419 #endif
 420         default: return "";
 421 #endif
 422         }
 423 }
 424
 425 static int r600_get_compute_param(struct pipe_screen *screen,
 426         enum pipe_compute_cap param,
 427         void *ret)
 428 {
 429         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
 430
 431         //TODO: select these params by asic
 432         switch (param) {
 433         case PIPE_COMPUTE_CAP_IR_TARGET: {
 434                 const char *gpu = r600_get_llvm_processor_name(rscreen->family);
 435                 if (ret) {
 436                         sprintf(ret, "%s-r600--", gpu);
 437                 }
 438                 return (8 + strlen(gpu)) * sizeof(char);
 439         }
 440         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 441                 if (ret) {
 442                         uint64_t *grid_dimension = ret;
 443                         grid_dimension[0] = 3;
 444                 }
 445                 return 1 * sizeof(uint64_t);
 446
 447         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 448                 if (ret) {
 449                         uint64_t *grid_size = ret;
 450                         grid_size[0] = 65535;
 451                         grid_size[1] = 65535;
 452                         grid_size[2] = 1;
 453                 }
 454                 return 3 * sizeof(uint64_t) ;
 455
 456         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 457                 if (ret) {
 458                         uint64_t *block_size = ret;
 459                         block_size[0] = 256;
 460                         block_size[1] = 256;
 461                         block_size[2] = 256;
 462                 }
 463                 return 3 * sizeof(uint64_t);
 464
 465         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 466                 if (ret) {
 467                         uint64_t *max_threads_per_block = ret;
 468                         *max_threads_per_block = 256;
 469                 }
 470                 return sizeof(uint64_t);
 471
 472         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 473                 if (ret) {
 474                         uint64_t *max_global_size = ret;
 475                         /* XXX: This is what the proprietary driver reports, we
 476                          * may want to use a different value. */
 477                         /* XXX: Not sure what to put here for SI. */
 478                         if (rscreen->chip_class >= SI)
 479                                 *max_global_size = 2000000000;
 480                         else
 481                                 *max_global_size = 201326592;
 482                 }
 483                 return sizeof(uint64_t);
 484
 485         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 486                 if (ret) {
 487                         uint64_t *max_local_size = ret;
 488                         /* Value reported by the closed source driver. */
 489                         *max_local_size = 32768;
 490                 }
 491                 return sizeof(uint64_t);
 492
 493         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 494                 if (ret) {
 495                         uint64_t *max_input_size = ret;
 496                         /* Value reported by the closed source driver. */
 497                         *max_input_size = 1024;
 498                 }
 499                 return sizeof(uint64_t);
 500
 501         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 502                 if (ret) {
 503                         uint64_t max_global_size;
 504                         uint64_t *max_mem_alloc_size = ret;
 505                         r600_get_compute_param(screen, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, &max_global_size);
 506                         /* OpenCL requres this value be at least
 507                          * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
 508                          * I'm really not sure what value to report here, but
 509                          * MAX_GLOBAL_SIZE / 4 seems resonable.
 510                          */
 511                         *max_mem_alloc_size = max_global_size / 4;
 512                 }
 513                 return sizeof(uint64_t);
 514
 515         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 516                 if (ret) {
 517                         uint32_t *max_clock_frequency = ret;
 518                         *max_clock_frequency = rscreen->info.max_sclk;
 519                 }
 520                 return sizeof(uint32_t);
 521
 522         default:
 523                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 524                 return 0;
 525         }
 526 }
 527
 528 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 529 {
 530         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 531
 532         return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
 533                         rscreen->info.r600_clock_crystal_freq;
 534 }
 535
 536 static int r600_get_driver_query_info(struct pipe_screen *screen,
 537                                       unsigned index,
 538                                       struct pipe_driver_query_info *info)
 539 {
 540         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 541         struct pipe_driver_query_info list[] = {
 542                 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
 543                 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->info.vram_size, TRUE},
 544                 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->info.gart_size, TRUE},
 545                 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE},
 546                 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, 0, FALSE},
 547                 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, 0, TRUE},
 548                 {"VRAM-usage", R600_QUERY_VRAM_USAGE, rscreen->info.vram_size, TRUE},
 549                 {"GTT-usage", R600_QUERY_GTT_USAGE, rscreen->info.gart_size, TRUE},
 550         };
 551
 552         if (!info)
 553                 return Elements(list);
 554
 555         if (index >= Elements(list))
 556                 return 0;
 557
 558         *info = list[index];
 559         return 1;
 560 }
 561
 562 static void r600_fence_reference(struct pipe_screen *screen,
 563                                  struct pipe_fence_handle **ptr,
 564                                  struct pipe_fence_handle *fence)
 565 {
 566         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 567
 568         rws->fence_reference(ptr, fence);
 569 }
 570
 571 static boolean r600_fence_signalled(struct pipe_screen *screen,
 572                                     struct pipe_fence_handle *fence)
 573 {
 574         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 575
 576         return rws->fence_wait(rws, fence, 0);
 577 }
 578
 579 static boolean r600_fence_finish(struct pipe_screen *screen,
 580                                  struct pipe_fence_handle *fence,
 581                                  uint64_t timeout)
 582 {
 583         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 584
 585         return rws->fence_wait(rws, fence, timeout);
 586 }
 587
 588 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
 589                                   uint32_t tiling_config)
 590 {
 591         switch ((tiling_config & 0xe) >> 1) {
 592         case 0:
 593                 rscreen->tiling_info.num_channels = 1;
 594                 break;
 595         case 1:
 596                 rscreen->tiling_info.num_channels = 2;
 597                 break;
 598         case 2:
 599                 rscreen->tiling_info.num_channels = 4;
 600                 break;
 601         case 3:
 602                 rscreen->tiling_info.num_channels = 8;
 603                 break;
 604         default:
 605                 return false;
 606         }
 607
 608         switch ((tiling_config & 0x30) >> 4) {
 609         case 0:
 610                 rscreen->tiling_info.num_banks = 4;
 611                 break;
 612         case 1:
 613                 rscreen->tiling_info.num_banks = 8;
 614                 break;
 615         default:
 616                 return false;
 617
 618         }
 619         switch ((tiling_config & 0xc0) >> 6) {
 620         case 0:
 621                 rscreen->tiling_info.group_bytes = 256;
 622                 break;
 623         case 1:
 624                 rscreen->tiling_info.group_bytes = 512;
 625                 break;
 626         default:
 627                 return false;
 628         }
 629         return true;
 630 }
 631
 632 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
 633                                        uint32_t tiling_config)
 634 {
 635         switch (tiling_config & 0xf) {
 636         case 0:
 637                 rscreen->tiling_info.num_channels = 1;
 638                 break;
 639         case 1:
 640                 rscreen->tiling_info.num_channels = 2;
 641                 break;
 642         case 2:
 643                 rscreen->tiling_info.num_channels = 4;
 644                 break;
 645         case 3:
 646                 rscreen->tiling_info.num_channels = 8;
 647                 break;
 648         default:
 649                 return false;
 650         }
 651
 652         switch ((tiling_config & 0xf0) >> 4) {
 653         case 0:
 654                 rscreen->tiling_info.num_banks = 4;
 655                 break;
 656         case 1:
 657                 rscreen->tiling_info.num_banks = 8;
 658                 break;
 659         case 2:
 660                 rscreen->tiling_info.num_banks = 16;
 661                 break;
 662         default:
 663                 return false;
 664         }
 665
 666         switch ((tiling_config & 0xf00) >> 8) {
 667         case 0:
 668                 rscreen->tiling_info.group_bytes = 256;
 669                 break;
 670         case 1:
 671                 rscreen->tiling_info.group_bytes = 512;
 672                 break;
 673         default:
 674                 return false;
 675         }
 676         return true;
 677 }
 678
 679 static bool r600_init_tiling(struct r600_common_screen *rscreen)
 680 {
 681         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 682
 683         /* set default group bytes, overridden by tiling info ioctl */
 684         if (rscreen->chip_class <= R700) {
 685                 rscreen->tiling_info.group_bytes = 256;
 686         } else {
 687                 rscreen->tiling_info.group_bytes = 512;
 688         }
 689
 690         if (!tiling_config)
 691                 return true;
 692
 693         if (rscreen->chip_class <= R700) {
 694                 return r600_interpret_tiling(rscreen, tiling_config);
 695         } else {
 696                 return evergreen_interpret_tiling(rscreen, tiling_config);
 697         }
 698 }
 699
 700 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 701                                                   const struct pipe_resource *templ)
 702 {
 703         if (templ->target == PIPE_BUFFER) {
 704                 return r600_buffer_create(screen, templ, 4096);
 705         } else {
 706                 return r600_texture_create(screen, templ);
 707         }
 708 }
 709
 710 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 711                              struct radeon_winsys *ws)
 712 {
 713         ws->query_info(ws, &rscreen->info);
 714
 715         rscreen->b.get_name = r600_get_name;
 716         rscreen->b.get_vendor = r600_get_vendor;
 717         rscreen->b.get_compute_param = r600_get_compute_param;
 718         rscreen->b.get_paramf = r600_get_paramf;
 719         rscreen->b.get_driver_query_info = r600_get_driver_query_info;
 720         rscreen->b.get_timestamp = r600_get_timestamp;
 721         rscreen->b.fence_finish = r600_fence_finish;
 722         rscreen->b.fence_reference = r600_fence_reference;
 723         rscreen->b.fence_signalled = r600_fence_signalled;
 724         rscreen->b.resource_destroy = u_resource_destroy_vtbl;
 725
 726         if (rscreen->info.has_uvd) {
 727                 rscreen->b.get_video_param = rvid_get_video_param;
 728                 rscreen->b.is_video_format_supported = rvid_is_format_supported;
 729         } else {
 730                 rscreen->b.get_video_param = r600_get_video_param;
 731                 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 732         }
 733
 734         r600_init_screen_texture_functions(rscreen);
 735
 736         rscreen->ws = ws;
 737         rscreen->family = rscreen->info.family;
 738         rscreen->chip_class = rscreen->info.chip_class;
 739         rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
 740
 741         if (!r600_init_tiling(rscreen)) {
 742                 return false;
 743         }
 744         util_format_s3tc_init();
 745         pipe_mutex_init(rscreen->aux_context_lock);
 746
 747         if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
 748                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
 749                                                                                 PIPE_BIND_CUSTOM,
 750                                                                                 PIPE_USAGE_STAGING,
 751                                                                                 4096);
 752                 if (rscreen->trace_bo) {
 753                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 754                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 755                 }
 756         }
 757
 758         return true;
 759 }
 760
 761 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
 762 {
 763         pipe_mutex_destroy(rscreen->aux_context_lock);
 764         rscreen->aux_context->destroy(rscreen->aux_context);
 765
 766         if (rscreen->trace_bo) {
 767                 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 768                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 769         }
 770
 771         rscreen->ws->destroy(rscreen->ws);
 772         FREE(rscreen);
 773 }
 774
 775 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
 776 {
 777         struct tgsi_parse_context parse;
 778
 779         if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
 780                 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
 781                 return ~0;
 782         }
 783         return parse.FullHeader.Processor.Processor;
 784 }
 785
 786 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 787                           const struct tgsi_token *tokens)
 788 {
 789         /* Compute shader don't have tgsi_tokens */
 790         if (!tokens)
 791                 return (rscreen->debug_flags & DBG_CS) != 0;
 792
 793         switch (tgsi_get_processor_type(tokens)) {
 794         case TGSI_PROCESSOR_VERTEX:
 795                 return (rscreen->debug_flags & DBG_VS) != 0;
 796         case TGSI_PROCESSOR_GEOMETRY:
 797                 return (rscreen->debug_flags & DBG_GS) != 0;
 798         case TGSI_PROCESSOR_FRAGMENT:
 799                 return (rscreen->debug_flags & DBG_PS) != 0;
 800         case TGSI_PROCESSOR_COMPUTE:
 801                 return (rscreen->debug_flags & DBG_CS) != 0;
 802         default:
 803                 return false;
 804         }
 805 }
 806
 807 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 808                               unsigned offset, unsigned size, unsigned value)
 809 {
 810         struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
 811
 812         pipe_mutex_lock(rscreen->aux_context_lock);
 813         rctx->clear_buffer(&rctx->b, dst, offset, size, value);
 814         rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
 815         pipe_mutex_unlock(rscreen->aux_context_lock);
 816 }