2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
27 #include "r600_pipe_common.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
45 struct r600_multi_fence
{
46 struct pipe_reference reference
;
47 struct pipe_fence_handle
*gfx
;
48 struct pipe_fence_handle
*sdma
;
52 * shader binary helpers.
54 void radeon_shader_binary_init(struct radeon_shader_binary
*b
)
56 memset(b
, 0, sizeof(*b
));
59 void radeon_shader_binary_clean(struct radeon_shader_binary
*b
)
66 FREE(b
->global_symbol_offsets
);
68 FREE(b
->disasm_string
);
75 void r600_draw_rectangle(struct blitter_context
*blitter
,
76 int x1
, int y1
, int x2
, int y2
, float depth
,
77 enum blitter_attrib_type type
,
78 const union pipe_color_union
*attrib
)
80 struct r600_common_context
*rctx
=
81 (struct r600_common_context
*)util_blitter_get_pipe(blitter
);
82 struct pipe_viewport_state viewport
;
83 struct pipe_resource
*buf
= NULL
;
87 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
88 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
92 /* Some operations (like color resolve on r6xx) don't work
93 * with the conventional primitive types.
94 * One that works is PT_RECTLIST, which we use here. */
97 viewport
.scale
[0] = 1.0f
;
98 viewport
.scale
[1] = 1.0f
;
99 viewport
.scale
[2] = 1.0f
;
100 viewport
.translate
[0] = 0.0f
;
101 viewport
.translate
[1] = 0.0f
;
102 viewport
.translate
[2] = 0.0f
;
103 rctx
->b
.set_viewport_states(&rctx
->b
, 0, 1, &viewport
);
105 /* Upload vertices. The hw rectangle has only 3 vertices,
106 * I guess the 4th one is derived from the first 3.
107 * The vertex specification should match u_blitter's vertex element state. */
108 u_upload_alloc(rctx
->uploader
, 0, sizeof(float) * 24, 256, &offset
, &buf
, (void**)&vb
);
128 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
129 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
130 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
134 util_draw_vertex_buffer(&rctx
->b
, NULL
, buf
, blitter
->vb_slot
, offset
,
135 R600_PRIM_RECTANGLE_LIST
, 3, 2);
136 pipe_resource_reference(&buf
, NULL
);
139 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
)
141 /* Flush the GFX IB if it's not empty. */
142 if (ctx
->gfx
.cs
->cdw
> ctx
->initial_gfx_cs_size
)
143 ctx
->gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
145 /* Flush if there's not enough space. */
146 if ((num_dw
+ ctx
->dma
.cs
->cdw
) > ctx
->dma
.cs
->max_dw
) {
147 ctx
->dma
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
148 assert((num_dw
+ ctx
->dma
.cs
->cdw
) <= ctx
->dma
.cs
->max_dw
);
152 static void r600_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
156 void r600_preflush_suspend_features(struct r600_common_context
*ctx
)
158 /* suspend queries */
159 if (!LIST_IS_EMPTY(&ctx
->active_queries
))
160 r600_suspend_queries(ctx
);
162 ctx
->streamout
.suspended
= false;
163 if (ctx
->streamout
.begin_emitted
) {
164 r600_emit_streamout_end(ctx
);
165 ctx
->streamout
.suspended
= true;
169 void r600_postflush_resume_features(struct r600_common_context
*ctx
)
171 if (ctx
->streamout
.suspended
) {
172 ctx
->streamout
.append_bitmask
= ctx
->streamout
.enabled_mask
;
173 r600_streamout_buffers_dirty(ctx
);
177 if (!LIST_IS_EMPTY(&ctx
->active_queries
))
178 r600_resume_queries(ctx
);
181 static void r600_flush_from_st(struct pipe_context
*ctx
,
182 struct pipe_fence_handle
**fence
,
185 struct pipe_screen
*screen
= ctx
->screen
;
186 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
188 struct pipe_fence_handle
*gfx_fence
= NULL
;
189 struct pipe_fence_handle
*sdma_fence
= NULL
;
191 if (flags
& PIPE_FLUSH_END_OF_FRAME
)
192 rflags
|= RADEON_FLUSH_END_OF_FRAME
;
195 rctx
->dma
.flush(rctx
, rflags
, fence
? &sdma_fence
: NULL
);
197 rctx
->gfx
.flush(rctx
, rflags
, fence
? &gfx_fence
: NULL
);
199 /* Both engines can signal out of order, so we need to keep both fences. */
200 if (gfx_fence
|| sdma_fence
) {
201 struct r600_multi_fence
*multi_fence
=
202 CALLOC_STRUCT(r600_multi_fence
);
206 multi_fence
->reference
.count
= 1;
207 multi_fence
->gfx
= gfx_fence
;
208 multi_fence
->sdma
= sdma_fence
;
210 screen
->fence_reference(screen
, fence
, NULL
);
211 *fence
= (struct pipe_fence_handle
*)multi_fence
;
215 static void r600_flush_dma_ring(void *ctx
, unsigned flags
,
216 struct pipe_fence_handle
**fence
)
218 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
219 struct radeon_winsys_cs
*cs
= rctx
->dma
.cs
;
222 rctx
->ws
->cs_flush(cs
, flags
, &rctx
->last_sdma_fence
);
224 rctx
->ws
->fence_reference(fence
, rctx
->last_sdma_fence
);
227 static enum pipe_reset_status
r600_get_reset_status(struct pipe_context
*ctx
)
229 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
230 unsigned latest
= rctx
->ws
->query_value(rctx
->ws
,
231 RADEON_GPU_RESET_COUNTER
);
233 if (rctx
->gpu_reset_counter
== latest
)
234 return PIPE_NO_RESET
;
236 rctx
->gpu_reset_counter
= latest
;
237 return PIPE_UNKNOWN_CONTEXT_RESET
;
240 static void r600_set_debug_callback(struct pipe_context
*ctx
,
241 const struct pipe_debug_callback
*cb
)
243 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
248 memset(&rctx
->debug
, 0, sizeof(rctx
->debug
));
251 bool r600_common_context_init(struct r600_common_context
*rctx
,
252 struct r600_common_screen
*rscreen
)
254 util_slab_create(&rctx
->pool_transfers
,
255 sizeof(struct r600_transfer
), 64,
256 UTIL_SLAB_SINGLETHREADED
);
258 rctx
->screen
= rscreen
;
259 rctx
->ws
= rscreen
->ws
;
260 rctx
->family
= rscreen
->family
;
261 rctx
->chip_class
= rscreen
->chip_class
;
263 if (rscreen
->chip_class
>= CIK
)
264 rctx
->max_db
= MAX2(8, rscreen
->info
.num_render_backends
);
265 else if (rscreen
->chip_class
>= EVERGREEN
)
270 rctx
->b
.invalidate_resource
= r600_invalidate_resource
;
271 rctx
->b
.transfer_map
= u_transfer_map_vtbl
;
272 rctx
->b
.transfer_flush_region
= u_transfer_flush_region_vtbl
;
273 rctx
->b
.transfer_unmap
= u_transfer_unmap_vtbl
;
274 rctx
->b
.transfer_inline_write
= u_default_transfer_inline_write
;
275 rctx
->b
.memory_barrier
= r600_memory_barrier
;
276 rctx
->b
.flush
= r600_flush_from_st
;
277 rctx
->b
.set_debug_callback
= r600_set_debug_callback
;
279 if (rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
>= 43) {
280 rctx
->b
.get_device_reset_status
= r600_get_reset_status
;
281 rctx
->gpu_reset_counter
=
282 rctx
->ws
->query_value(rctx
->ws
,
283 RADEON_GPU_RESET_COUNTER
);
286 LIST_INITHEAD(&rctx
->texture_buffers
);
288 r600_init_context_texture_functions(rctx
);
289 r600_init_viewport_functions(rctx
);
290 r600_streamout_init(rctx
);
291 r600_query_init(rctx
);
292 cayman_init_msaa(&rctx
->b
);
294 rctx
->allocator_so_filled_size
= u_suballocator_create(&rctx
->b
, 4096, 4,
295 0, PIPE_USAGE_DEFAULT
, TRUE
);
296 if (!rctx
->allocator_so_filled_size
)
299 rctx
->uploader
= u_upload_create(&rctx
->b
, 1024 * 1024,
300 PIPE_BIND_INDEX_BUFFER
|
301 PIPE_BIND_CONSTANT_BUFFER
, PIPE_USAGE_STREAM
);
305 rctx
->ctx
= rctx
->ws
->ctx_create(rctx
->ws
);
309 if (rscreen
->info
.has_sdma
&& !(rscreen
->debug_flags
& DBG_NO_ASYNC_DMA
)) {
310 rctx
->dma
.cs
= rctx
->ws
->cs_create(rctx
->ctx
, RING_DMA
,
313 rctx
->dma
.flush
= r600_flush_dma_ring
;
319 void r600_common_context_cleanup(struct r600_common_context
*rctx
)
322 rctx
->ws
->cs_destroy(rctx
->gfx
.cs
);
324 rctx
->ws
->cs_destroy(rctx
->dma
.cs
);
326 rctx
->ws
->ctx_destroy(rctx
->ctx
);
328 if (rctx
->uploader
) {
329 u_upload_destroy(rctx
->uploader
);
332 util_slab_destroy(&rctx
->pool_transfers
);
334 if (rctx
->allocator_so_filled_size
) {
335 u_suballocator_destroy(rctx
->allocator_so_filled_size
);
337 rctx
->ws
->fence_reference(&rctx
->last_sdma_fence
, NULL
);
340 void r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
342 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
343 struct r600_resource
*rr
= (struct r600_resource
*)r
;
350 * The idea is to compute a gross estimate of memory requirement of
351 * each draw call. After each draw call, memory will be precisely
352 * accounted. So the uncertainty is only on the current draw call.
353 * In practice this gave very good estimate (+/- 10% of the target
356 if (rr
->domains
& RADEON_DOMAIN_GTT
) {
357 rctx
->gtt
+= rr
->buf
->size
;
359 if (rr
->domains
& RADEON_DOMAIN_VRAM
) {
360 rctx
->vram
+= rr
->buf
->size
;
368 static const struct debug_named_value common_debug_options
[] = {
370 { "tex", DBG_TEX
, "Print texture info" },
371 { "compute", DBG_COMPUTE
, "Print compute info" },
372 { "vm", DBG_VM
, "Print virtual addresses when creating resources" },
373 { "info", DBG_INFO
, "Print driver information" },
376 { "fs", DBG_FS
, "Print fetch shaders" },
377 { "vs", DBG_VS
, "Print vertex shaders" },
378 { "gs", DBG_GS
, "Print geometry shaders" },
379 { "ps", DBG_PS
, "Print pixel shaders" },
380 { "cs", DBG_CS
, "Print compute shaders" },
381 { "tcs", DBG_TCS
, "Print tessellation control shaders" },
382 { "tes", DBG_TES
, "Print tessellation evaluation shaders" },
383 { "noir", DBG_NO_IR
, "Don't print the LLVM IR"},
384 { "notgsi", DBG_NO_TGSI
, "Don't print the TGSI"},
385 { "noasm", DBG_NO_ASM
, "Don't print disassembled shaders"},
386 { "preoptir", DBG_PREOPT_IR
, "Print the LLVM IR before initial optimizations" },
389 { "nodma", DBG_NO_ASYNC_DMA
, "Disable asynchronous DMA" },
390 { "nohyperz", DBG_NO_HYPERZ
, "Disable Hyper-Z" },
391 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
392 { "noinvalrange", DBG_NO_DISCARD_RANGE
, "Disable handling of INVALIDATE_RANGE map flags" },
393 { "no2d", DBG_NO_2D_TILING
, "Disable 2D tiling" },
394 { "notiling", DBG_NO_TILING
, "Disable tiling" },
395 { "switch_on_eop", DBG_SWITCH_ON_EOP
, "Program WD/IA to switch on end-of-packet." },
396 { "forcedma", DBG_FORCE_DMA
, "Use asynchronous DMA for all operations when possible." },
397 { "precompile", DBG_PRECOMPILE
, "Compile one shader variant at shader creation." },
398 { "nowc", DBG_NO_WC
, "Disable GTT write combining" },
399 { "check_vm", DBG_CHECK_VM
, "Check VM faults and dump debug info." },
400 { "nodcc", DBG_NO_DCC
, "Disable DCC." },
401 { "nodccclear", DBG_NO_DCC_CLEAR
, "Disable DCC fast clear." },
402 { "norbplus", DBG_NO_RB_PLUS
, "Disable RB+ on Stoney." },
403 { "sisched", DBG_SI_SCHED
, "Enable LLVM SI Machine Instruction Scheduler." },
404 { "mono", DBG_MONOLITHIC_SHADERS
, "Use old-style monolithic shaders compiled on demand" },
405 { "noce", DBG_NO_CE
, "Disable the constant engine"},
407 DEBUG_NAMED_VALUE_END
/* must be last */
410 static const char* r600_get_vendor(struct pipe_screen
* pscreen
)
415 static const char* r600_get_device_vendor(struct pipe_screen
* pscreen
)
420 static const char* r600_get_chip_name(struct r600_common_screen
*rscreen
)
422 switch (rscreen
->info
.family
) {
423 case CHIP_R600
: return "AMD R600";
424 case CHIP_RV610
: return "AMD RV610";
425 case CHIP_RV630
: return "AMD RV630";
426 case CHIP_RV670
: return "AMD RV670";
427 case CHIP_RV620
: return "AMD RV620";
428 case CHIP_RV635
: return "AMD RV635";
429 case CHIP_RS780
: return "AMD RS780";
430 case CHIP_RS880
: return "AMD RS880";
431 case CHIP_RV770
: return "AMD RV770";
432 case CHIP_RV730
: return "AMD RV730";
433 case CHIP_RV710
: return "AMD RV710";
434 case CHIP_RV740
: return "AMD RV740";
435 case CHIP_CEDAR
: return "AMD CEDAR";
436 case CHIP_REDWOOD
: return "AMD REDWOOD";
437 case CHIP_JUNIPER
: return "AMD JUNIPER";
438 case CHIP_CYPRESS
: return "AMD CYPRESS";
439 case CHIP_HEMLOCK
: return "AMD HEMLOCK";
440 case CHIP_PALM
: return "AMD PALM";
441 case CHIP_SUMO
: return "AMD SUMO";
442 case CHIP_SUMO2
: return "AMD SUMO2";
443 case CHIP_BARTS
: return "AMD BARTS";
444 case CHIP_TURKS
: return "AMD TURKS";
445 case CHIP_CAICOS
: return "AMD CAICOS";
446 case CHIP_CAYMAN
: return "AMD CAYMAN";
447 case CHIP_ARUBA
: return "AMD ARUBA";
448 case CHIP_TAHITI
: return "AMD TAHITI";
449 case CHIP_PITCAIRN
: return "AMD PITCAIRN";
450 case CHIP_VERDE
: return "AMD CAPE VERDE";
451 case CHIP_OLAND
: return "AMD OLAND";
452 case CHIP_HAINAN
: return "AMD HAINAN";
453 case CHIP_BONAIRE
: return "AMD BONAIRE";
454 case CHIP_KAVERI
: return "AMD KAVERI";
455 case CHIP_KABINI
: return "AMD KABINI";
456 case CHIP_HAWAII
: return "AMD HAWAII";
457 case CHIP_MULLINS
: return "AMD MULLINS";
458 case CHIP_TONGA
: return "AMD TONGA";
459 case CHIP_ICELAND
: return "AMD ICELAND";
460 case CHIP_CARRIZO
: return "AMD CARRIZO";
461 case CHIP_FIJI
: return "AMD FIJI";
462 case CHIP_POLARIS10
: return "AMD POLARIS10";
463 case CHIP_POLARIS11
: return "AMD POLARIS11";
464 case CHIP_STONEY
: return "AMD STONEY";
465 default: return "AMD unknown";
469 static const char* r600_get_name(struct pipe_screen
* pscreen
)
471 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
473 return rscreen
->renderer_string
;
476 static float r600_get_paramf(struct pipe_screen
* pscreen
,
477 enum pipe_capf param
)
479 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
482 case PIPE_CAPF_MAX_LINE_WIDTH
:
483 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
484 case PIPE_CAPF_MAX_POINT_WIDTH
:
485 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
486 if (rscreen
->family
>= CHIP_CEDAR
)
490 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
492 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
494 case PIPE_CAPF_GUARD_BAND_LEFT
:
495 case PIPE_CAPF_GUARD_BAND_TOP
:
496 case PIPE_CAPF_GUARD_BAND_RIGHT
:
497 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
503 static int r600_get_video_param(struct pipe_screen
*screen
,
504 enum pipe_video_profile profile
,
505 enum pipe_video_entrypoint entrypoint
,
506 enum pipe_video_cap param
)
509 case PIPE_VIDEO_CAP_SUPPORTED
:
510 return vl_profile_supported(screen
, profile
, entrypoint
);
511 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
513 case PIPE_VIDEO_CAP_MAX_WIDTH
:
514 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
515 return vl_video_buffer_max_size(screen
);
516 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
517 return PIPE_FORMAT_NV12
;
518 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
520 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
522 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
524 case PIPE_VIDEO_CAP_MAX_LEVEL
:
525 return vl_level_supported(screen
, profile
);
531 const char *r600_get_llvm_processor_name(enum radeon_family family
)
574 case CHIP_TAHITI
: return "tahiti";
575 case CHIP_PITCAIRN
: return "pitcairn";
576 case CHIP_VERDE
: return "verde";
577 case CHIP_OLAND
: return "oland";
578 case CHIP_HAINAN
: return "hainan";
579 case CHIP_BONAIRE
: return "bonaire";
580 case CHIP_KABINI
: return "kabini";
581 case CHIP_KAVERI
: return "kaveri";
582 case CHIP_HAWAII
: return "hawaii";
585 case CHIP_TONGA
: return "tonga";
586 case CHIP_ICELAND
: return "iceland";
587 case CHIP_CARRIZO
: return "carrizo";
588 #if HAVE_LLVM <= 0x0307
589 case CHIP_FIJI
: return "tonga";
590 case CHIP_STONEY
: return "carrizo";
592 case CHIP_FIJI
: return "fiji";
593 case CHIP_STONEY
: return "stoney";
595 #if HAVE_LLVM <= 0x0308
596 case CHIP_POLARIS10
: return "tonga";
597 case CHIP_POLARIS11
: return "tonga";
599 case CHIP_POLARIS10
: return "polaris10";
600 case CHIP_POLARIS11
: return "polaris11";
606 static int r600_get_compute_param(struct pipe_screen
*screen
,
607 enum pipe_shader_ir ir_type
,
608 enum pipe_compute_cap param
,
611 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
613 //TODO: select these params by asic
615 case PIPE_COMPUTE_CAP_IR_TARGET
: {
618 if (rscreen
->family
<= CHIP_ARUBA
) {
623 switch(rscreen
->family
) {
624 /* Clang < 3.6 is missing Hainan in its list of
625 * GPUs, so we need to use the name of a similar GPU.
628 gpu
= r600_get_llvm_processor_name(rscreen
->family
);
632 sprintf(ret
, "%s-%s", gpu
, triple
);
634 /* +2 for dash and terminating NIL byte */
635 return (strlen(triple
) + strlen(gpu
) + 2) * sizeof(char);
637 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
639 uint64_t *grid_dimension
= ret
;
640 grid_dimension
[0] = 3;
642 return 1 * sizeof(uint64_t);
644 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
646 uint64_t *grid_size
= ret
;
647 grid_size
[0] = 65535;
648 grid_size
[1] = 65535;
649 grid_size
[2] = 65535;
651 return 3 * sizeof(uint64_t) ;
653 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
655 uint64_t *block_size
= ret
;
656 if (rscreen
->chip_class
>= SI
&& HAVE_LLVM
>= 0x309 &&
657 ir_type
== PIPE_SHADER_IR_TGSI
) {
658 block_size
[0] = 2048;
659 block_size
[1] = 2048;
660 block_size
[2] = 2048;
667 return 3 * sizeof(uint64_t);
669 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
671 uint64_t *max_threads_per_block
= ret
;
672 if (rscreen
->chip_class
>= SI
&& HAVE_LLVM
>= 0x309 &&
673 ir_type
== PIPE_SHADER_IR_TGSI
)
674 *max_threads_per_block
= 2048;
676 *max_threads_per_block
= 256;
678 return sizeof(uint64_t);
680 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
682 uint64_t *max_global_size
= ret
;
683 uint64_t max_mem_alloc_size
;
685 r600_get_compute_param(screen
, ir_type
,
686 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
687 &max_mem_alloc_size
);
689 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
690 * 1/4 of the MAX_GLOBAL_SIZE. Since the
691 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
692 * make sure we never report more than
693 * 4 * MAX_MEM_ALLOC_SIZE.
695 *max_global_size
= MIN2(4 * max_mem_alloc_size
,
696 rscreen
->info
.gart_size
+
697 rscreen
->info
.vram_size
);
699 return sizeof(uint64_t);
701 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
703 uint64_t *max_local_size
= ret
;
704 /* Value reported by the closed source driver. */
705 *max_local_size
= 32768;
707 return sizeof(uint64_t);
709 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
711 uint64_t *max_input_size
= ret
;
712 /* Value reported by the closed source driver. */
713 *max_input_size
= 1024;
715 return sizeof(uint64_t);
717 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
719 uint64_t *max_mem_alloc_size
= ret
;
721 /* XXX: The limit in older kernels is 256 MB. We
722 * should add a query here for newer kernels.
724 *max_mem_alloc_size
= 256 * 1024 * 1024;
726 return sizeof(uint64_t);
728 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
730 uint32_t *max_clock_frequency
= ret
;
731 *max_clock_frequency
= rscreen
->info
.max_shader_clock
;
733 return sizeof(uint32_t);
735 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
737 uint32_t *max_compute_units
= ret
;
738 *max_compute_units
= rscreen
->info
.num_good_compute_units
;
740 return sizeof(uint32_t);
742 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
744 uint32_t *images_supported
= ret
;
745 *images_supported
= 0;
747 return sizeof(uint32_t);
748 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
750 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
752 uint32_t *subgroup_size
= ret
;
753 *subgroup_size
= r600_wavefront_size(rscreen
->family
);
755 return sizeof(uint32_t);
758 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
762 static uint64_t r600_get_timestamp(struct pipe_screen
*screen
)
764 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
766 return 1000000 * rscreen
->ws
->query_value(rscreen
->ws
, RADEON_TIMESTAMP
) /
767 rscreen
->info
.clock_crystal_freq
;
770 static void r600_fence_reference(struct pipe_screen
*screen
,
771 struct pipe_fence_handle
**dst
,
772 struct pipe_fence_handle
*src
)
774 struct radeon_winsys
*ws
= ((struct r600_common_screen
*)screen
)->ws
;
775 struct r600_multi_fence
**rdst
= (struct r600_multi_fence
**)dst
;
776 struct r600_multi_fence
*rsrc
= (struct r600_multi_fence
*)src
;
778 if (pipe_reference(&(*rdst
)->reference
, &rsrc
->reference
)) {
779 ws
->fence_reference(&(*rdst
)->gfx
, NULL
);
780 ws
->fence_reference(&(*rdst
)->sdma
, NULL
);
786 static boolean
r600_fence_finish(struct pipe_screen
*screen
,
787 struct pipe_fence_handle
*fence
,
790 struct radeon_winsys
*rws
= ((struct r600_common_screen
*)screen
)->ws
;
791 struct r600_multi_fence
*rfence
= (struct r600_multi_fence
*)fence
;
792 int64_t abs_timeout
= os_time_get_absolute_timeout(timeout
);
795 if (!rws
->fence_wait(rws
, rfence
->sdma
, timeout
))
798 /* Recompute the timeout after waiting. */
799 if (timeout
&& timeout
!= PIPE_TIMEOUT_INFINITE
) {
800 int64_t time
= os_time_get_nano();
801 timeout
= abs_timeout
> time
? abs_timeout
- time
: 0;
808 return rws
->fence_wait(rws
, rfence
->gfx
, timeout
);
811 static void r600_query_memory_info(struct pipe_screen
*screen
,
812 struct pipe_memory_info
*info
)
814 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
815 struct radeon_winsys
*ws
= rscreen
->ws
;
816 unsigned vram_usage
, gtt_usage
;
818 info
->total_device_memory
= rscreen
->info
.vram_size
/ 1024;
819 info
->total_staging_memory
= rscreen
->info
.gart_size
/ 1024;
821 /* The real TTM memory usage is somewhat random, because:
823 * 1) TTM delays freeing memory, because it can only free it after
826 * 2) The memory usage can be really low if big VRAM evictions are
827 * taking place, but the real usage is well above the size of VRAM.
829 * Instead, return statistics of this process.
831 vram_usage
= ws
->query_value(ws
, RADEON_REQUESTED_VRAM_MEMORY
) / 1024;
832 gtt_usage
= ws
->query_value(ws
, RADEON_REQUESTED_GTT_MEMORY
) / 1024;
834 info
->avail_device_memory
=
835 vram_usage
<= info
->total_device_memory
?
836 info
->total_device_memory
- vram_usage
: 0;
837 info
->avail_staging_memory
=
838 gtt_usage
<= info
->total_staging_memory
?
839 info
->total_staging_memory
- gtt_usage
: 0;
841 info
->device_memory_evicted
=
842 ws
->query_value(ws
, RADEON_NUM_BYTES_MOVED
) / 1024;
843 /* Just return the number of evicted 64KB pages. */
844 info
->nr_device_memory_evictions
= info
->device_memory_evicted
/ 64;
847 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
848 const struct pipe_resource
*templ
)
850 if (templ
->target
== PIPE_BUFFER
) {
851 return r600_buffer_create(screen
, templ
, 4096);
853 return r600_texture_create(screen
, templ
);
857 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
858 struct radeon_winsys
*ws
)
860 char llvm_string
[32] = {};
862 ws
->query_info(ws
, &rscreen
->info
);
865 snprintf(llvm_string
, sizeof(llvm_string
),
866 ", LLVM %i.%i.%i", (HAVE_LLVM
>> 8) & 0xff,
867 HAVE_LLVM
& 0xff, MESA_LLVM_VERSION_PATCH
);
870 snprintf(rscreen
->renderer_string
, sizeof(rscreen
->renderer_string
),
871 "%s (DRM %i.%i.%i%s)",
872 r600_get_chip_name(rscreen
), rscreen
->info
.drm_major
,
873 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
,
876 rscreen
->b
.get_name
= r600_get_name
;
877 rscreen
->b
.get_vendor
= r600_get_vendor
;
878 rscreen
->b
.get_device_vendor
= r600_get_device_vendor
;
879 rscreen
->b
.get_compute_param
= r600_get_compute_param
;
880 rscreen
->b
.get_paramf
= r600_get_paramf
;
881 rscreen
->b
.get_timestamp
= r600_get_timestamp
;
882 rscreen
->b
.fence_finish
= r600_fence_finish
;
883 rscreen
->b
.fence_reference
= r600_fence_reference
;
884 rscreen
->b
.resource_destroy
= u_resource_destroy_vtbl
;
885 rscreen
->b
.resource_from_user_memory
= r600_buffer_from_user_memory
;
886 rscreen
->b
.query_memory_info
= r600_query_memory_info
;
888 if (rscreen
->info
.has_uvd
) {
889 rscreen
->b
.get_video_param
= rvid_get_video_param
;
890 rscreen
->b
.is_video_format_supported
= rvid_is_format_supported
;
892 rscreen
->b
.get_video_param
= r600_get_video_param
;
893 rscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
896 r600_init_screen_texture_functions(rscreen
);
897 r600_init_screen_query_functions(rscreen
);
900 rscreen
->family
= rscreen
->info
.family
;
901 rscreen
->chip_class
= rscreen
->info
.chip_class
;
902 rscreen
->debug_flags
= debug_get_flags_option("R600_DEBUG", common_debug_options
, 0);
904 rscreen
->force_aniso
= MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
905 if (rscreen
->force_aniso
>= 0) {
906 printf("radeon: Forcing anisotropy filter to %ix\n",
907 /* round down to a power of two */
908 1 << util_logbase2(rscreen
->force_aniso
));
911 util_format_s3tc_init();
912 pipe_mutex_init(rscreen
->aux_context_lock
);
913 pipe_mutex_init(rscreen
->gpu_load_mutex
);
915 if (rscreen
->debug_flags
& DBG_INFO
) {
916 printf("pci_id = 0x%x\n", rscreen
->info
.pci_id
);
917 printf("family = %i (%s)\n", rscreen
->info
.family
,
918 r600_get_chip_name(rscreen
));
919 printf("chip_class = %i\n", rscreen
->info
.chip_class
);
920 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen
->info
.gart_size
, 1024*1024));
921 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen
->info
.vram_size
, 1024*1024));
922 printf("has_virtual_memory = %i\n", rscreen
->info
.has_virtual_memory
);
923 printf("gfx_ib_pad_with_type2 = %i\n", rscreen
->info
.gfx_ib_pad_with_type2
);
924 printf("has_sdma = %i\n", rscreen
->info
.has_sdma
);
925 printf("has_uvd = %i\n", rscreen
->info
.has_uvd
);
926 printf("vce_fw_version = %i\n", rscreen
->info
.vce_fw_version
);
927 printf("vce_harvest_config = %i\n", rscreen
->info
.vce_harvest_config
);
928 printf("clock_crystal_freq = %i\n", rscreen
->info
.clock_crystal_freq
);
929 printf("drm = %i.%i.%i\n", rscreen
->info
.drm_major
,
930 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
);
931 printf("has_userptr = %i\n", rscreen
->info
.has_userptr
);
933 printf("r600_max_quad_pipes = %i\n", rscreen
->info
.r600_max_quad_pipes
);
934 printf("max_shader_clock = %i\n", rscreen
->info
.max_shader_clock
);
935 printf("num_good_compute_units = %i\n", rscreen
->info
.num_good_compute_units
);
936 printf("max_se = %i\n", rscreen
->info
.max_se
);
937 printf("max_sh_per_se = %i\n", rscreen
->info
.max_sh_per_se
);
939 printf("r600_gb_backend_map = %i\n", rscreen
->info
.r600_gb_backend_map
);
940 printf("r600_gb_backend_map_valid = %i\n", rscreen
->info
.r600_gb_backend_map_valid
);
941 printf("r600_num_banks = %i\n", rscreen
->info
.r600_num_banks
);
942 printf("num_render_backends = %i\n", rscreen
->info
.num_render_backends
);
943 printf("num_tile_pipes = %i\n", rscreen
->info
.num_tile_pipes
);
944 printf("pipe_interleave_bytes = %i\n", rscreen
->info
.pipe_interleave_bytes
);
945 printf("si_tile_mode_array_valid = %i\n", rscreen
->info
.si_tile_mode_array_valid
);
946 printf("cik_macrotile_mode_array_valid = %i\n", rscreen
->info
.cik_macrotile_mode_array_valid
);
951 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
)
953 r600_perfcounters_destroy(rscreen
);
954 r600_gpu_load_kill_thread(rscreen
);
956 pipe_mutex_destroy(rscreen
->gpu_load_mutex
);
957 pipe_mutex_destroy(rscreen
->aux_context_lock
);
958 rscreen
->aux_context
->destroy(rscreen
->aux_context
);
960 rscreen
->ws
->destroy(rscreen
->ws
);
964 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
968 case PIPE_SHADER_VERTEX
:
969 return (rscreen
->debug_flags
& DBG_VS
) != 0;
970 case PIPE_SHADER_TESS_CTRL
:
971 return (rscreen
->debug_flags
& DBG_TCS
) != 0;
972 case PIPE_SHADER_TESS_EVAL
:
973 return (rscreen
->debug_flags
& DBG_TES
) != 0;
974 case PIPE_SHADER_GEOMETRY
:
975 return (rscreen
->debug_flags
& DBG_GS
) != 0;
976 case PIPE_SHADER_FRAGMENT
:
977 return (rscreen
->debug_flags
& DBG_PS
) != 0;
978 case PIPE_SHADER_COMPUTE
:
979 return (rscreen
->debug_flags
& DBG_CS
) != 0;
985 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
986 uint64_t offset
, uint64_t size
, unsigned value
,
989 struct r600_common_context
*rctx
= (struct r600_common_context
*)rscreen
->aux_context
;
991 pipe_mutex_lock(rscreen
->aux_context_lock
);
992 rctx
->clear_buffer(&rctx
->b
, dst
, offset
, size
, value
, is_framebuffer
);
993 rscreen
->aux_context
->flush(rscreen
->aux_context
, NULL
, 0);
994 pipe_mutex_unlock(rscreen
->aux_context_lock
);