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[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 struct r600_multi_fence {
47 struct pipe_reference reference;
48 struct pipe_fence_handle *gfx;
49 struct pipe_fence_handle *sdma;
50 };
51
52 /*
53 * shader binary helpers.
54 */
55 void radeon_shader_binary_init(struct radeon_shader_binary *b)
56 {
57 memset(b, 0, sizeof(*b));
58 }
59
60 void radeon_shader_binary_clean(struct radeon_shader_binary *b)
61 {
62 if (!b)
63 return;
64 FREE(b->code);
65 FREE(b->config);
66 FREE(b->rodata);
67 FREE(b->global_symbol_offsets);
68 FREE(b->relocs);
69 FREE(b->disasm_string);
70 FREE(b->llvm_ir_string);
71 }
72
73 /*
74 * pipe_context
75 */
76
77 void r600_draw_rectangle(struct blitter_context *blitter,
78 int x1, int y1, int x2, int y2, float depth,
79 enum blitter_attrib_type type,
80 const union pipe_color_union *attrib)
81 {
82 struct r600_common_context *rctx =
83 (struct r600_common_context*)util_blitter_get_pipe(blitter);
84 struct pipe_viewport_state viewport;
85 struct pipe_resource *buf = NULL;
86 unsigned offset = 0;
87 float *vb;
88
89 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
90 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
91 return;
92 }
93
94 /* Some operations (like color resolve on r6xx) don't work
95 * with the conventional primitive types.
96 * One that works is PT_RECTLIST, which we use here. */
97
98 /* setup viewport */
99 viewport.scale[0] = 1.0f;
100 viewport.scale[1] = 1.0f;
101 viewport.scale[2] = 1.0f;
102 viewport.translate[0] = 0.0f;
103 viewport.translate[1] = 0.0f;
104 viewport.translate[2] = 0.0f;
105 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
106
107 /* Upload vertices. The hw rectangle has only 3 vertices,
108 * I guess the 4th one is derived from the first 3.
109 * The vertex specification should match u_blitter's vertex element state. */
110 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, 256, &offset, &buf, (void**)&vb);
111 if (!buf)
112 return;
113
114 vb[0] = x1;
115 vb[1] = y1;
116 vb[2] = depth;
117 vb[3] = 1;
118
119 vb[8] = x1;
120 vb[9] = y2;
121 vb[10] = depth;
122 vb[11] = 1;
123
124 vb[16] = x2;
125 vb[17] = y1;
126 vb[18] = depth;
127 vb[19] = 1;
128
129 if (attrib) {
130 memcpy(vb+4, attrib->f, sizeof(float)*4);
131 memcpy(vb+12, attrib->f, sizeof(float)*4);
132 memcpy(vb+20, attrib->f, sizeof(float)*4);
133 }
134
135 /* draw */
136 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
137 R600_PRIM_RECTANGLE_LIST, 3, 2);
138 pipe_resource_reference(&buf, NULL);
139 }
140
141 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
142 struct r600_resource *dst, struct r600_resource *src)
143 {
144 uint64_t vram = 0, gtt = 0;
145
146 if (dst) {
147 vram += dst->vram_usage;
148 gtt += dst->gart_usage;
149 }
150 if (src) {
151 vram += src->vram_usage;
152 gtt += src->gart_usage;
153 }
154
155 /* Flush the GFX IB if DMA depends on it. */
156 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
157 ((dst &&
158 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
159 RADEON_USAGE_READWRITE)) ||
160 (src &&
161 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
162 RADEON_USAGE_WRITE))))
163 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
164
165 /* Flush if there's not enough space, or if the memory usage per IB
166 * is too large.
167 */
168 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
169 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
170 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
171 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
172 }
173
174 /* If GPUVM is not supported, the CS checker needs 2 entries
175 * in the buffer list per packet, which has to be done manually.
176 */
177 if (ctx->screen->info.has_virtual_memory) {
178 if (dst)
179 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
180 RADEON_USAGE_WRITE,
181 RADEON_PRIO_SDMA_BUFFER);
182 if (src)
183 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
184 RADEON_USAGE_READ,
185 RADEON_PRIO_SDMA_BUFFER);
186 }
187 }
188
189 /* This is required to prevent read-after-write hazards. */
190 void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
191 {
192 struct radeon_winsys_cs *cs = rctx->dma.cs;
193
194 /* done at the end of DMA calls, so increment this. */
195 rctx->num_dma_calls++;
196
197 /* IBs using too little memory are limited by the IB submission overhead.
198 * IBs using too much memory are limited by the kernel/TTM overhead.
199 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
200 *
201 * This heuristic makes sure that DMA requests are executed
202 * very soon after the call is made and lowers memory usage.
203 * It improves texture upload performance by keeping the DMA
204 * engine busy while uploads are being submitted.
205 */
206 if (cs->used_vram + cs->used_gart > 64 * 1024 * 1024) {
207 rctx->dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
208 return;
209 }
210
211 r600_need_dma_space(rctx, 1, NULL, NULL);
212
213 if (!radeon_emitted(cs, 0)) /* empty queue */
214 return;
215
216 /* NOP waits for idle on Evergreen and later. */
217 if (rctx->chip_class >= CIK)
218 radeon_emit(cs, 0x00000000); /* NOP */
219 else if (rctx->chip_class >= EVERGREEN)
220 radeon_emit(cs, 0xf0000000); /* NOP */
221 else {
222 /* TODO: R600-R700 should use the FENCE packet.
223 * CS checker support is required. */
224 }
225 }
226
227 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
228 {
229 }
230
231 void r600_preflush_suspend_features(struct r600_common_context *ctx)
232 {
233 /* suspend queries */
234 if (!LIST_IS_EMPTY(&ctx->active_queries))
235 r600_suspend_queries(ctx);
236
237 ctx->streamout.suspended = false;
238 if (ctx->streamout.begin_emitted) {
239 r600_emit_streamout_end(ctx);
240 ctx->streamout.suspended = true;
241 }
242 }
243
244 void r600_postflush_resume_features(struct r600_common_context *ctx)
245 {
246 if (ctx->streamout.suspended) {
247 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
248 r600_streamout_buffers_dirty(ctx);
249 }
250
251 /* resume queries */
252 if (!LIST_IS_EMPTY(&ctx->active_queries))
253 r600_resume_queries(ctx);
254 }
255
256 static void r600_flush_from_st(struct pipe_context *ctx,
257 struct pipe_fence_handle **fence,
258 unsigned flags)
259 {
260 struct pipe_screen *screen = ctx->screen;
261 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
262 unsigned rflags = 0;
263 struct pipe_fence_handle *gfx_fence = NULL;
264 struct pipe_fence_handle *sdma_fence = NULL;
265
266 if (flags & PIPE_FLUSH_END_OF_FRAME)
267 rflags |= RADEON_FLUSH_END_OF_FRAME;
268 if (flags & PIPE_FLUSH_DEFERRED)
269 rflags |= RADEON_FLUSH_ASYNC;
270
271 if (rctx->dma.cs) {
272 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
273 }
274 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
275
276 /* Both engines can signal out of order, so we need to keep both fences. */
277 if (gfx_fence || sdma_fence) {
278 struct r600_multi_fence *multi_fence =
279 CALLOC_STRUCT(r600_multi_fence);
280 if (!multi_fence)
281 return;
282
283 multi_fence->reference.count = 1;
284 multi_fence->gfx = gfx_fence;
285 multi_fence->sdma = sdma_fence;
286
287 screen->fence_reference(screen, fence, NULL);
288 *fence = (struct pipe_fence_handle*)multi_fence;
289 }
290 }
291
292 static void r600_flush_dma_ring(void *ctx, unsigned flags,
293 struct pipe_fence_handle **fence)
294 {
295 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
296 struct radeon_winsys_cs *cs = rctx->dma.cs;
297 struct radeon_saved_cs saved;
298 bool check_vm =
299 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
300 rctx->check_vm_faults;
301
302 if (!radeon_emitted(cs, 0)) {
303 if (fence)
304 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
305 return;
306 }
307
308 if (check_vm)
309 radeon_save_cs(rctx->ws, cs, &saved);
310
311 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
312 if (fence)
313 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
314
315 if (check_vm) {
316 /* Use conservative timeout 800ms, after which we won't wait any
317 * longer and assume the GPU is hung.
318 */
319 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
320
321 rctx->check_vm_faults(rctx, &saved, RING_DMA);
322 radeon_clear_saved_cs(&saved);
323 }
324 }
325
326 /**
327 * Store a linearized copy of all chunks of \p cs together with the buffer
328 * list in \p saved.
329 */
330 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
331 struct radeon_saved_cs *saved)
332 {
333 void *buf;
334 unsigned i;
335
336 /* Save the IB chunks. */
337 saved->num_dw = cs->prev_dw + cs->current.cdw;
338 saved->ib = MALLOC(4 * saved->num_dw);
339 if (!saved->ib)
340 goto oom;
341
342 buf = saved->ib;
343 for (i = 0; i < cs->num_prev; ++i) {
344 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
345 buf += cs->prev[i].cdw;
346 }
347 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
348
349 /* Save the buffer list. */
350 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
351 saved->bo_list = CALLOC(saved->bo_count,
352 sizeof(saved->bo_list[0]));
353 if (!saved->bo_list) {
354 FREE(saved->ib);
355 goto oom;
356 }
357 ws->cs_get_buffer_list(cs, saved->bo_list);
358
359 return;
360
361 oom:
362 fprintf(stderr, "%s: out of memory\n", __func__);
363 memset(saved, 0, sizeof(*saved));
364 }
365
366 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
367 {
368 FREE(saved->ib);
369 FREE(saved->bo_list);
370
371 memset(saved, 0, sizeof(*saved));
372 }
373
374 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
375 {
376 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
377 unsigned latest = rctx->ws->query_value(rctx->ws,
378 RADEON_GPU_RESET_COUNTER);
379
380 if (rctx->gpu_reset_counter == latest)
381 return PIPE_NO_RESET;
382
383 rctx->gpu_reset_counter = latest;
384 return PIPE_UNKNOWN_CONTEXT_RESET;
385 }
386
387 static void r600_set_debug_callback(struct pipe_context *ctx,
388 const struct pipe_debug_callback *cb)
389 {
390 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
391
392 if (cb)
393 rctx->debug = *cb;
394 else
395 memset(&rctx->debug, 0, sizeof(rctx->debug));
396 }
397
398 bool r600_common_context_init(struct r600_common_context *rctx,
399 struct r600_common_screen *rscreen,
400 unsigned context_flags)
401 {
402 util_slab_create(&rctx->pool_transfers,
403 sizeof(struct r600_transfer), 64,
404 UTIL_SLAB_SINGLETHREADED);
405
406 rctx->screen = rscreen;
407 rctx->ws = rscreen->ws;
408 rctx->family = rscreen->family;
409 rctx->chip_class = rscreen->chip_class;
410
411 if (rscreen->chip_class >= CIK)
412 rctx->max_db = MAX2(8, rscreen->info.num_render_backends);
413 else if (rscreen->chip_class >= EVERGREEN)
414 rctx->max_db = 8;
415 else
416 rctx->max_db = 4;
417
418 rctx->b.invalidate_resource = r600_invalidate_resource;
419 rctx->b.transfer_map = u_transfer_map_vtbl;
420 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
421 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
422 rctx->b.texture_subdata = u_default_texture_subdata;
423 rctx->b.memory_barrier = r600_memory_barrier;
424 rctx->b.flush = r600_flush_from_st;
425 rctx->b.set_debug_callback = r600_set_debug_callback;
426
427 /* evergreen_compute.c has a special codepath for global buffers.
428 * Everything else can use the direct path.
429 */
430 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
431 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
432 rctx->b.buffer_subdata = u_default_buffer_subdata;
433 else
434 rctx->b.buffer_subdata = r600_buffer_subdata;
435
436 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
437 rctx->b.get_device_reset_status = r600_get_reset_status;
438 rctx->gpu_reset_counter =
439 rctx->ws->query_value(rctx->ws,
440 RADEON_GPU_RESET_COUNTER);
441 }
442
443 LIST_INITHEAD(&rctx->texture_buffers);
444
445 r600_init_context_texture_functions(rctx);
446 r600_init_viewport_functions(rctx);
447 r600_streamout_init(rctx);
448 r600_query_init(rctx);
449 cayman_init_msaa(&rctx->b);
450
451 rctx->allocator_zeroed_memory =
452 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
453 0, PIPE_USAGE_DEFAULT, true);
454 if (!rctx->allocator_zeroed_memory)
455 return false;
456
457 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024,
458 PIPE_BIND_INDEX_BUFFER |
459 PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
460 if (!rctx->uploader)
461 return false;
462
463 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
464 if (!rctx->ctx)
465 return false;
466
467 if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
468 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
469 r600_flush_dma_ring,
470 rctx);
471 rctx->dma.flush = r600_flush_dma_ring;
472 }
473
474 p_atomic_inc(&rscreen->num_contexts);
475 return true;
476 }
477
478 void r600_common_context_cleanup(struct r600_common_context *rctx)
479 {
480 unsigned i,j;
481
482 p_atomic_dec(&rctx->screen->num_contexts);
483
484 /* Release DCC stats. */
485 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
486 assert(!rctx->dcc_stats[i].query_active);
487
488 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
489 if (rctx->dcc_stats[i].ps_stats[j])
490 rctx->b.destroy_query(&rctx->b,
491 rctx->dcc_stats[i].ps_stats[j]);
492
493 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
494 }
495
496 if (rctx->gfx.cs)
497 rctx->ws->cs_destroy(rctx->gfx.cs);
498 if (rctx->dma.cs)
499 rctx->ws->cs_destroy(rctx->dma.cs);
500 if (rctx->ctx)
501 rctx->ws->ctx_destroy(rctx->ctx);
502
503 if (rctx->uploader) {
504 u_upload_destroy(rctx->uploader);
505 }
506
507 util_slab_destroy(&rctx->pool_transfers);
508
509 if (rctx->allocator_zeroed_memory) {
510 u_suballocator_destroy(rctx->allocator_zeroed_memory);
511 }
512 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
513 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
514 }
515
516 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
517 {
518 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
519 struct r600_resource *rr = (struct r600_resource *)r;
520
521 if (!r) {
522 return;
523 }
524
525 /*
526 * The idea is to compute a gross estimate of memory requirement of
527 * each draw call. After each draw call, memory will be precisely
528 * accounted. So the uncertainty is only on the current draw call.
529 * In practice this gave very good estimate (+/- 10% of the target
530 * memory limit).
531 */
532 rctx->vram += rr->vram_usage;
533 rctx->gtt += rr->gart_usage;
534 }
535
536 /*
537 * pipe_screen
538 */
539
540 static const struct debug_named_value common_debug_options[] = {
541 /* logging */
542 { "tex", DBG_TEX, "Print texture info" },
543 { "compute", DBG_COMPUTE, "Print compute info" },
544 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
545 { "info", DBG_INFO, "Print driver information" },
546
547 /* shaders */
548 { "fs", DBG_FS, "Print fetch shaders" },
549 { "vs", DBG_VS, "Print vertex shaders" },
550 { "gs", DBG_GS, "Print geometry shaders" },
551 { "ps", DBG_PS, "Print pixel shaders" },
552 { "cs", DBG_CS, "Print compute shaders" },
553 { "tcs", DBG_TCS, "Print tessellation control shaders" },
554 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
555 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
556 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
557 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
558 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
559
560 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
561
562 /* features */
563 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
564 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
565 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
566 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
567 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
568 { "notiling", DBG_NO_TILING, "Disable tiling" },
569 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
570 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
571 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
572 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
573 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
574 { "nodcc", DBG_NO_DCC, "Disable DCC." },
575 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
576 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
577 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
578 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
579 { "noce", DBG_NO_CE, "Disable the constant engine"},
580 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
581 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
582
583 DEBUG_NAMED_VALUE_END /* must be last */
584 };
585
586 static const char* r600_get_vendor(struct pipe_screen* pscreen)
587 {
588 return "X.Org";
589 }
590
591 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
592 {
593 return "AMD";
594 }
595
596 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
597 {
598 switch (rscreen->info.family) {
599 case CHIP_R600: return "AMD R600";
600 case CHIP_RV610: return "AMD RV610";
601 case CHIP_RV630: return "AMD RV630";
602 case CHIP_RV670: return "AMD RV670";
603 case CHIP_RV620: return "AMD RV620";
604 case CHIP_RV635: return "AMD RV635";
605 case CHIP_RS780: return "AMD RS780";
606 case CHIP_RS880: return "AMD RS880";
607 case CHIP_RV770: return "AMD RV770";
608 case CHIP_RV730: return "AMD RV730";
609 case CHIP_RV710: return "AMD RV710";
610 case CHIP_RV740: return "AMD RV740";
611 case CHIP_CEDAR: return "AMD CEDAR";
612 case CHIP_REDWOOD: return "AMD REDWOOD";
613 case CHIP_JUNIPER: return "AMD JUNIPER";
614 case CHIP_CYPRESS: return "AMD CYPRESS";
615 case CHIP_HEMLOCK: return "AMD HEMLOCK";
616 case CHIP_PALM: return "AMD PALM";
617 case CHIP_SUMO: return "AMD SUMO";
618 case CHIP_SUMO2: return "AMD SUMO2";
619 case CHIP_BARTS: return "AMD BARTS";
620 case CHIP_TURKS: return "AMD TURKS";
621 case CHIP_CAICOS: return "AMD CAICOS";
622 case CHIP_CAYMAN: return "AMD CAYMAN";
623 case CHIP_ARUBA: return "AMD ARUBA";
624 case CHIP_TAHITI: return "AMD TAHITI";
625 case CHIP_PITCAIRN: return "AMD PITCAIRN";
626 case CHIP_VERDE: return "AMD CAPE VERDE";
627 case CHIP_OLAND: return "AMD OLAND";
628 case CHIP_HAINAN: return "AMD HAINAN";
629 case CHIP_BONAIRE: return "AMD BONAIRE";
630 case CHIP_KAVERI: return "AMD KAVERI";
631 case CHIP_KABINI: return "AMD KABINI";
632 case CHIP_HAWAII: return "AMD HAWAII";
633 case CHIP_MULLINS: return "AMD MULLINS";
634 case CHIP_TONGA: return "AMD TONGA";
635 case CHIP_ICELAND: return "AMD ICELAND";
636 case CHIP_CARRIZO: return "AMD CARRIZO";
637 case CHIP_FIJI: return "AMD FIJI";
638 case CHIP_POLARIS10: return "AMD POLARIS10";
639 case CHIP_POLARIS11: return "AMD POLARIS11";
640 case CHIP_STONEY: return "AMD STONEY";
641 default: return "AMD unknown";
642 }
643 }
644
645 static const char* r600_get_name(struct pipe_screen* pscreen)
646 {
647 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
648
649 return rscreen->renderer_string;
650 }
651
652 static float r600_get_paramf(struct pipe_screen* pscreen,
653 enum pipe_capf param)
654 {
655 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
656
657 switch (param) {
658 case PIPE_CAPF_MAX_LINE_WIDTH:
659 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
660 case PIPE_CAPF_MAX_POINT_WIDTH:
661 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
662 if (rscreen->family >= CHIP_CEDAR)
663 return 16384.0f;
664 else
665 return 8192.0f;
666 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
667 return 16.0f;
668 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
669 return 16.0f;
670 case PIPE_CAPF_GUARD_BAND_LEFT:
671 case PIPE_CAPF_GUARD_BAND_TOP:
672 case PIPE_CAPF_GUARD_BAND_RIGHT:
673 case PIPE_CAPF_GUARD_BAND_BOTTOM:
674 return 0.0f;
675 }
676 return 0.0f;
677 }
678
679 static int r600_get_video_param(struct pipe_screen *screen,
680 enum pipe_video_profile profile,
681 enum pipe_video_entrypoint entrypoint,
682 enum pipe_video_cap param)
683 {
684 switch (param) {
685 case PIPE_VIDEO_CAP_SUPPORTED:
686 return vl_profile_supported(screen, profile, entrypoint);
687 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
688 return 1;
689 case PIPE_VIDEO_CAP_MAX_WIDTH:
690 case PIPE_VIDEO_CAP_MAX_HEIGHT:
691 return vl_video_buffer_max_size(screen);
692 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
693 return PIPE_FORMAT_NV12;
694 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
695 return false;
696 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
697 return false;
698 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
699 return true;
700 case PIPE_VIDEO_CAP_MAX_LEVEL:
701 return vl_level_supported(screen, profile);
702 default:
703 return 0;
704 }
705 }
706
707 const char *r600_get_llvm_processor_name(enum radeon_family family)
708 {
709 switch (family) {
710 case CHIP_R600:
711 case CHIP_RV630:
712 case CHIP_RV635:
713 case CHIP_RV670:
714 return "r600";
715 case CHIP_RV610:
716 case CHIP_RV620:
717 case CHIP_RS780:
718 case CHIP_RS880:
719 return "rs880";
720 case CHIP_RV710:
721 return "rv710";
722 case CHIP_RV730:
723 return "rv730";
724 case CHIP_RV740:
725 case CHIP_RV770:
726 return "rv770";
727 case CHIP_PALM:
728 case CHIP_CEDAR:
729 return "cedar";
730 case CHIP_SUMO:
731 case CHIP_SUMO2:
732 return "sumo";
733 case CHIP_REDWOOD:
734 return "redwood";
735 case CHIP_JUNIPER:
736 return "juniper";
737 case CHIP_HEMLOCK:
738 case CHIP_CYPRESS:
739 return "cypress";
740 case CHIP_BARTS:
741 return "barts";
742 case CHIP_TURKS:
743 return "turks";
744 case CHIP_CAICOS:
745 return "caicos";
746 case CHIP_CAYMAN:
747 case CHIP_ARUBA:
748 return "cayman";
749
750 case CHIP_TAHITI: return "tahiti";
751 case CHIP_PITCAIRN: return "pitcairn";
752 case CHIP_VERDE: return "verde";
753 case CHIP_OLAND: return "oland";
754 case CHIP_HAINAN: return "hainan";
755 case CHIP_BONAIRE: return "bonaire";
756 case CHIP_KABINI: return "kabini";
757 case CHIP_KAVERI: return "kaveri";
758 case CHIP_HAWAII: return "hawaii";
759 case CHIP_MULLINS:
760 return "mullins";
761 case CHIP_TONGA: return "tonga";
762 case CHIP_ICELAND: return "iceland";
763 case CHIP_CARRIZO: return "carrizo";
764 #if HAVE_LLVM <= 0x0307
765 case CHIP_FIJI: return "tonga";
766 case CHIP_STONEY: return "carrizo";
767 #else
768 case CHIP_FIJI: return "fiji";
769 case CHIP_STONEY: return "stoney";
770 #endif
771 #if HAVE_LLVM <= 0x0308
772 case CHIP_POLARIS10: return "tonga";
773 case CHIP_POLARIS11: return "tonga";
774 #else
775 case CHIP_POLARIS10: return "polaris10";
776 case CHIP_POLARIS11: return "polaris11";
777 #endif
778 default: return "";
779 }
780 }
781
782 static int r600_get_compute_param(struct pipe_screen *screen,
783 enum pipe_shader_ir ir_type,
784 enum pipe_compute_cap param,
785 void *ret)
786 {
787 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
788
789 //TODO: select these params by asic
790 switch (param) {
791 case PIPE_COMPUTE_CAP_IR_TARGET: {
792 const char *gpu;
793 const char *triple;
794 if (rscreen->family <= CHIP_ARUBA) {
795 triple = "r600--";
796 } else {
797 triple = "amdgcn--";
798 }
799 switch(rscreen->family) {
800 /* Clang < 3.6 is missing Hainan in its list of
801 * GPUs, so we need to use the name of a similar GPU.
802 */
803 default:
804 gpu = r600_get_llvm_processor_name(rscreen->family);
805 break;
806 }
807 if (ret) {
808 sprintf(ret, "%s-%s", gpu, triple);
809 }
810 /* +2 for dash and terminating NIL byte */
811 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
812 }
813 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
814 if (ret) {
815 uint64_t *grid_dimension = ret;
816 grid_dimension[0] = 3;
817 }
818 return 1 * sizeof(uint64_t);
819
820 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
821 if (ret) {
822 uint64_t *grid_size = ret;
823 grid_size[0] = 65535;
824 grid_size[1] = 65535;
825 grid_size[2] = 65535;
826 }
827 return 3 * sizeof(uint64_t) ;
828
829 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
830 if (ret) {
831 uint64_t *block_size = ret;
832 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
833 ir_type == PIPE_SHADER_IR_TGSI) {
834 block_size[0] = 2048;
835 block_size[1] = 2048;
836 block_size[2] = 2048;
837 } else {
838 block_size[0] = 256;
839 block_size[1] = 256;
840 block_size[2] = 256;
841 }
842 }
843 return 3 * sizeof(uint64_t);
844
845 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
846 if (ret) {
847 uint64_t *max_threads_per_block = ret;
848 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
849 ir_type == PIPE_SHADER_IR_TGSI)
850 *max_threads_per_block = 2048;
851 else
852 *max_threads_per_block = 256;
853 }
854 return sizeof(uint64_t);
855
856 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
857 if (ret) {
858 uint64_t *max_global_size = ret;
859 uint64_t max_mem_alloc_size;
860
861 r600_get_compute_param(screen, ir_type,
862 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
863 &max_mem_alloc_size);
864
865 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
866 * 1/4 of the MAX_GLOBAL_SIZE. Since the
867 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
868 * make sure we never report more than
869 * 4 * MAX_MEM_ALLOC_SIZE.
870 */
871 *max_global_size = MIN2(4 * max_mem_alloc_size,
872 MAX2(rscreen->info.gart_size,
873 rscreen->info.vram_size));
874 }
875 return sizeof(uint64_t);
876
877 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
878 if (ret) {
879 uint64_t *max_local_size = ret;
880 /* Value reported by the closed source driver. */
881 *max_local_size = 32768;
882 }
883 return sizeof(uint64_t);
884
885 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
886 if (ret) {
887 uint64_t *max_input_size = ret;
888 /* Value reported by the closed source driver. */
889 *max_input_size = 1024;
890 }
891 return sizeof(uint64_t);
892
893 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
894 if (ret) {
895 uint64_t *max_mem_alloc_size = ret;
896
897 *max_mem_alloc_size = rscreen->info.max_alloc_size;
898 }
899 return sizeof(uint64_t);
900
901 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
902 if (ret) {
903 uint32_t *max_clock_frequency = ret;
904 *max_clock_frequency = rscreen->info.max_shader_clock;
905 }
906 return sizeof(uint32_t);
907
908 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
909 if (ret) {
910 uint32_t *max_compute_units = ret;
911 *max_compute_units = rscreen->info.num_good_compute_units;
912 }
913 return sizeof(uint32_t);
914
915 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
916 if (ret) {
917 uint32_t *images_supported = ret;
918 *images_supported = 0;
919 }
920 return sizeof(uint32_t);
921 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
922 break; /* unused */
923 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
924 if (ret) {
925 uint32_t *subgroup_size = ret;
926 *subgroup_size = r600_wavefront_size(rscreen->family);
927 }
928 return sizeof(uint32_t);
929 }
930
931 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
932 return 0;
933 }
934
935 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
936 {
937 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
938
939 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
940 rscreen->info.clock_crystal_freq;
941 }
942
943 static void r600_fence_reference(struct pipe_screen *screen,
944 struct pipe_fence_handle **dst,
945 struct pipe_fence_handle *src)
946 {
947 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
948 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
949 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
950
951 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
952 ws->fence_reference(&(*rdst)->gfx, NULL);
953 ws->fence_reference(&(*rdst)->sdma, NULL);
954 FREE(*rdst);
955 }
956 *rdst = rsrc;
957 }
958
959 static boolean r600_fence_finish(struct pipe_screen *screen,
960 struct pipe_fence_handle *fence,
961 uint64_t timeout)
962 {
963 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
964 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
965 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
966
967 if (rfence->sdma) {
968 if (!rws->fence_wait(rws, rfence->sdma, timeout))
969 return false;
970
971 /* Recompute the timeout after waiting. */
972 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
973 int64_t time = os_time_get_nano();
974 timeout = abs_timeout > time ? abs_timeout - time : 0;
975 }
976 }
977
978 if (!rfence->gfx)
979 return true;
980
981 return rws->fence_wait(rws, rfence->gfx, timeout);
982 }
983
984 static void r600_query_memory_info(struct pipe_screen *screen,
985 struct pipe_memory_info *info)
986 {
987 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
988 struct radeon_winsys *ws = rscreen->ws;
989 unsigned vram_usage, gtt_usage;
990
991 info->total_device_memory = rscreen->info.vram_size / 1024;
992 info->total_staging_memory = rscreen->info.gart_size / 1024;
993
994 /* The real TTM memory usage is somewhat random, because:
995 *
996 * 1) TTM delays freeing memory, because it can only free it after
997 * fences expire.
998 *
999 * 2) The memory usage can be really low if big VRAM evictions are
1000 * taking place, but the real usage is well above the size of VRAM.
1001 *
1002 * Instead, return statistics of this process.
1003 */
1004 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1005 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1006
1007 info->avail_device_memory =
1008 vram_usage <= info->total_device_memory ?
1009 info->total_device_memory - vram_usage : 0;
1010 info->avail_staging_memory =
1011 gtt_usage <= info->total_staging_memory ?
1012 info->total_staging_memory - gtt_usage : 0;
1013
1014 info->device_memory_evicted =
1015 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1016 /* Just return the number of evicted 64KB pages. */
1017 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1018 }
1019
1020 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1021 const struct pipe_resource *templ)
1022 {
1023 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1024
1025 if (templ->target == PIPE_BUFFER) {
1026 return r600_buffer_create(screen, templ,
1027 rscreen->info.gart_page_size);
1028 } else {
1029 return r600_texture_create(screen, templ);
1030 }
1031 }
1032
1033 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1034 struct radeon_winsys *ws)
1035 {
1036 char llvm_string[32] = {}, kernel_version[128] = {};
1037 struct utsname uname_data;
1038
1039 ws->query_info(ws, &rscreen->info);
1040
1041 if (uname(&uname_data) == 0)
1042 snprintf(kernel_version, sizeof(kernel_version),
1043 " / %s", uname_data.release);
1044
1045 #if HAVE_LLVM
1046 snprintf(llvm_string, sizeof(llvm_string),
1047 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1048 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1049 #endif
1050
1051 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1052 "%s (DRM %i.%i.%i%s%s)",
1053 r600_get_chip_name(rscreen), rscreen->info.drm_major,
1054 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1055 kernel_version, llvm_string);
1056
1057 rscreen->b.get_name = r600_get_name;
1058 rscreen->b.get_vendor = r600_get_vendor;
1059 rscreen->b.get_device_vendor = r600_get_device_vendor;
1060 rscreen->b.get_compute_param = r600_get_compute_param;
1061 rscreen->b.get_paramf = r600_get_paramf;
1062 rscreen->b.get_timestamp = r600_get_timestamp;
1063 rscreen->b.fence_finish = r600_fence_finish;
1064 rscreen->b.fence_reference = r600_fence_reference;
1065 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1066 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1067 rscreen->b.query_memory_info = r600_query_memory_info;
1068
1069 if (rscreen->info.has_uvd) {
1070 rscreen->b.get_video_param = rvid_get_video_param;
1071 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1072 } else {
1073 rscreen->b.get_video_param = r600_get_video_param;
1074 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1075 }
1076
1077 r600_init_screen_texture_functions(rscreen);
1078 r600_init_screen_query_functions(rscreen);
1079
1080 rscreen->ws = ws;
1081 rscreen->family = rscreen->info.family;
1082 rscreen->chip_class = rscreen->info.chip_class;
1083 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1084
1085 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1086 if (rscreen->force_aniso >= 0) {
1087 printf("radeon: Forcing anisotropy filter to %ix\n",
1088 /* round down to a power of two */
1089 1 << util_logbase2(rscreen->force_aniso));
1090 }
1091
1092 util_format_s3tc_init();
1093 pipe_mutex_init(rscreen->aux_context_lock);
1094 pipe_mutex_init(rscreen->gpu_load_mutex);
1095
1096 if (rscreen->debug_flags & DBG_INFO) {
1097 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1098 printf("family = %i (%s)\n", rscreen->info.family,
1099 r600_get_chip_name(rscreen));
1100 printf("chip_class = %i\n", rscreen->info.chip_class);
1101 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1102 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1103 printf("max_alloc_size = %i MB\n",
1104 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1105 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1106 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1107 printf("has_sdma = %i\n", rscreen->info.has_sdma);
1108 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1109 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1110 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1111 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1112 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1113 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1114 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1115
1116 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1117 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1118 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1119 printf("max_se = %i\n", rscreen->info.max_se);
1120 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1121
1122 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1123 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1124 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1125 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1126 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1127 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1128 }
1129 return true;
1130 }
1131
1132 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1133 {
1134 r600_perfcounters_destroy(rscreen);
1135 r600_gpu_load_kill_thread(rscreen);
1136
1137 pipe_mutex_destroy(rscreen->gpu_load_mutex);
1138 pipe_mutex_destroy(rscreen->aux_context_lock);
1139 rscreen->aux_context->destroy(rscreen->aux_context);
1140
1141 rscreen->ws->destroy(rscreen->ws);
1142 FREE(rscreen);
1143 }
1144
1145 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1146 unsigned processor)
1147 {
1148 switch (processor) {
1149 case PIPE_SHADER_VERTEX:
1150 return (rscreen->debug_flags & DBG_VS) != 0;
1151 case PIPE_SHADER_TESS_CTRL:
1152 return (rscreen->debug_flags & DBG_TCS) != 0;
1153 case PIPE_SHADER_TESS_EVAL:
1154 return (rscreen->debug_flags & DBG_TES) != 0;
1155 case PIPE_SHADER_GEOMETRY:
1156 return (rscreen->debug_flags & DBG_GS) != 0;
1157 case PIPE_SHADER_FRAGMENT:
1158 return (rscreen->debug_flags & DBG_PS) != 0;
1159 case PIPE_SHADER_COMPUTE:
1160 return (rscreen->debug_flags & DBG_CS) != 0;
1161 default:
1162 return false;
1163 }
1164 }
1165
1166 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1167 uint64_t offset, uint64_t size, unsigned value,
1168 enum r600_coherency coher)
1169 {
1170 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1171
1172 pipe_mutex_lock(rscreen->aux_context_lock);
1173 rctx->clear_buffer(&rctx->b, dst, offset, size, value, coher);
1174 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1175 pipe_mutex_unlock(rscreen->aux_context_lock);
1176 }