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radeonsi: apply the double EVENT_WRITE_EOP workaround to VI as well
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 struct r600_multi_fence {
47 struct pipe_reference reference;
48 struct pipe_fence_handle *gfx;
49 struct pipe_fence_handle *sdma;
50
51 /* If the context wasn't flushed at fence creation, this is non-NULL. */
52 struct {
53 struct r600_common_context *ctx;
54 unsigned ib_index;
55 } gfx_unflushed;
56 };
57
58 /*
59 * shader binary helpers.
60 */
61 void radeon_shader_binary_init(struct radeon_shader_binary *b)
62 {
63 memset(b, 0, sizeof(*b));
64 }
65
66 void radeon_shader_binary_clean(struct radeon_shader_binary *b)
67 {
68 if (!b)
69 return;
70 FREE(b->code);
71 FREE(b->config);
72 FREE(b->rodata);
73 FREE(b->global_symbol_offsets);
74 FREE(b->relocs);
75 FREE(b->disasm_string);
76 FREE(b->llvm_ir_string);
77 }
78
79 /*
80 * pipe_context
81 */
82
83 /**
84 * Write an EOP event.
85 *
86 * \param event EVENT_TYPE_*
87 * \param event_flags Optional cache flush flags (TC)
88 * \param data_sel 1 = fence, 3 = timestamp
89 * \param buf Buffer
90 * \param va GPU address
91 * \param old_value Previous fence value (for a bug workaround)
92 * \param new_value Fence value to write for this event.
93 */
94 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
95 unsigned event, unsigned event_flags,
96 unsigned data_sel,
97 struct r600_resource *buf, uint64_t va,
98 uint32_t old_fence, uint32_t new_fence)
99 {
100 struct radeon_winsys_cs *cs = ctx->gfx.cs;
101 unsigned op = EVENT_TYPE(event) |
102 EVENT_INDEX(5) |
103 event_flags;
104
105 if (ctx->chip_class == CIK ||
106 ctx->chip_class == VI) {
107 /* Two EOP events are required to make all engines go idle
108 * (and optional cache flushes executed) before the timestamp
109 * is written.
110 */
111 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
112 radeon_emit(cs, op);
113 radeon_emit(cs, va);
114 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
115 radeon_emit(cs, old_fence); /* immediate data */
116 radeon_emit(cs, 0); /* unused */
117 }
118
119 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
120 radeon_emit(cs, op);
121 radeon_emit(cs, va);
122 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
123 radeon_emit(cs, new_fence); /* immediate data */
124 radeon_emit(cs, 0); /* unused */
125
126 if (buf)
127 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
128 RADEON_PRIO_QUERY);
129 }
130
131 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
132 {
133 unsigned dwords = 6;
134
135 if (screen->chip_class == CIK ||
136 screen->chip_class == VI)
137 dwords *= 2;
138
139 if (!screen->info.has_virtual_memory)
140 dwords += 2;
141
142 return dwords;
143 }
144
145 void r600_gfx_wait_fence(struct r600_common_context *ctx,
146 uint64_t va, uint32_t ref, uint32_t mask)
147 {
148 struct radeon_winsys_cs *cs = ctx->gfx.cs;
149
150 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
151 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
152 radeon_emit(cs, va);
153 radeon_emit(cs, va >> 32);
154 radeon_emit(cs, ref); /* reference value */
155 radeon_emit(cs, mask); /* mask */
156 radeon_emit(cs, 4); /* poll interval */
157 }
158
159 void r600_draw_rectangle(struct blitter_context *blitter,
160 int x1, int y1, int x2, int y2, float depth,
161 enum blitter_attrib_type type,
162 const union pipe_color_union *attrib)
163 {
164 struct r600_common_context *rctx =
165 (struct r600_common_context*)util_blitter_get_pipe(blitter);
166 struct pipe_viewport_state viewport;
167 struct pipe_resource *buf = NULL;
168 unsigned offset = 0;
169 float *vb;
170
171 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
172 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
173 return;
174 }
175
176 /* Some operations (like color resolve on r6xx) don't work
177 * with the conventional primitive types.
178 * One that works is PT_RECTLIST, which we use here. */
179
180 /* setup viewport */
181 viewport.scale[0] = 1.0f;
182 viewport.scale[1] = 1.0f;
183 viewport.scale[2] = 1.0f;
184 viewport.translate[0] = 0.0f;
185 viewport.translate[1] = 0.0f;
186 viewport.translate[2] = 0.0f;
187 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
188
189 /* Upload vertices. The hw rectangle has only 3 vertices,
190 * I guess the 4th one is derived from the first 3.
191 * The vertex specification should match u_blitter's vertex element state. */
192 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, 256, &offset, &buf, (void**)&vb);
193 if (!buf)
194 return;
195
196 vb[0] = x1;
197 vb[1] = y1;
198 vb[2] = depth;
199 vb[3] = 1;
200
201 vb[8] = x1;
202 vb[9] = y2;
203 vb[10] = depth;
204 vb[11] = 1;
205
206 vb[16] = x2;
207 vb[17] = y1;
208 vb[18] = depth;
209 vb[19] = 1;
210
211 if (attrib) {
212 memcpy(vb+4, attrib->f, sizeof(float)*4);
213 memcpy(vb+12, attrib->f, sizeof(float)*4);
214 memcpy(vb+20, attrib->f, sizeof(float)*4);
215 }
216
217 /* draw */
218 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
219 R600_PRIM_RECTANGLE_LIST, 3, 2);
220 pipe_resource_reference(&buf, NULL);
221 }
222
223 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
224 struct r600_resource *dst, struct r600_resource *src)
225 {
226 uint64_t vram = 0, gtt = 0;
227
228 if (dst) {
229 vram += dst->vram_usage;
230 gtt += dst->gart_usage;
231 }
232 if (src) {
233 vram += src->vram_usage;
234 gtt += src->gart_usage;
235 }
236
237 /* Flush the GFX IB if DMA depends on it. */
238 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
239 ((dst &&
240 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
241 RADEON_USAGE_READWRITE)) ||
242 (src &&
243 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
244 RADEON_USAGE_WRITE))))
245 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
246
247 /* Flush if there's not enough space, or if the memory usage per IB
248 * is too large.
249 */
250 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
251 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
252 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
253 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
254 }
255
256 /* If GPUVM is not supported, the CS checker needs 2 entries
257 * in the buffer list per packet, which has to be done manually.
258 */
259 if (ctx->screen->info.has_virtual_memory) {
260 if (dst)
261 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
262 RADEON_USAGE_WRITE,
263 RADEON_PRIO_SDMA_BUFFER);
264 if (src)
265 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
266 RADEON_USAGE_READ,
267 RADEON_PRIO_SDMA_BUFFER);
268 }
269 }
270
271 /* This is required to prevent read-after-write hazards. */
272 void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
273 {
274 struct radeon_winsys_cs *cs = rctx->dma.cs;
275
276 /* done at the end of DMA calls, so increment this. */
277 rctx->num_dma_calls++;
278
279 /* IBs using too little memory are limited by the IB submission overhead.
280 * IBs using too much memory are limited by the kernel/TTM overhead.
281 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
282 *
283 * This heuristic makes sure that DMA requests are executed
284 * very soon after the call is made and lowers memory usage.
285 * It improves texture upload performance by keeping the DMA
286 * engine busy while uploads are being submitted.
287 */
288 if (cs->used_vram + cs->used_gart > 64 * 1024 * 1024) {
289 rctx->dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
290 return;
291 }
292
293 r600_need_dma_space(rctx, 1, NULL, NULL);
294
295 if (!radeon_emitted(cs, 0)) /* empty queue */
296 return;
297
298 /* NOP waits for idle on Evergreen and later. */
299 if (rctx->chip_class >= CIK)
300 radeon_emit(cs, 0x00000000); /* NOP */
301 else if (rctx->chip_class >= EVERGREEN)
302 radeon_emit(cs, 0xf0000000); /* NOP */
303 else {
304 /* TODO: R600-R700 should use the FENCE packet.
305 * CS checker support is required. */
306 }
307 }
308
309 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
310 {
311 }
312
313 void r600_preflush_suspend_features(struct r600_common_context *ctx)
314 {
315 /* suspend queries */
316 if (!LIST_IS_EMPTY(&ctx->active_queries))
317 r600_suspend_queries(ctx);
318
319 ctx->streamout.suspended = false;
320 if (ctx->streamout.begin_emitted) {
321 r600_emit_streamout_end(ctx);
322 ctx->streamout.suspended = true;
323 }
324 }
325
326 void r600_postflush_resume_features(struct r600_common_context *ctx)
327 {
328 if (ctx->streamout.suspended) {
329 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
330 r600_streamout_buffers_dirty(ctx);
331 }
332
333 /* resume queries */
334 if (!LIST_IS_EMPTY(&ctx->active_queries))
335 r600_resume_queries(ctx);
336 }
337
338 static void r600_flush_from_st(struct pipe_context *ctx,
339 struct pipe_fence_handle **fence,
340 unsigned flags)
341 {
342 struct pipe_screen *screen = ctx->screen;
343 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
344 struct radeon_winsys *ws = rctx->ws;
345 unsigned rflags = 0;
346 struct pipe_fence_handle *gfx_fence = NULL;
347 struct pipe_fence_handle *sdma_fence = NULL;
348 bool deferred_fence = false;
349
350 if (flags & PIPE_FLUSH_END_OF_FRAME)
351 rflags |= RADEON_FLUSH_END_OF_FRAME;
352 if (flags & PIPE_FLUSH_DEFERRED)
353 rflags |= RADEON_FLUSH_ASYNC;
354
355 if (rctx->dma.cs) {
356 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
357 }
358
359 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
360 if (fence)
361 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
362 if (!(rflags & RADEON_FLUSH_ASYNC))
363 ws->cs_sync_flush(rctx->gfx.cs);
364 } else {
365 /* Instead of flushing, create a deferred fence. Constraints:
366 * - The state tracker must allow a deferred flush.
367 * - The state tracker must request a fence.
368 * Thread safety in fence_finish must be ensured by the state tracker.
369 */
370 if (flags & PIPE_FLUSH_DEFERRED && fence) {
371 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
372 deferred_fence = true;
373 } else {
374 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
375 }
376 }
377
378 /* Both engines can signal out of order, so we need to keep both fences. */
379 if (fence) {
380 struct r600_multi_fence *multi_fence =
381 CALLOC_STRUCT(r600_multi_fence);
382 if (!multi_fence)
383 return;
384
385 multi_fence->reference.count = 1;
386 /* If both fences are NULL, fence_finish will always return true. */
387 multi_fence->gfx = gfx_fence;
388 multi_fence->sdma = sdma_fence;
389
390 if (deferred_fence) {
391 multi_fence->gfx_unflushed.ctx = rctx;
392 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
393 }
394
395 screen->fence_reference(screen, fence, NULL);
396 *fence = (struct pipe_fence_handle*)multi_fence;
397 }
398 }
399
400 static void r600_flush_dma_ring(void *ctx, unsigned flags,
401 struct pipe_fence_handle **fence)
402 {
403 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
404 struct radeon_winsys_cs *cs = rctx->dma.cs;
405 struct radeon_saved_cs saved;
406 bool check_vm =
407 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
408 rctx->check_vm_faults;
409
410 if (!radeon_emitted(cs, 0)) {
411 if (fence)
412 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
413 return;
414 }
415
416 if (check_vm)
417 radeon_save_cs(rctx->ws, cs, &saved);
418
419 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
420 if (fence)
421 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
422
423 if (check_vm) {
424 /* Use conservative timeout 800ms, after which we won't wait any
425 * longer and assume the GPU is hung.
426 */
427 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
428
429 rctx->check_vm_faults(rctx, &saved, RING_DMA);
430 radeon_clear_saved_cs(&saved);
431 }
432 }
433
434 /**
435 * Store a linearized copy of all chunks of \p cs together with the buffer
436 * list in \p saved.
437 */
438 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
439 struct radeon_saved_cs *saved)
440 {
441 void *buf;
442 unsigned i;
443
444 /* Save the IB chunks. */
445 saved->num_dw = cs->prev_dw + cs->current.cdw;
446 saved->ib = MALLOC(4 * saved->num_dw);
447 if (!saved->ib)
448 goto oom;
449
450 buf = saved->ib;
451 for (i = 0; i < cs->num_prev; ++i) {
452 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
453 buf += cs->prev[i].cdw;
454 }
455 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
456
457 /* Save the buffer list. */
458 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
459 saved->bo_list = CALLOC(saved->bo_count,
460 sizeof(saved->bo_list[0]));
461 if (!saved->bo_list) {
462 FREE(saved->ib);
463 goto oom;
464 }
465 ws->cs_get_buffer_list(cs, saved->bo_list);
466
467 return;
468
469 oom:
470 fprintf(stderr, "%s: out of memory\n", __func__);
471 memset(saved, 0, sizeof(*saved));
472 }
473
474 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
475 {
476 FREE(saved->ib);
477 FREE(saved->bo_list);
478
479 memset(saved, 0, sizeof(*saved));
480 }
481
482 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
483 {
484 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
485 unsigned latest = rctx->ws->query_value(rctx->ws,
486 RADEON_GPU_RESET_COUNTER);
487
488 if (rctx->gpu_reset_counter == latest)
489 return PIPE_NO_RESET;
490
491 rctx->gpu_reset_counter = latest;
492 return PIPE_UNKNOWN_CONTEXT_RESET;
493 }
494
495 static void r600_set_debug_callback(struct pipe_context *ctx,
496 const struct pipe_debug_callback *cb)
497 {
498 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
499
500 if (cb)
501 rctx->debug = *cb;
502 else
503 memset(&rctx->debug, 0, sizeof(rctx->debug));
504 }
505
506 static void r600_set_device_reset_callback(struct pipe_context *ctx,
507 const struct pipe_device_reset_callback *cb)
508 {
509 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
510
511 if (cb)
512 rctx->device_reset_callback = *cb;
513 else
514 memset(&rctx->device_reset_callback, 0,
515 sizeof(rctx->device_reset_callback));
516 }
517
518 bool r600_check_device_reset(struct r600_common_context *rctx)
519 {
520 enum pipe_reset_status status;
521
522 if (!rctx->device_reset_callback.reset)
523 return false;
524
525 if (!rctx->b.get_device_reset_status)
526 return false;
527
528 status = rctx->b.get_device_reset_status(&rctx->b);
529 if (status == PIPE_NO_RESET)
530 return false;
531
532 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
533 return true;
534 }
535
536 bool r600_common_context_init(struct r600_common_context *rctx,
537 struct r600_common_screen *rscreen,
538 unsigned context_flags)
539 {
540 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
541
542 rctx->screen = rscreen;
543 rctx->ws = rscreen->ws;
544 rctx->family = rscreen->family;
545 rctx->chip_class = rscreen->chip_class;
546
547 if (rscreen->chip_class >= CIK)
548 rctx->max_db = MAX2(8, rscreen->info.num_render_backends);
549 else if (rscreen->chip_class >= EVERGREEN)
550 rctx->max_db = 8;
551 else
552 rctx->max_db = 4;
553
554 rctx->b.invalidate_resource = r600_invalidate_resource;
555 rctx->b.transfer_map = u_transfer_map_vtbl;
556 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
557 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
558 rctx->b.texture_subdata = u_default_texture_subdata;
559 rctx->b.memory_barrier = r600_memory_barrier;
560 rctx->b.flush = r600_flush_from_st;
561 rctx->b.set_debug_callback = r600_set_debug_callback;
562
563 /* evergreen_compute.c has a special codepath for global buffers.
564 * Everything else can use the direct path.
565 */
566 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
567 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
568 rctx->b.buffer_subdata = u_default_buffer_subdata;
569 else
570 rctx->b.buffer_subdata = r600_buffer_subdata;
571
572 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
573 rctx->b.get_device_reset_status = r600_get_reset_status;
574 rctx->gpu_reset_counter =
575 rctx->ws->query_value(rctx->ws,
576 RADEON_GPU_RESET_COUNTER);
577 }
578
579 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
580
581 r600_init_context_texture_functions(rctx);
582 r600_init_viewport_functions(rctx);
583 r600_streamout_init(rctx);
584 r600_query_init(rctx);
585 cayman_init_msaa(&rctx->b);
586
587 rctx->allocator_zeroed_memory =
588 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
589 0, PIPE_USAGE_DEFAULT, true);
590 if (!rctx->allocator_zeroed_memory)
591 return false;
592
593 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024,
594 PIPE_BIND_INDEX_BUFFER |
595 PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
596 if (!rctx->uploader)
597 return false;
598
599 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
600 if (!rctx->ctx)
601 return false;
602
603 if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
604 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
605 r600_flush_dma_ring,
606 rctx);
607 rctx->dma.flush = r600_flush_dma_ring;
608 }
609
610 return true;
611 }
612
613 void r600_common_context_cleanup(struct r600_common_context *rctx)
614 {
615 unsigned i,j;
616
617 /* Release DCC stats. */
618 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
619 assert(!rctx->dcc_stats[i].query_active);
620
621 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
622 if (rctx->dcc_stats[i].ps_stats[j])
623 rctx->b.destroy_query(&rctx->b,
624 rctx->dcc_stats[i].ps_stats[j]);
625
626 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
627 }
628
629 if (rctx->query_result_shader)
630 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
631
632 if (rctx->gfx.cs)
633 rctx->ws->cs_destroy(rctx->gfx.cs);
634 if (rctx->dma.cs)
635 rctx->ws->cs_destroy(rctx->dma.cs);
636 if (rctx->ctx)
637 rctx->ws->ctx_destroy(rctx->ctx);
638
639 if (rctx->uploader) {
640 u_upload_destroy(rctx->uploader);
641 }
642
643 slab_destroy_child(&rctx->pool_transfers);
644
645 if (rctx->allocator_zeroed_memory) {
646 u_suballocator_destroy(rctx->allocator_zeroed_memory);
647 }
648 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
649 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
650 }
651
652 /*
653 * pipe_screen
654 */
655
656 static const struct debug_named_value common_debug_options[] = {
657 /* logging */
658 { "tex", DBG_TEX, "Print texture info" },
659 { "compute", DBG_COMPUTE, "Print compute info" },
660 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
661 { "info", DBG_INFO, "Print driver information" },
662
663 /* shaders */
664 { "fs", DBG_FS, "Print fetch shaders" },
665 { "vs", DBG_VS, "Print vertex shaders" },
666 { "gs", DBG_GS, "Print geometry shaders" },
667 { "ps", DBG_PS, "Print pixel shaders" },
668 { "cs", DBG_CS, "Print compute shaders" },
669 { "tcs", DBG_TCS, "Print tessellation control shaders" },
670 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
671 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
672 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
673 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
674 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
675 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
676 { "nooptvariant", DBG_NO_OPT_VARIANT, "Disable compiling optimized shader variants." },
677
678 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
679
680 /* features */
681 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
682 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
683 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
684 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
685 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
686 { "notiling", DBG_NO_TILING, "Disable tiling" },
687 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
688 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
689 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
690 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
691 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
692 { "nodcc", DBG_NO_DCC, "Disable DCC." },
693 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
694 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
695 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
696 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
697 { "noce", DBG_NO_CE, "Disable the constant engine"},
698 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
699 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
700
701 DEBUG_NAMED_VALUE_END /* must be last */
702 };
703
704 static const char* r600_get_vendor(struct pipe_screen* pscreen)
705 {
706 return "X.Org";
707 }
708
709 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
710 {
711 return "AMD";
712 }
713
714 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
715 {
716 switch (rscreen->info.family) {
717 case CHIP_R600: return "AMD R600";
718 case CHIP_RV610: return "AMD RV610";
719 case CHIP_RV630: return "AMD RV630";
720 case CHIP_RV670: return "AMD RV670";
721 case CHIP_RV620: return "AMD RV620";
722 case CHIP_RV635: return "AMD RV635";
723 case CHIP_RS780: return "AMD RS780";
724 case CHIP_RS880: return "AMD RS880";
725 case CHIP_RV770: return "AMD RV770";
726 case CHIP_RV730: return "AMD RV730";
727 case CHIP_RV710: return "AMD RV710";
728 case CHIP_RV740: return "AMD RV740";
729 case CHIP_CEDAR: return "AMD CEDAR";
730 case CHIP_REDWOOD: return "AMD REDWOOD";
731 case CHIP_JUNIPER: return "AMD JUNIPER";
732 case CHIP_CYPRESS: return "AMD CYPRESS";
733 case CHIP_HEMLOCK: return "AMD HEMLOCK";
734 case CHIP_PALM: return "AMD PALM";
735 case CHIP_SUMO: return "AMD SUMO";
736 case CHIP_SUMO2: return "AMD SUMO2";
737 case CHIP_BARTS: return "AMD BARTS";
738 case CHIP_TURKS: return "AMD TURKS";
739 case CHIP_CAICOS: return "AMD CAICOS";
740 case CHIP_CAYMAN: return "AMD CAYMAN";
741 case CHIP_ARUBA: return "AMD ARUBA";
742 case CHIP_TAHITI: return "AMD TAHITI";
743 case CHIP_PITCAIRN: return "AMD PITCAIRN";
744 case CHIP_VERDE: return "AMD CAPE VERDE";
745 case CHIP_OLAND: return "AMD OLAND";
746 case CHIP_HAINAN: return "AMD HAINAN";
747 case CHIP_BONAIRE: return "AMD BONAIRE";
748 case CHIP_KAVERI: return "AMD KAVERI";
749 case CHIP_KABINI: return "AMD KABINI";
750 case CHIP_HAWAII: return "AMD HAWAII";
751 case CHIP_MULLINS: return "AMD MULLINS";
752 case CHIP_TONGA: return "AMD TONGA";
753 case CHIP_ICELAND: return "AMD ICELAND";
754 case CHIP_CARRIZO: return "AMD CARRIZO";
755 case CHIP_FIJI: return "AMD FIJI";
756 case CHIP_POLARIS10: return "AMD POLARIS10";
757 case CHIP_POLARIS11: return "AMD POLARIS11";
758 case CHIP_STONEY: return "AMD STONEY";
759 default: return "AMD unknown";
760 }
761 }
762
763 static const char* r600_get_name(struct pipe_screen* pscreen)
764 {
765 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
766
767 return rscreen->renderer_string;
768 }
769
770 static float r600_get_paramf(struct pipe_screen* pscreen,
771 enum pipe_capf param)
772 {
773 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
774
775 switch (param) {
776 case PIPE_CAPF_MAX_LINE_WIDTH:
777 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
778 case PIPE_CAPF_MAX_POINT_WIDTH:
779 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
780 if (rscreen->family >= CHIP_CEDAR)
781 return 16384.0f;
782 else
783 return 8192.0f;
784 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
785 return 16.0f;
786 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
787 return 16.0f;
788 case PIPE_CAPF_GUARD_BAND_LEFT:
789 case PIPE_CAPF_GUARD_BAND_TOP:
790 case PIPE_CAPF_GUARD_BAND_RIGHT:
791 case PIPE_CAPF_GUARD_BAND_BOTTOM:
792 return 0.0f;
793 }
794 return 0.0f;
795 }
796
797 static int r600_get_video_param(struct pipe_screen *screen,
798 enum pipe_video_profile profile,
799 enum pipe_video_entrypoint entrypoint,
800 enum pipe_video_cap param)
801 {
802 switch (param) {
803 case PIPE_VIDEO_CAP_SUPPORTED:
804 return vl_profile_supported(screen, profile, entrypoint);
805 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
806 return 1;
807 case PIPE_VIDEO_CAP_MAX_WIDTH:
808 case PIPE_VIDEO_CAP_MAX_HEIGHT:
809 return vl_video_buffer_max_size(screen);
810 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
811 return PIPE_FORMAT_NV12;
812 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
813 return false;
814 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
815 return false;
816 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
817 return true;
818 case PIPE_VIDEO_CAP_MAX_LEVEL:
819 return vl_level_supported(screen, profile);
820 default:
821 return 0;
822 }
823 }
824
825 const char *r600_get_llvm_processor_name(enum radeon_family family)
826 {
827 switch (family) {
828 case CHIP_R600:
829 case CHIP_RV630:
830 case CHIP_RV635:
831 case CHIP_RV670:
832 return "r600";
833 case CHIP_RV610:
834 case CHIP_RV620:
835 case CHIP_RS780:
836 case CHIP_RS880:
837 return "rs880";
838 case CHIP_RV710:
839 return "rv710";
840 case CHIP_RV730:
841 return "rv730";
842 case CHIP_RV740:
843 case CHIP_RV770:
844 return "rv770";
845 case CHIP_PALM:
846 case CHIP_CEDAR:
847 return "cedar";
848 case CHIP_SUMO:
849 case CHIP_SUMO2:
850 return "sumo";
851 case CHIP_REDWOOD:
852 return "redwood";
853 case CHIP_JUNIPER:
854 return "juniper";
855 case CHIP_HEMLOCK:
856 case CHIP_CYPRESS:
857 return "cypress";
858 case CHIP_BARTS:
859 return "barts";
860 case CHIP_TURKS:
861 return "turks";
862 case CHIP_CAICOS:
863 return "caicos";
864 case CHIP_CAYMAN:
865 case CHIP_ARUBA:
866 return "cayman";
867
868 case CHIP_TAHITI: return "tahiti";
869 case CHIP_PITCAIRN: return "pitcairn";
870 case CHIP_VERDE: return "verde";
871 case CHIP_OLAND: return "oland";
872 case CHIP_HAINAN: return "hainan";
873 case CHIP_BONAIRE: return "bonaire";
874 case CHIP_KABINI: return "kabini";
875 case CHIP_KAVERI: return "kaveri";
876 case CHIP_HAWAII: return "hawaii";
877 case CHIP_MULLINS:
878 return "mullins";
879 case CHIP_TONGA: return "tonga";
880 case CHIP_ICELAND: return "iceland";
881 case CHIP_CARRIZO: return "carrizo";
882 #if HAVE_LLVM <= 0x0307
883 case CHIP_FIJI: return "tonga";
884 case CHIP_STONEY: return "carrizo";
885 #else
886 case CHIP_FIJI: return "fiji";
887 case CHIP_STONEY: return "stoney";
888 #endif
889 #if HAVE_LLVM <= 0x0308
890 case CHIP_POLARIS10: return "tonga";
891 case CHIP_POLARIS11: return "tonga";
892 #else
893 case CHIP_POLARIS10: return "polaris10";
894 case CHIP_POLARIS11: return "polaris11";
895 #endif
896 default: return "";
897 }
898 }
899
900 static int r600_get_compute_param(struct pipe_screen *screen,
901 enum pipe_shader_ir ir_type,
902 enum pipe_compute_cap param,
903 void *ret)
904 {
905 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
906
907 //TODO: select these params by asic
908 switch (param) {
909 case PIPE_COMPUTE_CAP_IR_TARGET: {
910 const char *gpu;
911 const char *triple;
912 if (rscreen->family <= CHIP_ARUBA) {
913 triple = "r600--";
914 } else {
915 if (HAVE_LLVM < 0x0400) {
916 triple = "amdgcn--";
917 } else {
918 triple = "amdgcn-mesa-mesa3d";
919 }
920 }
921 switch(rscreen->family) {
922 /* Clang < 3.6 is missing Hainan in its list of
923 * GPUs, so we need to use the name of a similar GPU.
924 */
925 default:
926 gpu = r600_get_llvm_processor_name(rscreen->family);
927 break;
928 }
929 if (ret) {
930 sprintf(ret, "%s-%s", gpu, triple);
931 }
932 /* +2 for dash and terminating NIL byte */
933 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
934 }
935 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
936 if (ret) {
937 uint64_t *grid_dimension = ret;
938 grid_dimension[0] = 3;
939 }
940 return 1 * sizeof(uint64_t);
941
942 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
943 if (ret) {
944 uint64_t *grid_size = ret;
945 grid_size[0] = 65535;
946 grid_size[1] = 65535;
947 grid_size[2] = 65535;
948 }
949 return 3 * sizeof(uint64_t) ;
950
951 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
952 if (ret) {
953 uint64_t *block_size = ret;
954 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
955 ir_type == PIPE_SHADER_IR_TGSI) {
956 block_size[0] = 2048;
957 block_size[1] = 2048;
958 block_size[2] = 2048;
959 } else {
960 block_size[0] = 256;
961 block_size[1] = 256;
962 block_size[2] = 256;
963 }
964 }
965 return 3 * sizeof(uint64_t);
966
967 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
968 if (ret) {
969 uint64_t *max_threads_per_block = ret;
970 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
971 ir_type == PIPE_SHADER_IR_TGSI)
972 *max_threads_per_block = 2048;
973 else
974 *max_threads_per_block = 256;
975 }
976 return sizeof(uint64_t);
977 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
978 if (ret) {
979 uint32_t *address_bits = ret;
980 address_bits[0] = 32;
981 if (rscreen->chip_class >= SI)
982 address_bits[0] = 64;
983 }
984 return 1 * sizeof(uint32_t);
985
986 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
987 if (ret) {
988 uint64_t *max_global_size = ret;
989 uint64_t max_mem_alloc_size;
990
991 r600_get_compute_param(screen, ir_type,
992 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
993 &max_mem_alloc_size);
994
995 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
996 * 1/4 of the MAX_GLOBAL_SIZE. Since the
997 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
998 * make sure we never report more than
999 * 4 * MAX_MEM_ALLOC_SIZE.
1000 */
1001 *max_global_size = MIN2(4 * max_mem_alloc_size,
1002 MAX2(rscreen->info.gart_size,
1003 rscreen->info.vram_size));
1004 }
1005 return sizeof(uint64_t);
1006
1007 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1008 if (ret) {
1009 uint64_t *max_local_size = ret;
1010 /* Value reported by the closed source driver. */
1011 *max_local_size = 32768;
1012 }
1013 return sizeof(uint64_t);
1014
1015 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1016 if (ret) {
1017 uint64_t *max_input_size = ret;
1018 /* Value reported by the closed source driver. */
1019 *max_input_size = 1024;
1020 }
1021 return sizeof(uint64_t);
1022
1023 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1024 if (ret) {
1025 uint64_t *max_mem_alloc_size = ret;
1026
1027 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1028 }
1029 return sizeof(uint64_t);
1030
1031 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1032 if (ret) {
1033 uint32_t *max_clock_frequency = ret;
1034 *max_clock_frequency = rscreen->info.max_shader_clock;
1035 }
1036 return sizeof(uint32_t);
1037
1038 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1039 if (ret) {
1040 uint32_t *max_compute_units = ret;
1041 *max_compute_units = rscreen->info.num_good_compute_units;
1042 }
1043 return sizeof(uint32_t);
1044
1045 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1046 if (ret) {
1047 uint32_t *images_supported = ret;
1048 *images_supported = 0;
1049 }
1050 return sizeof(uint32_t);
1051 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1052 break; /* unused */
1053 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1054 if (ret) {
1055 uint32_t *subgroup_size = ret;
1056 *subgroup_size = r600_wavefront_size(rscreen->family);
1057 }
1058 return sizeof(uint32_t);
1059 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1060 if (ret) {
1061 uint64_t *max_variable_threads_per_block = ret;
1062 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
1063 ir_type == PIPE_SHADER_IR_TGSI)
1064 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
1065 else
1066 *max_variable_threads_per_block = 0;
1067 }
1068 return sizeof(uint64_t);
1069 }
1070
1071 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1072 return 0;
1073 }
1074
1075 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1076 {
1077 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1078
1079 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1080 rscreen->info.clock_crystal_freq;
1081 }
1082
1083 static void r600_fence_reference(struct pipe_screen *screen,
1084 struct pipe_fence_handle **dst,
1085 struct pipe_fence_handle *src)
1086 {
1087 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1088 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1089 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1090
1091 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1092 ws->fence_reference(&(*rdst)->gfx, NULL);
1093 ws->fence_reference(&(*rdst)->sdma, NULL);
1094 FREE(*rdst);
1095 }
1096 *rdst = rsrc;
1097 }
1098
1099 static boolean r600_fence_finish(struct pipe_screen *screen,
1100 struct pipe_context *ctx,
1101 struct pipe_fence_handle *fence,
1102 uint64_t timeout)
1103 {
1104 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1105 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1106 struct r600_common_context *rctx =
1107 ctx ? (struct r600_common_context*)ctx : NULL;
1108 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1109
1110 if (rfence->sdma) {
1111 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1112 return false;
1113
1114 /* Recompute the timeout after waiting. */
1115 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1116 int64_t time = os_time_get_nano();
1117 timeout = abs_timeout > time ? abs_timeout - time : 0;
1118 }
1119 }
1120
1121 if (!rfence->gfx)
1122 return true;
1123
1124 /* Flush the gfx IB if it hasn't been flushed yet. */
1125 if (rctx &&
1126 rfence->gfx_unflushed.ctx == rctx &&
1127 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1128 rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
1129 rfence->gfx_unflushed.ctx = NULL;
1130
1131 if (!timeout)
1132 return false;
1133
1134 /* Recompute the timeout after all that. */
1135 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1136 int64_t time = os_time_get_nano();
1137 timeout = abs_timeout > time ? abs_timeout - time : 0;
1138 }
1139 }
1140
1141 return rws->fence_wait(rws, rfence->gfx, timeout);
1142 }
1143
1144 static void r600_query_memory_info(struct pipe_screen *screen,
1145 struct pipe_memory_info *info)
1146 {
1147 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1148 struct radeon_winsys *ws = rscreen->ws;
1149 unsigned vram_usage, gtt_usage;
1150
1151 info->total_device_memory = rscreen->info.vram_size / 1024;
1152 info->total_staging_memory = rscreen->info.gart_size / 1024;
1153
1154 /* The real TTM memory usage is somewhat random, because:
1155 *
1156 * 1) TTM delays freeing memory, because it can only free it after
1157 * fences expire.
1158 *
1159 * 2) The memory usage can be really low if big VRAM evictions are
1160 * taking place, but the real usage is well above the size of VRAM.
1161 *
1162 * Instead, return statistics of this process.
1163 */
1164 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1165 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1166
1167 info->avail_device_memory =
1168 vram_usage <= info->total_device_memory ?
1169 info->total_device_memory - vram_usage : 0;
1170 info->avail_staging_memory =
1171 gtt_usage <= info->total_staging_memory ?
1172 info->total_staging_memory - gtt_usage : 0;
1173
1174 info->device_memory_evicted =
1175 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1176
1177 if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
1178 info->nr_device_memory_evictions =
1179 ws->query_value(ws, RADEON_NUM_EVICTIONS);
1180 else
1181 /* Just return the number of evicted 64KB pages. */
1182 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1183 }
1184
1185 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1186 const struct pipe_resource *templ)
1187 {
1188 if (templ->target == PIPE_BUFFER) {
1189 return r600_buffer_create(screen, templ, 256);
1190 } else {
1191 return r600_texture_create(screen, templ);
1192 }
1193 }
1194
1195 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1196 struct radeon_winsys *ws)
1197 {
1198 char llvm_string[32] = {}, kernel_version[128] = {};
1199 struct utsname uname_data;
1200
1201 ws->query_info(ws, &rscreen->info);
1202
1203 if (uname(&uname_data) == 0)
1204 snprintf(kernel_version, sizeof(kernel_version),
1205 " / %s", uname_data.release);
1206
1207 #if HAVE_LLVM
1208 snprintf(llvm_string, sizeof(llvm_string),
1209 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1210 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1211 #endif
1212
1213 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1214 "%s (DRM %i.%i.%i%s%s)",
1215 r600_get_chip_name(rscreen), rscreen->info.drm_major,
1216 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1217 kernel_version, llvm_string);
1218
1219 rscreen->b.get_name = r600_get_name;
1220 rscreen->b.get_vendor = r600_get_vendor;
1221 rscreen->b.get_device_vendor = r600_get_device_vendor;
1222 rscreen->b.get_compute_param = r600_get_compute_param;
1223 rscreen->b.get_paramf = r600_get_paramf;
1224 rscreen->b.get_timestamp = r600_get_timestamp;
1225 rscreen->b.fence_finish = r600_fence_finish;
1226 rscreen->b.fence_reference = r600_fence_reference;
1227 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1228 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1229 rscreen->b.query_memory_info = r600_query_memory_info;
1230
1231 if (rscreen->info.has_uvd) {
1232 rscreen->b.get_video_param = rvid_get_video_param;
1233 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1234 } else {
1235 rscreen->b.get_video_param = r600_get_video_param;
1236 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1237 }
1238
1239 r600_init_screen_texture_functions(rscreen);
1240 r600_init_screen_query_functions(rscreen);
1241
1242 rscreen->ws = ws;
1243 rscreen->family = rscreen->info.family;
1244 rscreen->chip_class = rscreen->info.chip_class;
1245 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1246
1247 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1248
1249 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1250 if (rscreen->force_aniso >= 0) {
1251 printf("radeon: Forcing anisotropy filter to %ix\n",
1252 /* round down to a power of two */
1253 1 << util_logbase2(rscreen->force_aniso));
1254 }
1255
1256 util_format_s3tc_init();
1257 pipe_mutex_init(rscreen->aux_context_lock);
1258 pipe_mutex_init(rscreen->gpu_load_mutex);
1259
1260 if (rscreen->debug_flags & DBG_INFO) {
1261 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1262 printf("family = %i (%s)\n", rscreen->info.family,
1263 r600_get_chip_name(rscreen));
1264 printf("chip_class = %i\n", rscreen->info.chip_class);
1265 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1266 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1267 printf("max_alloc_size = %i MB\n",
1268 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1269 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1270 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1271 printf("has_sdma = %i\n", rscreen->info.has_sdma);
1272 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1273 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1274 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1275 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1276 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1277 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1278 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1279 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1280 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1281 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1282
1283 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1284 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1285 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1286 printf("max_se = %i\n", rscreen->info.max_se);
1287 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1288
1289 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1290 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1291 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1292 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1293 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1294 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1295 }
1296 return true;
1297 }
1298
1299 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1300 {
1301 r600_perfcounters_destroy(rscreen);
1302 r600_gpu_load_kill_thread(rscreen);
1303
1304 pipe_mutex_destroy(rscreen->gpu_load_mutex);
1305 pipe_mutex_destroy(rscreen->aux_context_lock);
1306 rscreen->aux_context->destroy(rscreen->aux_context);
1307
1308 slab_destroy_parent(&rscreen->pool_transfers);
1309
1310 rscreen->ws->destroy(rscreen->ws);
1311 FREE(rscreen);
1312 }
1313
1314 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1315 unsigned processor)
1316 {
1317 switch (processor) {
1318 case PIPE_SHADER_VERTEX:
1319 return (rscreen->debug_flags & DBG_VS) != 0;
1320 case PIPE_SHADER_TESS_CTRL:
1321 return (rscreen->debug_flags & DBG_TCS) != 0;
1322 case PIPE_SHADER_TESS_EVAL:
1323 return (rscreen->debug_flags & DBG_TES) != 0;
1324 case PIPE_SHADER_GEOMETRY:
1325 return (rscreen->debug_flags & DBG_GS) != 0;
1326 case PIPE_SHADER_FRAGMENT:
1327 return (rscreen->debug_flags & DBG_PS) != 0;
1328 case PIPE_SHADER_COMPUTE:
1329 return (rscreen->debug_flags & DBG_CS) != 0;
1330 default:
1331 return false;
1332 }
1333 }
1334
1335 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1336 {
1337 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1338 r600_can_dump_shader(rscreen, processor);
1339 }
1340
1341 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1342 uint64_t offset, uint64_t size, unsigned value,
1343 enum r600_coherency coher)
1344 {
1345 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1346
1347 pipe_mutex_lock(rscreen->aux_context_lock);
1348 rctx->clear_buffer(&rctx->b, dst, offset, size, value, coher);
1349 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1350 pipe_mutex_unlock(rscreen->aux_context_lock);
1351 }