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radeon: rename has_uvd info to has_hw_decode
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 #if HAVE_LLVM
47 #include <llvm-c/TargetMachine.h>
48 #endif
49
50 #ifndef MESA_LLVM_VERSION_PATCH
51 #define MESA_LLVM_VERSION_PATCH 0
52 #endif
53
54 struct r600_multi_fence {
55 struct pipe_reference reference;
56 struct pipe_fence_handle *gfx;
57 struct pipe_fence_handle *sdma;
58
59 /* If the context wasn't flushed at fence creation, this is non-NULL. */
60 struct {
61 struct r600_common_context *ctx;
62 unsigned ib_index;
63 } gfx_unflushed;
64 };
65
66 /*
67 * shader binary helpers.
68 */
69 void radeon_shader_binary_init(struct ac_shader_binary *b)
70 {
71 memset(b, 0, sizeof(*b));
72 }
73
74 void radeon_shader_binary_clean(struct ac_shader_binary *b)
75 {
76 if (!b)
77 return;
78 FREE(b->code);
79 FREE(b->config);
80 FREE(b->rodata);
81 FREE(b->global_symbol_offsets);
82 FREE(b->relocs);
83 FREE(b->disasm_string);
84 FREE(b->llvm_ir_string);
85 }
86
87 /*
88 * pipe_context
89 */
90
91 /**
92 * Write an EOP event.
93 *
94 * \param event EVENT_TYPE_*
95 * \param event_flags Optional cache flush flags (TC)
96 * \param data_sel 1 = fence, 3 = timestamp
97 * \param buf Buffer
98 * \param va GPU address
99 * \param old_value Previous fence value (for a bug workaround)
100 * \param new_value Fence value to write for this event.
101 */
102 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
103 unsigned event, unsigned event_flags,
104 unsigned data_sel,
105 struct r600_resource *buf, uint64_t va,
106 uint32_t old_fence, uint32_t new_fence)
107 {
108 struct radeon_winsys_cs *cs = ctx->gfx.cs;
109 unsigned op = EVENT_TYPE(event) |
110 EVENT_INDEX(5) |
111 event_flags;
112
113 if (ctx->chip_class >= GFX9) {
114 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 6, 0));
115 radeon_emit(cs, op);
116 radeon_emit(cs, EOP_DATA_SEL(data_sel));
117 radeon_emit(cs, va); /* address lo */
118 radeon_emit(cs, va >> 32); /* address hi */
119 radeon_emit(cs, new_fence); /* immediate data lo */
120 radeon_emit(cs, 0); /* immediate data hi */
121 radeon_emit(cs, 0); /* unused */
122 } else {
123 if (ctx->chip_class == CIK ||
124 ctx->chip_class == VI) {
125 /* Two EOP events are required to make all engines go idle
126 * (and optional cache flushes executed) before the timestamp
127 * is written.
128 */
129 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
130 radeon_emit(cs, op);
131 radeon_emit(cs, va);
132 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
133 radeon_emit(cs, old_fence); /* immediate data */
134 radeon_emit(cs, 0); /* unused */
135 }
136
137 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
138 radeon_emit(cs, op);
139 radeon_emit(cs, va);
140 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
141 radeon_emit(cs, new_fence); /* immediate data */
142 radeon_emit(cs, 0); /* unused */
143 }
144
145 if (buf)
146 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
147 RADEON_PRIO_QUERY);
148 }
149
150 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
151 {
152 unsigned dwords = 6;
153
154 if (screen->chip_class == CIK ||
155 screen->chip_class == VI)
156 dwords *= 2;
157
158 if (!screen->info.has_virtual_memory)
159 dwords += 2;
160
161 return dwords;
162 }
163
164 void r600_gfx_wait_fence(struct r600_common_context *ctx,
165 uint64_t va, uint32_t ref, uint32_t mask)
166 {
167 struct radeon_winsys_cs *cs = ctx->gfx.cs;
168
169 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
170 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
171 radeon_emit(cs, va);
172 radeon_emit(cs, va >> 32);
173 radeon_emit(cs, ref); /* reference value */
174 radeon_emit(cs, mask); /* mask */
175 radeon_emit(cs, 4); /* poll interval */
176 }
177
178 void r600_draw_rectangle(struct blitter_context *blitter,
179 int x1, int y1, int x2, int y2, float depth,
180 enum blitter_attrib_type type,
181 const union pipe_color_union *attrib)
182 {
183 struct r600_common_context *rctx =
184 (struct r600_common_context*)util_blitter_get_pipe(blitter);
185 struct pipe_viewport_state viewport;
186 struct pipe_resource *buf = NULL;
187 unsigned offset = 0;
188 float *vb;
189
190 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
191 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
192 return;
193 }
194
195 /* Some operations (like color resolve on r6xx) don't work
196 * with the conventional primitive types.
197 * One that works is PT_RECTLIST, which we use here. */
198
199 /* setup viewport */
200 viewport.scale[0] = 1.0f;
201 viewport.scale[1] = 1.0f;
202 viewport.scale[2] = 1.0f;
203 viewport.translate[0] = 0.0f;
204 viewport.translate[1] = 0.0f;
205 viewport.translate[2] = 0.0f;
206 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
207
208 /* Upload vertices. The hw rectangle has only 3 vertices,
209 * I guess the 4th one is derived from the first 3.
210 * The vertex specification should match u_blitter's vertex element state. */
211 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
212 rctx->screen->info.tcc_cache_line_size,
213 &offset, &buf, (void**)&vb);
214 if (!buf)
215 return;
216
217 vb[0] = x1;
218 vb[1] = y1;
219 vb[2] = depth;
220 vb[3] = 1;
221
222 vb[8] = x1;
223 vb[9] = y2;
224 vb[10] = depth;
225 vb[11] = 1;
226
227 vb[16] = x2;
228 vb[17] = y1;
229 vb[18] = depth;
230 vb[19] = 1;
231
232 if (attrib) {
233 memcpy(vb+4, attrib->f, sizeof(float)*4);
234 memcpy(vb+12, attrib->f, sizeof(float)*4);
235 memcpy(vb+20, attrib->f, sizeof(float)*4);
236 }
237
238 /* draw */
239 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
240 R600_PRIM_RECTANGLE_LIST, 3, 2);
241 pipe_resource_reference(&buf, NULL);
242 }
243
244 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
245 {
246 struct radeon_winsys_cs *cs = rctx->dma.cs;
247
248 /* NOP waits for idle on Evergreen and later. */
249 if (rctx->chip_class >= CIK)
250 radeon_emit(cs, 0x00000000); /* NOP */
251 else if (rctx->chip_class >= EVERGREEN)
252 radeon_emit(cs, 0xf0000000); /* NOP */
253 else {
254 /* TODO: R600-R700 should use the FENCE packet.
255 * CS checker support is required. */
256 }
257 }
258
259 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
260 struct r600_resource *dst, struct r600_resource *src)
261 {
262 uint64_t vram = ctx->dma.cs->used_vram;
263 uint64_t gtt = ctx->dma.cs->used_gart;
264
265 if (dst) {
266 vram += dst->vram_usage;
267 gtt += dst->gart_usage;
268 }
269 if (src) {
270 vram += src->vram_usage;
271 gtt += src->gart_usage;
272 }
273
274 /* Flush the GFX IB if DMA depends on it. */
275 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
276 ((dst &&
277 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
278 RADEON_USAGE_READWRITE)) ||
279 (src &&
280 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
281 RADEON_USAGE_WRITE))))
282 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
283
284 /* Flush if there's not enough space, or if the memory usage per IB
285 * is too large.
286 *
287 * IBs using too little memory are limited by the IB submission overhead.
288 * IBs using too much memory are limited by the kernel/TTM overhead.
289 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
290 *
291 * This heuristic makes sure that DMA requests are executed
292 * very soon after the call is made and lowers memory usage.
293 * It improves texture upload performance by keeping the DMA
294 * engine busy while uploads are being submitted.
295 */
296 num_dw++; /* for emit_wait_idle below */
297 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
298 ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 ||
299 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
300 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
301 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
302 }
303
304 /* Wait for idle if either buffer has been used in the IB before to
305 * prevent read-after-write hazards.
306 */
307 if ((dst &&
308 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, dst->buf,
309 RADEON_USAGE_READWRITE)) ||
310 (src &&
311 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, src->buf,
312 RADEON_USAGE_WRITE)))
313 r600_dma_emit_wait_idle(ctx);
314
315 /* If GPUVM is not supported, the CS checker needs 2 entries
316 * in the buffer list per packet, which has to be done manually.
317 */
318 if (ctx->screen->info.has_virtual_memory) {
319 if (dst)
320 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
321 RADEON_USAGE_WRITE,
322 RADEON_PRIO_SDMA_BUFFER);
323 if (src)
324 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
325 RADEON_USAGE_READ,
326 RADEON_PRIO_SDMA_BUFFER);
327 }
328
329 /* this function is called before all DMA calls, so increment this. */
330 ctx->num_dma_calls++;
331 }
332
333 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
334 {
335 }
336
337 void r600_preflush_suspend_features(struct r600_common_context *ctx)
338 {
339 /* suspend queries */
340 if (!LIST_IS_EMPTY(&ctx->active_queries))
341 r600_suspend_queries(ctx);
342
343 ctx->streamout.suspended = false;
344 if (ctx->streamout.begin_emitted) {
345 r600_emit_streamout_end(ctx);
346 ctx->streamout.suspended = true;
347 }
348 }
349
350 void r600_postflush_resume_features(struct r600_common_context *ctx)
351 {
352 if (ctx->streamout.suspended) {
353 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
354 r600_streamout_buffers_dirty(ctx);
355 }
356
357 /* resume queries */
358 if (!LIST_IS_EMPTY(&ctx->active_queries))
359 r600_resume_queries(ctx);
360 }
361
362 static void r600_flush_from_st(struct pipe_context *ctx,
363 struct pipe_fence_handle **fence,
364 unsigned flags)
365 {
366 struct pipe_screen *screen = ctx->screen;
367 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
368 struct radeon_winsys *ws = rctx->ws;
369 struct pipe_fence_handle *gfx_fence = NULL;
370 struct pipe_fence_handle *sdma_fence = NULL;
371 bool deferred_fence = false;
372 unsigned rflags = RADEON_FLUSH_ASYNC;
373
374 if (flags & PIPE_FLUSH_END_OF_FRAME)
375 rflags |= RADEON_FLUSH_END_OF_FRAME;
376
377 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
378 if (rctx->dma.cs)
379 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
380
381 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
382 if (fence)
383 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
384 if (!(flags & PIPE_FLUSH_DEFERRED))
385 ws->cs_sync_flush(rctx->gfx.cs);
386 } else {
387 /* Instead of flushing, create a deferred fence. Constraints:
388 * - The state tracker must allow a deferred flush.
389 * - The state tracker must request a fence.
390 * Thread safety in fence_finish must be ensured by the state tracker.
391 */
392 if (flags & PIPE_FLUSH_DEFERRED && fence) {
393 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
394 deferred_fence = true;
395 } else {
396 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
397 }
398 }
399
400 /* Both engines can signal out of order, so we need to keep both fences. */
401 if (fence) {
402 struct r600_multi_fence *multi_fence =
403 CALLOC_STRUCT(r600_multi_fence);
404 if (!multi_fence)
405 return;
406
407 multi_fence->reference.count = 1;
408 /* If both fences are NULL, fence_finish will always return true. */
409 multi_fence->gfx = gfx_fence;
410 multi_fence->sdma = sdma_fence;
411
412 if (deferred_fence) {
413 multi_fence->gfx_unflushed.ctx = rctx;
414 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
415 }
416
417 screen->fence_reference(screen, fence, NULL);
418 *fence = (struct pipe_fence_handle*)multi_fence;
419 }
420
421 if (!(flags & PIPE_FLUSH_DEFERRED)) {
422 if (rctx->dma.cs)
423 ws->cs_sync_flush(rctx->dma.cs);
424 ws->cs_sync_flush(rctx->gfx.cs);
425 }
426 }
427
428 static void r600_flush_dma_ring(void *ctx, unsigned flags,
429 struct pipe_fence_handle **fence)
430 {
431 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
432 struct radeon_winsys_cs *cs = rctx->dma.cs;
433 struct radeon_saved_cs saved;
434 bool check_vm =
435 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
436 rctx->check_vm_faults;
437
438 if (!radeon_emitted(cs, 0)) {
439 if (fence)
440 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
441 return;
442 }
443
444 if (check_vm)
445 radeon_save_cs(rctx->ws, cs, &saved);
446
447 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
448 if (fence)
449 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
450
451 if (check_vm) {
452 /* Use conservative timeout 800ms, after which we won't wait any
453 * longer and assume the GPU is hung.
454 */
455 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
456
457 rctx->check_vm_faults(rctx, &saved, RING_DMA);
458 radeon_clear_saved_cs(&saved);
459 }
460 }
461
462 /**
463 * Store a linearized copy of all chunks of \p cs together with the buffer
464 * list in \p saved.
465 */
466 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
467 struct radeon_saved_cs *saved)
468 {
469 void *buf;
470 unsigned i;
471
472 /* Save the IB chunks. */
473 saved->num_dw = cs->prev_dw + cs->current.cdw;
474 saved->ib = MALLOC(4 * saved->num_dw);
475 if (!saved->ib)
476 goto oom;
477
478 buf = saved->ib;
479 for (i = 0; i < cs->num_prev; ++i) {
480 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
481 buf += cs->prev[i].cdw;
482 }
483 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
484
485 /* Save the buffer list. */
486 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
487 saved->bo_list = CALLOC(saved->bo_count,
488 sizeof(saved->bo_list[0]));
489 if (!saved->bo_list) {
490 FREE(saved->ib);
491 goto oom;
492 }
493 ws->cs_get_buffer_list(cs, saved->bo_list);
494
495 return;
496
497 oom:
498 fprintf(stderr, "%s: out of memory\n", __func__);
499 memset(saved, 0, sizeof(*saved));
500 }
501
502 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
503 {
504 FREE(saved->ib);
505 FREE(saved->bo_list);
506
507 memset(saved, 0, sizeof(*saved));
508 }
509
510 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
511 {
512 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
513 unsigned latest = rctx->ws->query_value(rctx->ws,
514 RADEON_GPU_RESET_COUNTER);
515
516 if (rctx->gpu_reset_counter == latest)
517 return PIPE_NO_RESET;
518
519 rctx->gpu_reset_counter = latest;
520 return PIPE_UNKNOWN_CONTEXT_RESET;
521 }
522
523 static void r600_set_debug_callback(struct pipe_context *ctx,
524 const struct pipe_debug_callback *cb)
525 {
526 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
527
528 if (cb)
529 rctx->debug = *cb;
530 else
531 memset(&rctx->debug, 0, sizeof(rctx->debug));
532 }
533
534 static void r600_set_device_reset_callback(struct pipe_context *ctx,
535 const struct pipe_device_reset_callback *cb)
536 {
537 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
538
539 if (cb)
540 rctx->device_reset_callback = *cb;
541 else
542 memset(&rctx->device_reset_callback, 0,
543 sizeof(rctx->device_reset_callback));
544 }
545
546 bool r600_check_device_reset(struct r600_common_context *rctx)
547 {
548 enum pipe_reset_status status;
549
550 if (!rctx->device_reset_callback.reset)
551 return false;
552
553 if (!rctx->b.get_device_reset_status)
554 return false;
555
556 status = rctx->b.get_device_reset_status(&rctx->b);
557 if (status == PIPE_NO_RESET)
558 return false;
559
560 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
561 return true;
562 }
563
564 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
565 struct pipe_resource *dst,
566 uint64_t offset, uint64_t size,
567 unsigned value)
568 {
569 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
570
571 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
572 }
573
574 static bool r600_resource_commit(struct pipe_context *pctx,
575 struct pipe_resource *resource,
576 unsigned level, struct pipe_box *box,
577 bool commit)
578 {
579 struct r600_common_context *ctx = (struct r600_common_context *)pctx;
580 struct r600_resource *res = r600_resource(resource);
581
582 /*
583 * Since buffer commitment changes cannot be pipelined, we need to
584 * (a) flush any pending commands that refer to the buffer we're about
585 * to change, and
586 * (b) wait for threaded submit to finish, including those that were
587 * triggered by some other, earlier operation.
588 */
589 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
590 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
591 res->buf, RADEON_USAGE_READWRITE)) {
592 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
593 }
594 if (radeon_emitted(ctx->dma.cs, 0) &&
595 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
596 res->buf, RADEON_USAGE_READWRITE)) {
597 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
598 }
599
600 ctx->ws->cs_sync_flush(ctx->dma.cs);
601 ctx->ws->cs_sync_flush(ctx->gfx.cs);
602
603 assert(resource->target == PIPE_BUFFER);
604
605 return ctx->ws->buffer_commit(res->buf, box->x, box->width, commit);
606 }
607
608 bool r600_common_context_init(struct r600_common_context *rctx,
609 struct r600_common_screen *rscreen,
610 unsigned context_flags)
611 {
612 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
613 slab_create_child(&rctx->pool_transfers_unsync, &rscreen->pool_transfers);
614
615 rctx->screen = rscreen;
616 rctx->ws = rscreen->ws;
617 rctx->family = rscreen->family;
618 rctx->chip_class = rscreen->chip_class;
619
620 rctx->b.invalidate_resource = r600_invalidate_resource;
621 rctx->b.resource_commit = r600_resource_commit;
622 rctx->b.transfer_map = u_transfer_map_vtbl;
623 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
624 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
625 rctx->b.texture_subdata = u_default_texture_subdata;
626 rctx->b.memory_barrier = r600_memory_barrier;
627 rctx->b.flush = r600_flush_from_st;
628 rctx->b.set_debug_callback = r600_set_debug_callback;
629 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
630
631 /* evergreen_compute.c has a special codepath for global buffers.
632 * Everything else can use the direct path.
633 */
634 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
635 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
636 rctx->b.buffer_subdata = u_default_buffer_subdata;
637 else
638 rctx->b.buffer_subdata = r600_buffer_subdata;
639
640 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
641 rctx->b.get_device_reset_status = r600_get_reset_status;
642 rctx->gpu_reset_counter =
643 rctx->ws->query_value(rctx->ws,
644 RADEON_GPU_RESET_COUNTER);
645 }
646
647 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
648
649 r600_init_context_texture_functions(rctx);
650 r600_init_viewport_functions(rctx);
651 r600_streamout_init(rctx);
652 r600_query_init(rctx);
653 cayman_init_msaa(&rctx->b);
654
655 rctx->allocator_zeroed_memory =
656 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
657 0, PIPE_USAGE_DEFAULT, 0, true);
658 if (!rctx->allocator_zeroed_memory)
659 return false;
660
661 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
662 0, PIPE_USAGE_STREAM);
663 if (!rctx->b.stream_uploader)
664 return false;
665
666 rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024,
667 0, PIPE_USAGE_DEFAULT);
668 if (!rctx->b.const_uploader)
669 return false;
670
671 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
672 if (!rctx->ctx)
673 return false;
674
675 if (rscreen->info.num_sdma_rings && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
676 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
677 r600_flush_dma_ring,
678 rctx);
679 rctx->dma.flush = r600_flush_dma_ring;
680 }
681
682 return true;
683 }
684
685 void r600_common_context_cleanup(struct r600_common_context *rctx)
686 {
687 unsigned i,j;
688
689 /* Release DCC stats. */
690 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
691 assert(!rctx->dcc_stats[i].query_active);
692
693 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
694 if (rctx->dcc_stats[i].ps_stats[j])
695 rctx->b.destroy_query(&rctx->b,
696 rctx->dcc_stats[i].ps_stats[j]);
697
698 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
699 }
700
701 if (rctx->query_result_shader)
702 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
703
704 if (rctx->gfx.cs)
705 rctx->ws->cs_destroy(rctx->gfx.cs);
706 if (rctx->dma.cs)
707 rctx->ws->cs_destroy(rctx->dma.cs);
708 if (rctx->ctx)
709 rctx->ws->ctx_destroy(rctx->ctx);
710
711 if (rctx->b.stream_uploader)
712 u_upload_destroy(rctx->b.stream_uploader);
713 if (rctx->b.const_uploader)
714 u_upload_destroy(rctx->b.const_uploader);
715
716 slab_destroy_child(&rctx->pool_transfers);
717 slab_destroy_child(&rctx->pool_transfers_unsync);
718
719 if (rctx->allocator_zeroed_memory) {
720 u_suballocator_destroy(rctx->allocator_zeroed_memory);
721 }
722 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
723 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
724 }
725
726 /*
727 * pipe_screen
728 */
729
730 static const struct debug_named_value common_debug_options[] = {
731 /* logging */
732 { "tex", DBG_TEX, "Print texture info" },
733 { "compute", DBG_COMPUTE, "Print compute info" },
734 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
735 { "info", DBG_INFO, "Print driver information" },
736
737 /* shaders */
738 { "fs", DBG_FS, "Print fetch shaders" },
739 { "vs", DBG_VS, "Print vertex shaders" },
740 { "gs", DBG_GS, "Print geometry shaders" },
741 { "ps", DBG_PS, "Print pixel shaders" },
742 { "cs", DBG_CS, "Print compute shaders" },
743 { "tcs", DBG_TCS, "Print tessellation control shaders" },
744 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
745 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
746 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
747 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
748 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
749 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
750 { "nooptvariant", DBG_NO_OPT_VARIANT, "Disable compiling optimized shader variants." },
751
752 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
753 { "testvmfaultcp", DBG_TEST_VMFAULT_CP, "Invoke a CP VM fault test and exit." },
754 { "testvmfaultsdma", DBG_TEST_VMFAULT_SDMA, "Invoke a SDMA VM fault test and exit." },
755 { "testvmfaultshader", DBG_TEST_VMFAULT_SHADER, "Invoke a shader VM fault test and exit." },
756
757 /* features */
758 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
759 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
760 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
761 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
762 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
763 { "notiling", DBG_NO_TILING, "Disable tiling" },
764 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
765 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
766 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
767 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
768 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
769 { "nodcc", DBG_NO_DCC, "Disable DCC." },
770 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
771 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+." },
772 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
773 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
774 { "noce", DBG_NO_CE, "Disable the constant engine"},
775 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
776 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
777
778 DEBUG_NAMED_VALUE_END /* must be last */
779 };
780
781 static const char* r600_get_vendor(struct pipe_screen* pscreen)
782 {
783 return "X.Org";
784 }
785
786 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
787 {
788 return "AMD";
789 }
790
791 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
792 {
793 switch (rscreen->info.family) {
794 case CHIP_R600: return "AMD R600";
795 case CHIP_RV610: return "AMD RV610";
796 case CHIP_RV630: return "AMD RV630";
797 case CHIP_RV670: return "AMD RV670";
798 case CHIP_RV620: return "AMD RV620";
799 case CHIP_RV635: return "AMD RV635";
800 case CHIP_RS780: return "AMD RS780";
801 case CHIP_RS880: return "AMD RS880";
802 case CHIP_RV770: return "AMD RV770";
803 case CHIP_RV730: return "AMD RV730";
804 case CHIP_RV710: return "AMD RV710";
805 case CHIP_RV740: return "AMD RV740";
806 case CHIP_CEDAR: return "AMD CEDAR";
807 case CHIP_REDWOOD: return "AMD REDWOOD";
808 case CHIP_JUNIPER: return "AMD JUNIPER";
809 case CHIP_CYPRESS: return "AMD CYPRESS";
810 case CHIP_HEMLOCK: return "AMD HEMLOCK";
811 case CHIP_PALM: return "AMD PALM";
812 case CHIP_SUMO: return "AMD SUMO";
813 case CHIP_SUMO2: return "AMD SUMO2";
814 case CHIP_BARTS: return "AMD BARTS";
815 case CHIP_TURKS: return "AMD TURKS";
816 case CHIP_CAICOS: return "AMD CAICOS";
817 case CHIP_CAYMAN: return "AMD CAYMAN";
818 case CHIP_ARUBA: return "AMD ARUBA";
819 case CHIP_TAHITI: return "AMD TAHITI";
820 case CHIP_PITCAIRN: return "AMD PITCAIRN";
821 case CHIP_VERDE: return "AMD CAPE VERDE";
822 case CHIP_OLAND: return "AMD OLAND";
823 case CHIP_HAINAN: return "AMD HAINAN";
824 case CHIP_BONAIRE: return "AMD BONAIRE";
825 case CHIP_KAVERI: return "AMD KAVERI";
826 case CHIP_KABINI: return "AMD KABINI";
827 case CHIP_HAWAII: return "AMD HAWAII";
828 case CHIP_MULLINS: return "AMD MULLINS";
829 case CHIP_TONGA: return "AMD TONGA";
830 case CHIP_ICELAND: return "AMD ICELAND";
831 case CHIP_CARRIZO: return "AMD CARRIZO";
832 case CHIP_FIJI: return "AMD FIJI";
833 case CHIP_POLARIS10: return "AMD POLARIS10";
834 case CHIP_POLARIS11: return "AMD POLARIS11";
835 case CHIP_POLARIS12: return "AMD POLARIS12";
836 case CHIP_STONEY: return "AMD STONEY";
837 case CHIP_VEGA10: return "AMD VEGA10";
838 case CHIP_RAVEN: return "AMD RAVEN";
839 default: return "AMD unknown";
840 }
841 }
842
843 static void r600_disk_cache_create(struct r600_common_screen *rscreen)
844 {
845 /* Don't use the cache if shader dumping is enabled. */
846 if (rscreen->debug_flags &
847 (DBG_FS | DBG_VS | DBG_TCS | DBG_TES | DBG_GS | DBG_PS | DBG_CS))
848 return;
849
850 uint32_t mesa_timestamp;
851 if (disk_cache_get_function_timestamp(r600_disk_cache_create,
852 &mesa_timestamp)) {
853 char *timestamp_str;
854 int res = -1;
855 if (rscreen->chip_class < SI) {
856 res = asprintf(&timestamp_str, "%u",mesa_timestamp);
857 }
858 #if HAVE_LLVM
859 else {
860 uint32_t llvm_timestamp;
861 if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
862 &llvm_timestamp)) {
863 res = asprintf(&timestamp_str, "%u_%u",
864 mesa_timestamp, llvm_timestamp);
865 }
866 }
867 #endif
868 if (res != -1) {
869 rscreen->disk_shader_cache =
870 disk_cache_create(r600_get_chip_name(rscreen),
871 timestamp_str,
872 rscreen->debug_flags);
873 free(timestamp_str);
874 }
875 }
876 }
877
878 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
879 {
880 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
881 return rscreen->disk_shader_cache;
882 }
883
884 static const char* r600_get_name(struct pipe_screen* pscreen)
885 {
886 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
887
888 return rscreen->renderer_string;
889 }
890
891 static float r600_get_paramf(struct pipe_screen* pscreen,
892 enum pipe_capf param)
893 {
894 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
895
896 switch (param) {
897 case PIPE_CAPF_MAX_LINE_WIDTH:
898 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
899 case PIPE_CAPF_MAX_POINT_WIDTH:
900 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
901 if (rscreen->family >= CHIP_CEDAR)
902 return 16384.0f;
903 else
904 return 8192.0f;
905 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
906 return 16.0f;
907 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
908 return 16.0f;
909 case PIPE_CAPF_GUARD_BAND_LEFT:
910 case PIPE_CAPF_GUARD_BAND_TOP:
911 case PIPE_CAPF_GUARD_BAND_RIGHT:
912 case PIPE_CAPF_GUARD_BAND_BOTTOM:
913 return 0.0f;
914 }
915 return 0.0f;
916 }
917
918 static int r600_get_video_param(struct pipe_screen *screen,
919 enum pipe_video_profile profile,
920 enum pipe_video_entrypoint entrypoint,
921 enum pipe_video_cap param)
922 {
923 switch (param) {
924 case PIPE_VIDEO_CAP_SUPPORTED:
925 return vl_profile_supported(screen, profile, entrypoint);
926 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
927 return 1;
928 case PIPE_VIDEO_CAP_MAX_WIDTH:
929 case PIPE_VIDEO_CAP_MAX_HEIGHT:
930 return vl_video_buffer_max_size(screen);
931 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
932 return PIPE_FORMAT_NV12;
933 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
934 return false;
935 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
936 return false;
937 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
938 return true;
939 case PIPE_VIDEO_CAP_MAX_LEVEL:
940 return vl_level_supported(screen, profile);
941 default:
942 return 0;
943 }
944 }
945
946 const char *r600_get_llvm_processor_name(enum radeon_family family)
947 {
948 switch (family) {
949 case CHIP_R600:
950 case CHIP_RV630:
951 case CHIP_RV635:
952 case CHIP_RV670:
953 return "r600";
954 case CHIP_RV610:
955 case CHIP_RV620:
956 case CHIP_RS780:
957 case CHIP_RS880:
958 return "rs880";
959 case CHIP_RV710:
960 return "rv710";
961 case CHIP_RV730:
962 return "rv730";
963 case CHIP_RV740:
964 case CHIP_RV770:
965 return "rv770";
966 case CHIP_PALM:
967 case CHIP_CEDAR:
968 return "cedar";
969 case CHIP_SUMO:
970 case CHIP_SUMO2:
971 return "sumo";
972 case CHIP_REDWOOD:
973 return "redwood";
974 case CHIP_JUNIPER:
975 return "juniper";
976 case CHIP_HEMLOCK:
977 case CHIP_CYPRESS:
978 return "cypress";
979 case CHIP_BARTS:
980 return "barts";
981 case CHIP_TURKS:
982 return "turks";
983 case CHIP_CAICOS:
984 return "caicos";
985 case CHIP_CAYMAN:
986 case CHIP_ARUBA:
987 return "cayman";
988
989 case CHIP_TAHITI: return "tahiti";
990 case CHIP_PITCAIRN: return "pitcairn";
991 case CHIP_VERDE: return "verde";
992 case CHIP_OLAND: return "oland";
993 case CHIP_HAINAN: return "hainan";
994 case CHIP_BONAIRE: return "bonaire";
995 case CHIP_KABINI: return "kabini";
996 case CHIP_KAVERI: return "kaveri";
997 case CHIP_HAWAII: return "hawaii";
998 case CHIP_MULLINS:
999 return "mullins";
1000 case CHIP_TONGA: return "tonga";
1001 case CHIP_ICELAND: return "iceland";
1002 case CHIP_CARRIZO: return "carrizo";
1003 case CHIP_FIJI:
1004 return "fiji";
1005 case CHIP_STONEY:
1006 return "stoney";
1007 case CHIP_POLARIS10:
1008 return "polaris10";
1009 case CHIP_POLARIS11:
1010 case CHIP_POLARIS12: /* same as polaris11 */
1011 return "polaris11";
1012 case CHIP_VEGA10:
1013 case CHIP_RAVEN:
1014 return "gfx900";
1015 default:
1016 return "";
1017 }
1018 }
1019
1020 static int r600_get_compute_param(struct pipe_screen *screen,
1021 enum pipe_shader_ir ir_type,
1022 enum pipe_compute_cap param,
1023 void *ret)
1024 {
1025 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
1026
1027 //TODO: select these params by asic
1028 switch (param) {
1029 case PIPE_COMPUTE_CAP_IR_TARGET: {
1030 const char *gpu;
1031 const char *triple;
1032 if (rscreen->family <= CHIP_ARUBA) {
1033 triple = "r600--";
1034 } else {
1035 if (HAVE_LLVM < 0x0400) {
1036 triple = "amdgcn--";
1037 } else {
1038 triple = "amdgcn-mesa-mesa3d";
1039 }
1040 }
1041 switch(rscreen->family) {
1042 /* Clang < 3.6 is missing Hainan in its list of
1043 * GPUs, so we need to use the name of a similar GPU.
1044 */
1045 default:
1046 gpu = r600_get_llvm_processor_name(rscreen->family);
1047 break;
1048 }
1049 if (ret) {
1050 sprintf(ret, "%s-%s", gpu, triple);
1051 }
1052 /* +2 for dash and terminating NIL byte */
1053 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
1054 }
1055 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
1056 if (ret) {
1057 uint64_t *grid_dimension = ret;
1058 grid_dimension[0] = 3;
1059 }
1060 return 1 * sizeof(uint64_t);
1061
1062 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
1063 if (ret) {
1064 uint64_t *grid_size = ret;
1065 grid_size[0] = 65535;
1066 grid_size[1] = 65535;
1067 grid_size[2] = 65535;
1068 }
1069 return 3 * sizeof(uint64_t) ;
1070
1071 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
1072 if (ret) {
1073 uint64_t *block_size = ret;
1074 if (rscreen->chip_class >= SI &&
1075 ir_type == PIPE_SHADER_IR_TGSI) {
1076 block_size[0] = 2048;
1077 block_size[1] = 2048;
1078 block_size[2] = 2048;
1079 } else {
1080 block_size[0] = 256;
1081 block_size[1] = 256;
1082 block_size[2] = 256;
1083 }
1084 }
1085 return 3 * sizeof(uint64_t);
1086
1087 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
1088 if (ret) {
1089 uint64_t *max_threads_per_block = ret;
1090 if (rscreen->chip_class >= SI &&
1091 ir_type == PIPE_SHADER_IR_TGSI)
1092 *max_threads_per_block = 2048;
1093 else
1094 *max_threads_per_block = 256;
1095 }
1096 return sizeof(uint64_t);
1097 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
1098 if (ret) {
1099 uint32_t *address_bits = ret;
1100 address_bits[0] = 32;
1101 if (rscreen->chip_class >= SI)
1102 address_bits[0] = 64;
1103 }
1104 return 1 * sizeof(uint32_t);
1105
1106 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
1107 if (ret) {
1108 uint64_t *max_global_size = ret;
1109 uint64_t max_mem_alloc_size;
1110
1111 r600_get_compute_param(screen, ir_type,
1112 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
1113 &max_mem_alloc_size);
1114
1115 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1116 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1117 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1118 * make sure we never report more than
1119 * 4 * MAX_MEM_ALLOC_SIZE.
1120 */
1121 *max_global_size = MIN2(4 * max_mem_alloc_size,
1122 MAX2(rscreen->info.gart_size,
1123 rscreen->info.vram_size));
1124 }
1125 return sizeof(uint64_t);
1126
1127 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1128 if (ret) {
1129 uint64_t *max_local_size = ret;
1130 /* Value reported by the closed source driver. */
1131 *max_local_size = 32768;
1132 }
1133 return sizeof(uint64_t);
1134
1135 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1136 if (ret) {
1137 uint64_t *max_input_size = ret;
1138 /* Value reported by the closed source driver. */
1139 *max_input_size = 1024;
1140 }
1141 return sizeof(uint64_t);
1142
1143 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1144 if (ret) {
1145 uint64_t *max_mem_alloc_size = ret;
1146
1147 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1148 }
1149 return sizeof(uint64_t);
1150
1151 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1152 if (ret) {
1153 uint32_t *max_clock_frequency = ret;
1154 *max_clock_frequency = rscreen->info.max_shader_clock;
1155 }
1156 return sizeof(uint32_t);
1157
1158 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1159 if (ret) {
1160 uint32_t *max_compute_units = ret;
1161 *max_compute_units = rscreen->info.num_good_compute_units;
1162 }
1163 return sizeof(uint32_t);
1164
1165 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1166 if (ret) {
1167 uint32_t *images_supported = ret;
1168 *images_supported = 0;
1169 }
1170 return sizeof(uint32_t);
1171 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1172 break; /* unused */
1173 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1174 if (ret) {
1175 uint32_t *subgroup_size = ret;
1176 *subgroup_size = r600_wavefront_size(rscreen->family);
1177 }
1178 return sizeof(uint32_t);
1179 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1180 if (ret) {
1181 uint64_t *max_variable_threads_per_block = ret;
1182 if (rscreen->chip_class >= SI &&
1183 ir_type == PIPE_SHADER_IR_TGSI)
1184 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
1185 else
1186 *max_variable_threads_per_block = 0;
1187 }
1188 return sizeof(uint64_t);
1189 }
1190
1191 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1192 return 0;
1193 }
1194
1195 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1196 {
1197 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1198
1199 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1200 rscreen->info.clock_crystal_freq;
1201 }
1202
1203 static void r600_fence_reference(struct pipe_screen *screen,
1204 struct pipe_fence_handle **dst,
1205 struct pipe_fence_handle *src)
1206 {
1207 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1208 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1209 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1210
1211 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1212 ws->fence_reference(&(*rdst)->gfx, NULL);
1213 ws->fence_reference(&(*rdst)->sdma, NULL);
1214 FREE(*rdst);
1215 }
1216 *rdst = rsrc;
1217 }
1218
1219 static boolean r600_fence_finish(struct pipe_screen *screen,
1220 struct pipe_context *ctx,
1221 struct pipe_fence_handle *fence,
1222 uint64_t timeout)
1223 {
1224 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1225 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1226 struct r600_common_context *rctx;
1227 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1228
1229 ctx = threaded_context_unwrap_sync(ctx);
1230 rctx = ctx ? (struct r600_common_context*)ctx : NULL;
1231
1232 if (rfence->sdma) {
1233 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1234 return false;
1235
1236 /* Recompute the timeout after waiting. */
1237 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1238 int64_t time = os_time_get_nano();
1239 timeout = abs_timeout > time ? abs_timeout - time : 0;
1240 }
1241 }
1242
1243 if (!rfence->gfx)
1244 return true;
1245
1246 /* Flush the gfx IB if it hasn't been flushed yet. */
1247 if (rctx &&
1248 rfence->gfx_unflushed.ctx == rctx &&
1249 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1250 rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
1251 rfence->gfx_unflushed.ctx = NULL;
1252
1253 if (!timeout)
1254 return false;
1255
1256 /* Recompute the timeout after all that. */
1257 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1258 int64_t time = os_time_get_nano();
1259 timeout = abs_timeout > time ? abs_timeout - time : 0;
1260 }
1261 }
1262
1263 return rws->fence_wait(rws, rfence->gfx, timeout);
1264 }
1265
1266 static void r600_query_memory_info(struct pipe_screen *screen,
1267 struct pipe_memory_info *info)
1268 {
1269 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1270 struct radeon_winsys *ws = rscreen->ws;
1271 unsigned vram_usage, gtt_usage;
1272
1273 info->total_device_memory = rscreen->info.vram_size / 1024;
1274 info->total_staging_memory = rscreen->info.gart_size / 1024;
1275
1276 /* The real TTM memory usage is somewhat random, because:
1277 *
1278 * 1) TTM delays freeing memory, because it can only free it after
1279 * fences expire.
1280 *
1281 * 2) The memory usage can be really low if big VRAM evictions are
1282 * taking place, but the real usage is well above the size of VRAM.
1283 *
1284 * Instead, return statistics of this process.
1285 */
1286 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1287 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1288
1289 info->avail_device_memory =
1290 vram_usage <= info->total_device_memory ?
1291 info->total_device_memory - vram_usage : 0;
1292 info->avail_staging_memory =
1293 gtt_usage <= info->total_staging_memory ?
1294 info->total_staging_memory - gtt_usage : 0;
1295
1296 info->device_memory_evicted =
1297 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1298
1299 if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
1300 info->nr_device_memory_evictions =
1301 ws->query_value(ws, RADEON_NUM_EVICTIONS);
1302 else
1303 /* Just return the number of evicted 64KB pages. */
1304 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1305 }
1306
1307 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1308 const struct pipe_resource *templ)
1309 {
1310 if (templ->target == PIPE_BUFFER) {
1311 return r600_buffer_create(screen, templ, 256);
1312 } else {
1313 return r600_texture_create(screen, templ);
1314 }
1315 }
1316
1317 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1318 struct radeon_winsys *ws)
1319 {
1320 char llvm_string[32] = {}, kernel_version[128] = {};
1321 struct utsname uname_data;
1322
1323 ws->query_info(ws, &rscreen->info);
1324
1325 if (uname(&uname_data) == 0)
1326 snprintf(kernel_version, sizeof(kernel_version),
1327 " / %s", uname_data.release);
1328
1329 if (HAVE_LLVM > 0) {
1330 snprintf(llvm_string, sizeof(llvm_string),
1331 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1332 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1333 }
1334
1335 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1336 "%s (DRM %i.%i.%i%s%s)",
1337 r600_get_chip_name(rscreen), rscreen->info.drm_major,
1338 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1339 kernel_version, llvm_string);
1340
1341 rscreen->b.get_name = r600_get_name;
1342 rscreen->b.get_vendor = r600_get_vendor;
1343 rscreen->b.get_device_vendor = r600_get_device_vendor;
1344 rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
1345 rscreen->b.get_compute_param = r600_get_compute_param;
1346 rscreen->b.get_paramf = r600_get_paramf;
1347 rscreen->b.get_timestamp = r600_get_timestamp;
1348 rscreen->b.fence_finish = r600_fence_finish;
1349 rscreen->b.fence_reference = r600_fence_reference;
1350 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1351 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1352 rscreen->b.query_memory_info = r600_query_memory_info;
1353
1354 if (rscreen->info.has_hw_decode) {
1355 rscreen->b.get_video_param = rvid_get_video_param;
1356 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1357 } else {
1358 rscreen->b.get_video_param = r600_get_video_param;
1359 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1360 }
1361
1362 r600_init_screen_texture_functions(rscreen);
1363 r600_init_screen_query_functions(rscreen);
1364
1365 rscreen->ws = ws;
1366 rscreen->family = rscreen->info.family;
1367 rscreen->chip_class = rscreen->info.chip_class;
1368 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1369 rscreen->has_rbplus = false;
1370 rscreen->rbplus_allowed = false;
1371
1372 r600_disk_cache_create(rscreen);
1373
1374 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1375
1376 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1377 if (rscreen->force_aniso >= 0) {
1378 printf("radeon: Forcing anisotropy filter to %ix\n",
1379 /* round down to a power of two */
1380 1 << util_logbase2(rscreen->force_aniso));
1381 }
1382
1383 util_format_s3tc_init();
1384 (void) mtx_init(&rscreen->aux_context_lock, mtx_plain);
1385 (void) mtx_init(&rscreen->gpu_load_mutex, mtx_plain);
1386
1387 if (rscreen->debug_flags & DBG_INFO) {
1388 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1389 printf("family = %i (%s)\n", rscreen->info.family,
1390 r600_get_chip_name(rscreen));
1391 printf("chip_class = %i\n", rscreen->info.chip_class);
1392 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1393 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1394 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024));
1395 printf("max_alloc_size = %i MB\n",
1396 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1397 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1398 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1399 printf("num_sdma_rings = %i\n", rscreen->info.num_sdma_rings);
1400 printf("has_hw_decode = %i\n", rscreen->info.has_hw_decode);
1401 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1402 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1403 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1404 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1405 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1406 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1407 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1408 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1409 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1410
1411 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1412 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1413 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1414 printf("max_se = %i\n", rscreen->info.max_se);
1415 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1416
1417 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1418 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1419 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1420 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1421 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1422 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1423 printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask);
1424 }
1425 return true;
1426 }
1427
1428 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1429 {
1430 r600_perfcounters_destroy(rscreen);
1431 r600_gpu_load_kill_thread(rscreen);
1432
1433 mtx_destroy(&rscreen->gpu_load_mutex);
1434 mtx_destroy(&rscreen->aux_context_lock);
1435 rscreen->aux_context->destroy(rscreen->aux_context);
1436
1437 slab_destroy_parent(&rscreen->pool_transfers);
1438
1439 disk_cache_destroy(rscreen->disk_shader_cache);
1440 rscreen->ws->destroy(rscreen->ws);
1441 FREE(rscreen);
1442 }
1443
1444 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1445 unsigned processor)
1446 {
1447 switch (processor) {
1448 case PIPE_SHADER_VERTEX:
1449 return (rscreen->debug_flags & DBG_VS) != 0;
1450 case PIPE_SHADER_TESS_CTRL:
1451 return (rscreen->debug_flags & DBG_TCS) != 0;
1452 case PIPE_SHADER_TESS_EVAL:
1453 return (rscreen->debug_flags & DBG_TES) != 0;
1454 case PIPE_SHADER_GEOMETRY:
1455 return (rscreen->debug_flags & DBG_GS) != 0;
1456 case PIPE_SHADER_FRAGMENT:
1457 return (rscreen->debug_flags & DBG_PS) != 0;
1458 case PIPE_SHADER_COMPUTE:
1459 return (rscreen->debug_flags & DBG_CS) != 0;
1460 default:
1461 return false;
1462 }
1463 }
1464
1465 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1466 {
1467 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1468 r600_can_dump_shader(rscreen, processor);
1469 }
1470
1471 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1472 uint64_t offset, uint64_t size, unsigned value)
1473 {
1474 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1475
1476 mtx_lock(&rscreen->aux_context_lock);
1477 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1478 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1479 mtx_unlock(&rscreen->aux_context_lock);
1480 }