src/gallium/drivers/radeon/r600_pipe_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 #include "r600_pipe_common.h"
  28 #include "r600_cs.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "util/list.h"
  31 #include "util/u_draw_quad.h"
  32 #include "util/u_memory.h"
  33 #include "util/u_format_s3tc.h"
  34 #include "util/u_upload_mgr.h"
  35 #include "os/os_time.h"
  36 #include "vl/vl_decoder.h"
  37 #include "vl/vl_video_buffer.h"
  38 #include "radeon/radeon_video.h"
  39 #include <inttypes.h>
  40
  41 #ifndef HAVE_LLVM
  42 #define HAVE_LLVM 0
  43 #endif
  44
  45 struct r600_multi_fence {
  46         struct pipe_reference reference;
  47         struct pipe_fence_handle *gfx;
  48         struct pipe_fence_handle *sdma;
  49 };
  50
  51 /*
  52  * shader binary helpers.
  53  */
  54 void radeon_shader_binary_init(struct radeon_shader_binary *b)
  55 {
  56         memset(b, 0, sizeof(*b));
  57 }
  58
  59 void radeon_shader_binary_clean(struct radeon_shader_binary *b)
  60 {
  61         if (!b)
  62                 return;
  63         FREE(b->code);
  64         FREE(b->config);
  65         FREE(b->rodata);
  66         FREE(b->global_symbol_offsets);
  67         FREE(b->relocs);
  68         FREE(b->disasm_string);
  69 }
  70
  71 /*
  72  * pipe_context
  73  */
  74
  75 void r600_draw_rectangle(struct blitter_context *blitter,
  76                          int x1, int y1, int x2, int y2, float depth,
  77                          enum blitter_attrib_type type,
  78                          const union pipe_color_union *attrib)
  79 {
  80         struct r600_common_context *rctx =
  81                 (struct r600_common_context*)util_blitter_get_pipe(blitter);
  82         struct pipe_viewport_state viewport;
  83         struct pipe_resource *buf = NULL;
  84         unsigned offset = 0;
  85         float *vb;
  86
  87         if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
  88                 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
  89                 return;
  90         }
  91
  92         /* Some operations (like color resolve on r6xx) don't work
  93          * with the conventional primitive types.
  94          * One that works is PT_RECTLIST, which we use here. */
  95
  96         /* setup viewport */
  97         viewport.scale[0] = 1.0f;
  98         viewport.scale[1] = 1.0f;
  99         viewport.scale[2] = 1.0f;
 100         viewport.translate[0] = 0.0f;
 101         viewport.translate[1] = 0.0f;
 102         viewport.translate[2] = 0.0f;
 103         rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
 104
 105         /* Upload vertices. The hw rectangle has only 3 vertices,
 106          * I guess the 4th one is derived from the first 3.
 107          * The vertex specification should match u_blitter's vertex element state. */
 108         u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, 256, &offset, &buf, (void**)&vb);
 109         if (!buf)
 110                 return;
 111
 112         vb[0] = x1;
 113         vb[1] = y1;
 114         vb[2] = depth;
 115         vb[3] = 1;
 116
 117         vb[8] = x1;
 118         vb[9] = y2;
 119         vb[10] = depth;
 120         vb[11] = 1;
 121
 122         vb[16] = x2;
 123         vb[17] = y1;
 124         vb[18] = depth;
 125         vb[19] = 1;
 126
 127         if (attrib) {
 128                 memcpy(vb+4, attrib->f, sizeof(float)*4);
 129                 memcpy(vb+12, attrib->f, sizeof(float)*4);
 130                 memcpy(vb+20, attrib->f, sizeof(float)*4);
 131         }
 132
 133         /* draw */
 134         util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
 135                                 R600_PRIM_RECTANGLE_LIST, 3, 2);
 136         pipe_resource_reference(&buf, NULL);
 137 }
 138
 139 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
 140 {
 141         /* Flush the GFX IB if it's not empty. */
 142         if (ctx->gfx.cs->cdw > ctx->initial_gfx_cs_size)
 143                 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
 144
 145         /* Flush if there's not enough space. */
 146         if ((num_dw + ctx->dma.cs->cdw) > ctx->dma.cs->max_dw) {
 147                 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
 148                 assert((num_dw + ctx->dma.cs->cdw) <= ctx->dma.cs->max_dw);
 149         }
 150 }
 151
 152 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
 153 {
 154 }
 155
 156 void r600_preflush_suspend_features(struct r600_common_context *ctx)
 157 {
 158         /* suspend queries */
 159         if (ctx->num_cs_dw_nontimer_queries_suspend) {
 160                 /* Since non-timer queries are suspended during blits,
 161                  * we have to guard against double-suspends. */
 162                 r600_suspend_nontimer_queries(ctx);
 163                 ctx->nontimer_queries_suspended_by_flush = true;
 164         }
 165         if (!LIST_IS_EMPTY(&ctx->active_timer_queries))
 166                 r600_suspend_timer_queries(ctx);
 167
 168         ctx->streamout.suspended = false;
 169         if (ctx->streamout.begin_emitted) {
 170                 r600_emit_streamout_end(ctx);
 171                 ctx->streamout.suspended = true;
 172         }
 173 }
 174
 175 void r600_postflush_resume_features(struct r600_common_context *ctx)
 176 {
 177         if (ctx->streamout.suspended) {
 178                 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
 179                 r600_streamout_buffers_dirty(ctx);
 180         }
 181
 182         /* resume queries */
 183         if (!LIST_IS_EMPTY(&ctx->active_timer_queries))
 184                 r600_resume_timer_queries(ctx);
 185         if (ctx->nontimer_queries_suspended_by_flush) {
 186                 ctx->nontimer_queries_suspended_by_flush = false;
 187                 r600_resume_nontimer_queries(ctx);
 188         }
 189 }
 190
 191 static void r600_flush_from_st(struct pipe_context *ctx,
 192                                struct pipe_fence_handle **fence,
 193                                unsigned flags)
 194 {
 195         struct pipe_screen *screen = ctx->screen;
 196         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 197         unsigned rflags = 0;
 198         struct pipe_fence_handle *gfx_fence = NULL;
 199         struct pipe_fence_handle *sdma_fence = NULL;
 200
 201         if (flags & PIPE_FLUSH_END_OF_FRAME)
 202                 rflags |= RADEON_FLUSH_END_OF_FRAME;
 203
 204         if (rctx->dma.cs) {
 205                 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
 206         }
 207         rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
 208
 209         /* Both engines can signal out of order, so we need to keep both fences. */
 210         if (gfx_fence || sdma_fence) {
 211                 struct r600_multi_fence *multi_fence =
 212                         CALLOC_STRUCT(r600_multi_fence);
 213                 if (!multi_fence)
 214                         return;
 215
 216                 multi_fence->reference.count = 1;
 217                 multi_fence->gfx = gfx_fence;
 218                 multi_fence->sdma = sdma_fence;
 219
 220                 screen->fence_reference(screen, fence, NULL);
 221                 *fence = (struct pipe_fence_handle*)multi_fence;
 222         }
 223 }
 224
 225 static void r600_flush_dma_ring(void *ctx, unsigned flags,
 226                                 struct pipe_fence_handle **fence)
 227 {
 228         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 229         struct radeon_winsys_cs *cs = rctx->dma.cs;
 230
 231         if (cs->cdw)
 232                 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence, 0);
 233         if (fence)
 234                 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
 235 }
 236
 237 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
 238 {
 239         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 240         unsigned latest = rctx->ws->query_value(rctx->ws,
 241                                                 RADEON_GPU_RESET_COUNTER);
 242
 243         if (rctx->gpu_reset_counter == latest)
 244                 return PIPE_NO_RESET;
 245
 246         rctx->gpu_reset_counter = latest;
 247         return PIPE_UNKNOWN_CONTEXT_RESET;
 248 }
 249
 250 static void r600_set_debug_callback(struct pipe_context *ctx,
 251                                     const struct pipe_debug_callback *cb)
 252 {
 253         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 254
 255         if (cb)
 256                 rctx->debug = *cb;
 257         else
 258                 memset(&rctx->debug, 0, sizeof(rctx->debug));
 259 }
 260
 261 bool r600_common_context_init(struct r600_common_context *rctx,
 262                               struct r600_common_screen *rscreen)
 263 {
 264         util_slab_create(&rctx->pool_transfers,
 265                          sizeof(struct r600_transfer), 64,
 266                          UTIL_SLAB_SINGLETHREADED);
 267
 268         rctx->screen = rscreen;
 269         rctx->ws = rscreen->ws;
 270         rctx->family = rscreen->family;
 271         rctx->chip_class = rscreen->chip_class;
 272
 273         if (rscreen->chip_class >= CIK)
 274                 rctx->max_db = MAX2(8, rscreen->info.num_render_backends);
 275         else if (rscreen->chip_class >= EVERGREEN)
 276                 rctx->max_db = 8;
 277         else
 278                 rctx->max_db = 4;
 279
 280         rctx->b.invalidate_resource = r600_invalidate_resource;
 281         rctx->b.transfer_map = u_transfer_map_vtbl;
 282         rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
 283         rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
 284         rctx->b.transfer_inline_write = u_default_transfer_inline_write;
 285         rctx->b.memory_barrier = r600_memory_barrier;
 286         rctx->b.flush = r600_flush_from_st;
 287         rctx->b.set_debug_callback = r600_set_debug_callback;
 288
 289         if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
 290                 rctx->b.get_device_reset_status = r600_get_reset_status;
 291                 rctx->gpu_reset_counter =
 292                         rctx->ws->query_value(rctx->ws,
 293                                               RADEON_GPU_RESET_COUNTER);
 294         }
 295
 296         LIST_INITHEAD(&rctx->texture_buffers);
 297
 298         r600_init_context_texture_functions(rctx);
 299         r600_streamout_init(rctx);
 300         r600_query_init(rctx);
 301         cayman_init_msaa(&rctx->b);
 302
 303         rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
 304                                                                0, PIPE_USAGE_DEFAULT, TRUE);
 305         if (!rctx->allocator_so_filled_size)
 306                 return false;
 307
 308         rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024,
 309                                         PIPE_BIND_INDEX_BUFFER |
 310                                         PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
 311         if (!rctx->uploader)
 312                 return false;
 313
 314         rctx->ctx = rctx->ws->ctx_create(rctx->ws);
 315         if (!rctx->ctx)
 316                 return false;
 317
 318         if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
 319                 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
 320                                                    r600_flush_dma_ring,
 321                                                    rctx, NULL);
 322                 rctx->dma.flush = r600_flush_dma_ring;
 323         }
 324
 325         return true;
 326 }
 327
 328 void r600_common_context_cleanup(struct r600_common_context *rctx)
 329 {
 330         if (rctx->gfx.cs)
 331                 rctx->ws->cs_destroy(rctx->gfx.cs);
 332         if (rctx->dma.cs)
 333                 rctx->ws->cs_destroy(rctx->dma.cs);
 334         if (rctx->ctx)
 335                 rctx->ws->ctx_destroy(rctx->ctx);
 336
 337         if (rctx->uploader) {
 338                 u_upload_destroy(rctx->uploader);
 339         }
 340
 341         util_slab_destroy(&rctx->pool_transfers);
 342
 343         if (rctx->allocator_so_filled_size) {
 344                 u_suballocator_destroy(rctx->allocator_so_filled_size);
 345         }
 346         rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
 347 }
 348
 349 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 350 {
 351         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 352         struct r600_resource *rr = (struct r600_resource *)r;
 353
 354         if (!r) {
 355                 return;
 356         }
 357
 358         /*
 359          * The idea is to compute a gross estimate of memory requirement of
 360          * each draw call. After each draw call, memory will be precisely
 361          * accounted. So the uncertainty is only on the current draw call.
 362          * In practice this gave very good estimate (+/- 10% of the target
 363          * memory limit).
 364          */
 365         if (rr->domains & RADEON_DOMAIN_GTT) {
 366                 rctx->gtt += rr->buf->size;
 367         }
 368         if (rr->domains & RADEON_DOMAIN_VRAM) {
 369                 rctx->vram += rr->buf->size;
 370         }
 371 }
 372
 373 /*
 374  * pipe_screen
 375  */
 376
 377 static const struct debug_named_value common_debug_options[] = {
 378         /* logging */
 379         { "tex", DBG_TEX, "Print texture info" },
 380         { "compute", DBG_COMPUTE, "Print compute info" },
 381         { "vm", DBG_VM, "Print virtual addresses when creating resources" },
 382         { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
 383         { "info", DBG_INFO, "Print driver information" },
 384
 385         /* shaders */
 386         { "fs", DBG_FS, "Print fetch shaders" },
 387         { "vs", DBG_VS, "Print vertex shaders" },
 388         { "gs", DBG_GS, "Print geometry shaders" },
 389         { "ps", DBG_PS, "Print pixel shaders" },
 390         { "cs", DBG_CS, "Print compute shaders" },
 391         { "tcs", DBG_TCS, "Print tessellation control shaders" },
 392         { "tes", DBG_TES, "Print tessellation evaluation shaders" },
 393         { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
 394         { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
 395         { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
 396         { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
 397
 398         /* features */
 399         { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
 400         { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
 401         /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
 402         { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
 403         { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
 404         { "notiling", DBG_NO_TILING, "Disable tiling" },
 405         { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
 406         { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
 407         { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
 408         { "nowc", DBG_NO_WC, "Disable GTT write combining" },
 409         { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
 410         { "nodcc", DBG_NO_DCC, "Disable DCC." },
 411         { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
 412         { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
 413         { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
 414
 415         DEBUG_NAMED_VALUE_END /* must be last */
 416 };
 417
 418 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 419 {
 420         return "X.Org";
 421 }
 422
 423 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
 424 {
 425         return "AMD";
 426 }
 427
 428 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
 429 {
 430         switch (rscreen->info.family) {
 431         case CHIP_R600: return "AMD R600";
 432         case CHIP_RV610: return "AMD RV610";
 433         case CHIP_RV630: return "AMD RV630";
 434         case CHIP_RV670: return "AMD RV670";
 435         case CHIP_RV620: return "AMD RV620";
 436         case CHIP_RV635: return "AMD RV635";
 437         case CHIP_RS780: return "AMD RS780";
 438         case CHIP_RS880: return "AMD RS880";
 439         case CHIP_RV770: return "AMD RV770";
 440         case CHIP_RV730: return "AMD RV730";
 441         case CHIP_RV710: return "AMD RV710";
 442         case CHIP_RV740: return "AMD RV740";
 443         case CHIP_CEDAR: return "AMD CEDAR";
 444         case CHIP_REDWOOD: return "AMD REDWOOD";
 445         case CHIP_JUNIPER: return "AMD JUNIPER";
 446         case CHIP_CYPRESS: return "AMD CYPRESS";
 447         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 448         case CHIP_PALM: return "AMD PALM";
 449         case CHIP_SUMO: return "AMD SUMO";
 450         case CHIP_SUMO2: return "AMD SUMO2";
 451         case CHIP_BARTS: return "AMD BARTS";
 452         case CHIP_TURKS: return "AMD TURKS";
 453         case CHIP_CAICOS: return "AMD CAICOS";
 454         case CHIP_CAYMAN: return "AMD CAYMAN";
 455         case CHIP_ARUBA: return "AMD ARUBA";
 456         case CHIP_TAHITI: return "AMD TAHITI";
 457         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 458         case CHIP_VERDE: return "AMD CAPE VERDE";
 459         case CHIP_OLAND: return "AMD OLAND";
 460         case CHIP_HAINAN: return "AMD HAINAN";
 461         case CHIP_BONAIRE: return "AMD BONAIRE";
 462         case CHIP_KAVERI: return "AMD KAVERI";
 463         case CHIP_KABINI: return "AMD KABINI";
 464         case CHIP_HAWAII: return "AMD HAWAII";
 465         case CHIP_MULLINS: return "AMD MULLINS";
 466         case CHIP_TONGA: return "AMD TONGA";
 467         case CHIP_ICELAND: return "AMD ICELAND";
 468         case CHIP_CARRIZO: return "AMD CARRIZO";
 469         case CHIP_FIJI: return "AMD FIJI";
 470         case CHIP_STONEY: return "AMD STONEY";
 471         default: return "AMD unknown";
 472         }
 473 }
 474
 475 static const char* r600_get_name(struct pipe_screen* pscreen)
 476 {
 477         struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
 478
 479         return rscreen->renderer_string;
 480 }
 481
 482 static float r600_get_paramf(struct pipe_screen* pscreen,
 483                              enum pipe_capf param)
 484 {
 485         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 486
 487         switch (param) {
 488         case PIPE_CAPF_MAX_LINE_WIDTH:
 489         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 490         case PIPE_CAPF_MAX_POINT_WIDTH:
 491         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 492                 if (rscreen->family >= CHIP_CEDAR)
 493                         return 16384.0f;
 494                 else
 495                         return 8192.0f;
 496         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 497                 return 16.0f;
 498         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 499                 return 16.0f;
 500         case PIPE_CAPF_GUARD_BAND_LEFT:
 501         case PIPE_CAPF_GUARD_BAND_TOP:
 502         case PIPE_CAPF_GUARD_BAND_RIGHT:
 503         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 504                 return 0.0f;
 505         }
 506         return 0.0f;
 507 }
 508
 509 static int r600_get_video_param(struct pipe_screen *screen,
 510                                 enum pipe_video_profile profile,
 511                                 enum pipe_video_entrypoint entrypoint,
 512                                 enum pipe_video_cap param)
 513 {
 514         switch (param) {
 515         case PIPE_VIDEO_CAP_SUPPORTED:
 516                 return vl_profile_supported(screen, profile, entrypoint);
 517         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 518                 return 1;
 519         case PIPE_VIDEO_CAP_MAX_WIDTH:
 520         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 521                 return vl_video_buffer_max_size(screen);
 522         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 523                 return PIPE_FORMAT_NV12;
 524         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 525                 return false;
 526         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 527                 return false;
 528         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 529                 return true;
 530         case PIPE_VIDEO_CAP_MAX_LEVEL:
 531                 return vl_level_supported(screen, profile);
 532         default:
 533                 return 0;
 534         }
 535 }
 536
 537 const char *r600_get_llvm_processor_name(enum radeon_family family)
 538 {
 539         switch (family) {
 540         case CHIP_R600:
 541         case CHIP_RV630:
 542         case CHIP_RV635:
 543         case CHIP_RV670:
 544                 return "r600";
 545         case CHIP_RV610:
 546         case CHIP_RV620:
 547         case CHIP_RS780:
 548         case CHIP_RS880:
 549                 return "rs880";
 550         case CHIP_RV710:
 551                 return "rv710";
 552         case CHIP_RV730:
 553                 return "rv730";
 554         case CHIP_RV740:
 555         case CHIP_RV770:
 556                 return "rv770";
 557         case CHIP_PALM:
 558         case CHIP_CEDAR:
 559                 return "cedar";
 560         case CHIP_SUMO:
 561         case CHIP_SUMO2:
 562                 return "sumo";
 563         case CHIP_REDWOOD:
 564                 return "redwood";
 565         case CHIP_JUNIPER:
 566                 return "juniper";
 567         case CHIP_HEMLOCK:
 568         case CHIP_CYPRESS:
 569                 return "cypress";
 570         case CHIP_BARTS:
 571                 return "barts";
 572         case CHIP_TURKS:
 573                 return "turks";
 574         case CHIP_CAICOS:
 575                 return "caicos";
 576         case CHIP_CAYMAN:
 577         case CHIP_ARUBA:
 578                 return "cayman";
 579
 580         case CHIP_TAHITI: return "tahiti";
 581         case CHIP_PITCAIRN: return "pitcairn";
 582         case CHIP_VERDE: return "verde";
 583         case CHIP_OLAND: return "oland";
 584         case CHIP_HAINAN: return "hainan";
 585         case CHIP_BONAIRE: return "bonaire";
 586         case CHIP_KABINI: return "kabini";
 587         case CHIP_KAVERI: return "kaveri";
 588         case CHIP_HAWAII: return "hawaii";
 589         case CHIP_MULLINS:
 590                 return "mullins";
 591         case CHIP_TONGA: return "tonga";
 592         case CHIP_ICELAND: return "iceland";
 593         case CHIP_CARRIZO: return "carrizo";
 594 #if HAVE_LLVM <= 0x0307
 595         case CHIP_FIJI: return "tonga";
 596         case CHIP_STONEY: return "carrizo";
 597 #else
 598         case CHIP_FIJI: return "fiji";
 599         case CHIP_STONEY: return "stoney";
 600 #endif
 601         default: return "";
 602         }
 603 }
 604
 605 static int r600_get_compute_param(struct pipe_screen *screen,
 606         enum pipe_compute_cap param,
 607         void *ret)
 608 {
 609         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
 610
 611         //TODO: select these params by asic
 612         switch (param) {
 613         case PIPE_COMPUTE_CAP_IR_TARGET: {
 614                 const char *gpu;
 615                 const char *triple;
 616                 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
 617                         triple = "r600--";
 618                 } else {
 619                         triple = "amdgcn--";
 620                 }
 621                 switch(rscreen->family) {
 622                 /* Clang < 3.6 is missing Hainan in its list of
 623                  * GPUs, so we need to use the name of a similar GPU.
 624                  */
 625 #if HAVE_LLVM < 0x0306
 626                 case CHIP_HAINAN:
 627                         gpu = "oland";
 628                         break;
 629 #endif
 630                 default:
 631                         gpu = r600_get_llvm_processor_name(rscreen->family);
 632                         break;
 633                 }
 634                 if (ret) {
 635                         sprintf(ret, "%s-%s", gpu, triple);
 636                 }
 637                 /* +2 for dash and terminating NIL byte */
 638                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 639         }
 640         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 641                 if (ret) {
 642                         uint64_t *grid_dimension = ret;
 643                         grid_dimension[0] = 3;
 644                 }
 645                 return 1 * sizeof(uint64_t);
 646
 647         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 648                 if (ret) {
 649                         uint64_t *grid_size = ret;
 650                         grid_size[0] = 65535;
 651                         grid_size[1] = 65535;
 652                         grid_size[2] = 1;
 653                 }
 654                 return 3 * sizeof(uint64_t) ;
 655
 656         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 657                 if (ret) {
 658                         uint64_t *block_size = ret;
 659                         block_size[0] = 256;
 660                         block_size[1] = 256;
 661                         block_size[2] = 256;
 662                 }
 663                 return 3 * sizeof(uint64_t);
 664
 665         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 666                 if (ret) {
 667                         uint64_t *max_threads_per_block = ret;
 668                         *max_threads_per_block = 256;
 669                 }
 670                 return sizeof(uint64_t);
 671
 672         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 673                 if (ret) {
 674                         uint64_t *max_global_size = ret;
 675                         uint64_t max_mem_alloc_size;
 676
 677                         r600_get_compute_param(screen,
 678                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 679                                 &max_mem_alloc_size);
 680
 681                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 682                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 683                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 684                          * make sure we never report more than
 685                          * 4 * MAX_MEM_ALLOC_SIZE.
 686                          */
 687                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 688                                 rscreen->info.gart_size +
 689                                 rscreen->info.vram_size);
 690                 }
 691                 return sizeof(uint64_t);
 692
 693         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 694                 if (ret) {
 695                         uint64_t *max_local_size = ret;
 696                         /* Value reported by the closed source driver. */
 697                         *max_local_size = 32768;
 698                 }
 699                 return sizeof(uint64_t);
 700
 701         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 702                 if (ret) {
 703                         uint64_t *max_input_size = ret;
 704                         /* Value reported by the closed source driver. */
 705                         *max_input_size = 1024;
 706                 }
 707                 return sizeof(uint64_t);
 708
 709         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 710                 if (ret) {
 711                         uint64_t *max_mem_alloc_size = ret;
 712
 713                         /* XXX: The limit in older kernels is 256 MB.  We
 714                          * should add a query here for newer kernels.
 715                          */
 716                         *max_mem_alloc_size = 256 * 1024 * 1024;
 717                 }
 718                 return sizeof(uint64_t);
 719
 720         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 721                 if (ret) {
 722                         uint32_t *max_clock_frequency = ret;
 723                         *max_clock_frequency = rscreen->info.max_shader_clock;
 724                 }
 725                 return sizeof(uint32_t);
 726
 727         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 728                 if (ret) {
 729                         uint32_t *max_compute_units = ret;
 730                         *max_compute_units = rscreen->info.num_good_compute_units;
 731                 }
 732                 return sizeof(uint32_t);
 733
 734         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 735                 if (ret) {
 736                         uint32_t *images_supported = ret;
 737                         *images_supported = 0;
 738                 }
 739                 return sizeof(uint32_t);
 740         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 741                 break; /* unused */
 742         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 743                 if (ret) {
 744                         uint32_t *subgroup_size = ret;
 745                         *subgroup_size = r600_wavefront_size(rscreen->family);
 746                 }
 747                 return sizeof(uint32_t);
 748         }
 749
 750         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 751         return 0;
 752 }
 753
 754 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 755 {
 756         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 757
 758         return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
 759                         rscreen->info.clock_crystal_freq;
 760 }
 761
 762 static void r600_fence_reference(struct pipe_screen *screen,
 763                                  struct pipe_fence_handle **dst,
 764                                  struct pipe_fence_handle *src)
 765 {
 766         struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
 767         struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
 768         struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
 769
 770         if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
 771                 ws->fence_reference(&(*rdst)->gfx, NULL);
 772                 ws->fence_reference(&(*rdst)->sdma, NULL);
 773                 FREE(*rdst);
 774         }
 775         *rdst = rsrc;
 776 }
 777
 778 static boolean r600_fence_finish(struct pipe_screen *screen,
 779                                  struct pipe_fence_handle *fence,
 780                                  uint64_t timeout)
 781 {
 782         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 783         struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
 784         int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
 785
 786         if (rfence->sdma) {
 787                 if (!rws->fence_wait(rws, rfence->sdma, timeout))
 788                         return false;
 789
 790                 /* Recompute the timeout after waiting. */
 791                 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
 792                         int64_t time = os_time_get_nano();
 793                         timeout = abs_timeout > time ? abs_timeout - time : 0;
 794                 }
 795         }
 796
 797         if (!rfence->gfx)
 798                 return true;
 799
 800         return rws->fence_wait(rws, rfence->gfx, timeout);
 801 }
 802
 803 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 804                                                   const struct pipe_resource *templ)
 805 {
 806         if (templ->target == PIPE_BUFFER) {
 807                 return r600_buffer_create(screen, templ, 4096);
 808         } else {
 809                 return r600_texture_create(screen, templ);
 810         }
 811 }
 812
 813 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 814                              struct radeon_winsys *ws)
 815 {
 816         char llvm_string[32] = {};
 817
 818         ws->query_info(ws, &rscreen->info);
 819
 820 #if HAVE_LLVM
 821         snprintf(llvm_string, sizeof(llvm_string),
 822                  ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
 823                  HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
 824 #endif
 825
 826         snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
 827                  "%s (DRM %i.%i.%i%s)",
 828                  r600_get_chip_name(rscreen), rscreen->info.drm_major,
 829                  rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
 830                  llvm_string);
 831
 832         rscreen->b.get_name = r600_get_name;
 833         rscreen->b.get_vendor = r600_get_vendor;
 834         rscreen->b.get_device_vendor = r600_get_device_vendor;
 835         rscreen->b.get_compute_param = r600_get_compute_param;
 836         rscreen->b.get_paramf = r600_get_paramf;
 837         rscreen->b.get_timestamp = r600_get_timestamp;
 838         rscreen->b.fence_finish = r600_fence_finish;
 839         rscreen->b.fence_reference = r600_fence_reference;
 840         rscreen->b.resource_destroy = u_resource_destroy_vtbl;
 841         rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
 842
 843         if (rscreen->info.has_uvd) {
 844                 rscreen->b.get_video_param = rvid_get_video_param;
 845                 rscreen->b.is_video_format_supported = rvid_is_format_supported;
 846         } else {
 847                 rscreen->b.get_video_param = r600_get_video_param;
 848                 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 849         }
 850
 851         r600_init_screen_texture_functions(rscreen);
 852         r600_init_screen_query_functions(rscreen);
 853
 854         rscreen->ws = ws;
 855         rscreen->family = rscreen->info.family;
 856         rscreen->chip_class = rscreen->info.chip_class;
 857         rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
 858
 859         util_format_s3tc_init();
 860         pipe_mutex_init(rscreen->aux_context_lock);
 861         pipe_mutex_init(rscreen->gpu_load_mutex);
 862
 863         if (((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 28) ||
 864              rscreen->info.drm_major == 3) &&
 865             (rscreen->debug_flags & DBG_TRACE_CS)) {
 866                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
 867                                                                                 PIPE_BIND_CUSTOM,
 868                                                                                 PIPE_USAGE_STAGING,
 869                                                                                 4096);
 870                 if (rscreen->trace_bo) {
 871                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->buf, NULL,
 872                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 873                 }
 874         }
 875
 876         if (rscreen->debug_flags & DBG_INFO) {
 877                 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
 878                 printf("family = %i (%s)\n", rscreen->info.family,
 879                        r600_get_chip_name(rscreen));
 880                 printf("chip_class = %i\n", rscreen->info.chip_class);
 881                 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
 882                 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
 883                 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
 884                 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
 885                 printf("has_sdma = %i\n", rscreen->info.has_sdma);
 886                 printf("has_uvd = %i\n", rscreen->info.has_uvd);
 887                 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
 888                 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
 889                 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
 890                 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
 891                        rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
 892                 printf("has_userptr = %i\n", rscreen->info.has_userptr);
 893
 894                 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
 895                 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
 896                 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
 897                 printf("max_se = %i\n", rscreen->info.max_se);
 898                 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
 899
 900                 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
 901                 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
 902                 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
 903                 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
 904                 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
 905                 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
 906                 printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
 907                 printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
 908         }
 909         return true;
 910 }
 911
 912 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
 913 {
 914         r600_perfcounters_destroy(rscreen);
 915         r600_gpu_load_kill_thread(rscreen);
 916
 917         pipe_mutex_destroy(rscreen->gpu_load_mutex);
 918         pipe_mutex_destroy(rscreen->aux_context_lock);
 919         rscreen->aux_context->destroy(rscreen->aux_context);
 920
 921         if (rscreen->trace_bo)
 922                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 923
 924         rscreen->ws->destroy(rscreen->ws);
 925         FREE(rscreen);
 926 }
 927
 928 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 929                           unsigned processor)
 930 {
 931         switch (processor) {
 932         case TGSI_PROCESSOR_VERTEX:
 933                 return (rscreen->debug_flags & DBG_VS) != 0;
 934         case TGSI_PROCESSOR_TESS_CTRL:
 935                 return (rscreen->debug_flags & DBG_TCS) != 0;
 936         case TGSI_PROCESSOR_TESS_EVAL:
 937                 return (rscreen->debug_flags & DBG_TES) != 0;
 938         case TGSI_PROCESSOR_GEOMETRY:
 939                 return (rscreen->debug_flags & DBG_GS) != 0;
 940         case TGSI_PROCESSOR_FRAGMENT:
 941                 return (rscreen->debug_flags & DBG_PS) != 0;
 942         case TGSI_PROCESSOR_COMPUTE:
 943                 return (rscreen->debug_flags & DBG_CS) != 0;
 944         default:
 945                 return false;
 946         }
 947 }
 948
 949 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 950                               unsigned offset, unsigned size, unsigned value,
 951                               bool is_framebuffer)
 952 {
 953         struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
 954
 955         pipe_mutex_lock(rscreen->aux_context_lock);
 956         rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
 957         rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
 958         pipe_mutex_unlock(rscreen->aux_context_lock);
 959 }