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gallium/radeon: disable the shader cache if dumping shaders
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 #if HAVE_LLVM
47 #include <llvm-c/TargetMachine.h>
48 #endif
49
50 #ifndef MESA_LLVM_VERSION_PATCH
51 #define MESA_LLVM_VERSION_PATCH 0
52 #endif
53
54 struct r600_multi_fence {
55 struct pipe_reference reference;
56 struct pipe_fence_handle *gfx;
57 struct pipe_fence_handle *sdma;
58
59 /* If the context wasn't flushed at fence creation, this is non-NULL. */
60 struct {
61 struct r600_common_context *ctx;
62 unsigned ib_index;
63 } gfx_unflushed;
64 };
65
66 /*
67 * shader binary helpers.
68 */
69 void radeon_shader_binary_init(struct ac_shader_binary *b)
70 {
71 memset(b, 0, sizeof(*b));
72 }
73
74 void radeon_shader_binary_clean(struct ac_shader_binary *b)
75 {
76 if (!b)
77 return;
78 FREE(b->code);
79 FREE(b->config);
80 FREE(b->rodata);
81 FREE(b->global_symbol_offsets);
82 FREE(b->relocs);
83 FREE(b->disasm_string);
84 FREE(b->llvm_ir_string);
85 }
86
87 /*
88 * pipe_context
89 */
90
91 /**
92 * Write an EOP event.
93 *
94 * \param event EVENT_TYPE_*
95 * \param event_flags Optional cache flush flags (TC)
96 * \param data_sel 1 = fence, 3 = timestamp
97 * \param buf Buffer
98 * \param va GPU address
99 * \param old_value Previous fence value (for a bug workaround)
100 * \param new_value Fence value to write for this event.
101 */
102 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
103 unsigned event, unsigned event_flags,
104 unsigned data_sel,
105 struct r600_resource *buf, uint64_t va,
106 uint32_t old_fence, uint32_t new_fence)
107 {
108 struct radeon_winsys_cs *cs = ctx->gfx.cs;
109 unsigned op = EVENT_TYPE(event) |
110 EVENT_INDEX(5) |
111 event_flags;
112
113 if (ctx->chip_class == CIK ||
114 ctx->chip_class == VI) {
115 /* Two EOP events are required to make all engines go idle
116 * (and optional cache flushes executed) before the timestamp
117 * is written.
118 */
119 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
120 radeon_emit(cs, op);
121 radeon_emit(cs, va);
122 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
123 radeon_emit(cs, old_fence); /* immediate data */
124 radeon_emit(cs, 0); /* unused */
125 }
126
127 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
128 radeon_emit(cs, op);
129 radeon_emit(cs, va);
130 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
131 radeon_emit(cs, new_fence); /* immediate data */
132 radeon_emit(cs, 0); /* unused */
133
134 if (buf)
135 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
136 RADEON_PRIO_QUERY);
137 }
138
139 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
140 {
141 unsigned dwords = 6;
142
143 if (screen->chip_class == CIK ||
144 screen->chip_class == VI)
145 dwords *= 2;
146
147 if (!screen->info.has_virtual_memory)
148 dwords += 2;
149
150 return dwords;
151 }
152
153 void r600_gfx_wait_fence(struct r600_common_context *ctx,
154 uint64_t va, uint32_t ref, uint32_t mask)
155 {
156 struct radeon_winsys_cs *cs = ctx->gfx.cs;
157
158 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
159 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
160 radeon_emit(cs, va);
161 radeon_emit(cs, va >> 32);
162 radeon_emit(cs, ref); /* reference value */
163 radeon_emit(cs, mask); /* mask */
164 radeon_emit(cs, 4); /* poll interval */
165 }
166
167 void r600_draw_rectangle(struct blitter_context *blitter,
168 int x1, int y1, int x2, int y2, float depth,
169 enum blitter_attrib_type type,
170 const union pipe_color_union *attrib)
171 {
172 struct r600_common_context *rctx =
173 (struct r600_common_context*)util_blitter_get_pipe(blitter);
174 struct pipe_viewport_state viewport;
175 struct pipe_resource *buf = NULL;
176 unsigned offset = 0;
177 float *vb;
178
179 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
180 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
181 return;
182 }
183
184 /* Some operations (like color resolve on r6xx) don't work
185 * with the conventional primitive types.
186 * One that works is PT_RECTLIST, which we use here. */
187
188 /* setup viewport */
189 viewport.scale[0] = 1.0f;
190 viewport.scale[1] = 1.0f;
191 viewport.scale[2] = 1.0f;
192 viewport.translate[0] = 0.0f;
193 viewport.translate[1] = 0.0f;
194 viewport.translate[2] = 0.0f;
195 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
196
197 /* Upload vertices. The hw rectangle has only 3 vertices,
198 * I guess the 4th one is derived from the first 3.
199 * The vertex specification should match u_blitter's vertex element state. */
200 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
201 rctx->screen->info.tcc_cache_line_size,
202 &offset, &buf, (void**)&vb);
203 if (!buf)
204 return;
205
206 vb[0] = x1;
207 vb[1] = y1;
208 vb[2] = depth;
209 vb[3] = 1;
210
211 vb[8] = x1;
212 vb[9] = y2;
213 vb[10] = depth;
214 vb[11] = 1;
215
216 vb[16] = x2;
217 vb[17] = y1;
218 vb[18] = depth;
219 vb[19] = 1;
220
221 if (attrib) {
222 memcpy(vb+4, attrib->f, sizeof(float)*4);
223 memcpy(vb+12, attrib->f, sizeof(float)*4);
224 memcpy(vb+20, attrib->f, sizeof(float)*4);
225 }
226
227 /* draw */
228 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
229 R600_PRIM_RECTANGLE_LIST, 3, 2);
230 pipe_resource_reference(&buf, NULL);
231 }
232
233 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
234 {
235 struct radeon_winsys_cs *cs = rctx->dma.cs;
236
237 /* NOP waits for idle on Evergreen and later. */
238 if (rctx->chip_class >= CIK)
239 radeon_emit(cs, 0x00000000); /* NOP */
240 else if (rctx->chip_class >= EVERGREEN)
241 radeon_emit(cs, 0xf0000000); /* NOP */
242 else {
243 /* TODO: R600-R700 should use the FENCE packet.
244 * CS checker support is required. */
245 }
246 }
247
248 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
249 struct r600_resource *dst, struct r600_resource *src)
250 {
251 uint64_t vram = ctx->dma.cs->used_vram;
252 uint64_t gtt = ctx->dma.cs->used_gart;
253
254 if (dst) {
255 vram += dst->vram_usage;
256 gtt += dst->gart_usage;
257 }
258 if (src) {
259 vram += src->vram_usage;
260 gtt += src->gart_usage;
261 }
262
263 /* Flush the GFX IB if DMA depends on it. */
264 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
265 ((dst &&
266 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
267 RADEON_USAGE_READWRITE)) ||
268 (src &&
269 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
270 RADEON_USAGE_WRITE))))
271 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
272
273 /* Flush if there's not enough space, or if the memory usage per IB
274 * is too large.
275 *
276 * IBs using too little memory are limited by the IB submission overhead.
277 * IBs using too much memory are limited by the kernel/TTM overhead.
278 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
279 *
280 * This heuristic makes sure that DMA requests are executed
281 * very soon after the call is made and lowers memory usage.
282 * It improves texture upload performance by keeping the DMA
283 * engine busy while uploads are being submitted.
284 */
285 num_dw++; /* for emit_wait_idle below */
286 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
287 ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 ||
288 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
289 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
290 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
291 }
292
293 /* Wait for idle if either buffer has been used in the IB before to
294 * prevent read-after-write hazards.
295 */
296 if ((dst &&
297 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, dst->buf,
298 RADEON_USAGE_READWRITE)) ||
299 (src &&
300 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, src->buf,
301 RADEON_USAGE_WRITE)))
302 r600_dma_emit_wait_idle(ctx);
303
304 /* If GPUVM is not supported, the CS checker needs 2 entries
305 * in the buffer list per packet, which has to be done manually.
306 */
307 if (ctx->screen->info.has_virtual_memory) {
308 if (dst)
309 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
310 RADEON_USAGE_WRITE,
311 RADEON_PRIO_SDMA_BUFFER);
312 if (src)
313 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
314 RADEON_USAGE_READ,
315 RADEON_PRIO_SDMA_BUFFER);
316 }
317
318 /* this function is called before all DMA calls, so increment this. */
319 ctx->num_dma_calls++;
320 }
321
322 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
323 {
324 }
325
326 void r600_preflush_suspend_features(struct r600_common_context *ctx)
327 {
328 /* suspend queries */
329 if (!LIST_IS_EMPTY(&ctx->active_queries))
330 r600_suspend_queries(ctx);
331
332 ctx->streamout.suspended = false;
333 if (ctx->streamout.begin_emitted) {
334 r600_emit_streamout_end(ctx);
335 ctx->streamout.suspended = true;
336 }
337 }
338
339 void r600_postflush_resume_features(struct r600_common_context *ctx)
340 {
341 if (ctx->streamout.suspended) {
342 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
343 r600_streamout_buffers_dirty(ctx);
344 }
345
346 /* resume queries */
347 if (!LIST_IS_EMPTY(&ctx->active_queries))
348 r600_resume_queries(ctx);
349 }
350
351 static void r600_flush_from_st(struct pipe_context *ctx,
352 struct pipe_fence_handle **fence,
353 unsigned flags)
354 {
355 struct pipe_screen *screen = ctx->screen;
356 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
357 struct radeon_winsys *ws = rctx->ws;
358 unsigned rflags = 0;
359 struct pipe_fence_handle *gfx_fence = NULL;
360 struct pipe_fence_handle *sdma_fence = NULL;
361 bool deferred_fence = false;
362
363 if (flags & PIPE_FLUSH_END_OF_FRAME)
364 rflags |= RADEON_FLUSH_END_OF_FRAME;
365 if (flags & PIPE_FLUSH_DEFERRED)
366 rflags |= RADEON_FLUSH_ASYNC;
367
368 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
369 if (rctx->dma.cs)
370 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
371
372 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
373 if (fence)
374 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
375 if (!(rflags & RADEON_FLUSH_ASYNC))
376 ws->cs_sync_flush(rctx->gfx.cs);
377 } else {
378 /* Instead of flushing, create a deferred fence. Constraints:
379 * - The state tracker must allow a deferred flush.
380 * - The state tracker must request a fence.
381 * Thread safety in fence_finish must be ensured by the state tracker.
382 */
383 if (flags & PIPE_FLUSH_DEFERRED && fence) {
384 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
385 deferred_fence = true;
386 } else {
387 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
388 }
389 }
390
391 /* Both engines can signal out of order, so we need to keep both fences. */
392 if (fence) {
393 struct r600_multi_fence *multi_fence =
394 CALLOC_STRUCT(r600_multi_fence);
395 if (!multi_fence)
396 return;
397
398 multi_fence->reference.count = 1;
399 /* If both fences are NULL, fence_finish will always return true. */
400 multi_fence->gfx = gfx_fence;
401 multi_fence->sdma = sdma_fence;
402
403 if (deferred_fence) {
404 multi_fence->gfx_unflushed.ctx = rctx;
405 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
406 }
407
408 screen->fence_reference(screen, fence, NULL);
409 *fence = (struct pipe_fence_handle*)multi_fence;
410 }
411 }
412
413 static void r600_flush_dma_ring(void *ctx, unsigned flags,
414 struct pipe_fence_handle **fence)
415 {
416 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
417 struct radeon_winsys_cs *cs = rctx->dma.cs;
418 struct radeon_saved_cs saved;
419 bool check_vm =
420 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
421 rctx->check_vm_faults;
422
423 if (!radeon_emitted(cs, 0)) {
424 if (fence)
425 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
426 return;
427 }
428
429 if (check_vm)
430 radeon_save_cs(rctx->ws, cs, &saved);
431
432 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
433 if (fence)
434 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
435
436 if (check_vm) {
437 /* Use conservative timeout 800ms, after which we won't wait any
438 * longer and assume the GPU is hung.
439 */
440 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
441
442 rctx->check_vm_faults(rctx, &saved, RING_DMA);
443 radeon_clear_saved_cs(&saved);
444 }
445 }
446
447 /**
448 * Store a linearized copy of all chunks of \p cs together with the buffer
449 * list in \p saved.
450 */
451 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
452 struct radeon_saved_cs *saved)
453 {
454 void *buf;
455 unsigned i;
456
457 /* Save the IB chunks. */
458 saved->num_dw = cs->prev_dw + cs->current.cdw;
459 saved->ib = MALLOC(4 * saved->num_dw);
460 if (!saved->ib)
461 goto oom;
462
463 buf = saved->ib;
464 for (i = 0; i < cs->num_prev; ++i) {
465 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
466 buf += cs->prev[i].cdw;
467 }
468 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
469
470 /* Save the buffer list. */
471 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
472 saved->bo_list = CALLOC(saved->bo_count,
473 sizeof(saved->bo_list[0]));
474 if (!saved->bo_list) {
475 FREE(saved->ib);
476 goto oom;
477 }
478 ws->cs_get_buffer_list(cs, saved->bo_list);
479
480 return;
481
482 oom:
483 fprintf(stderr, "%s: out of memory\n", __func__);
484 memset(saved, 0, sizeof(*saved));
485 }
486
487 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
488 {
489 FREE(saved->ib);
490 FREE(saved->bo_list);
491
492 memset(saved, 0, sizeof(*saved));
493 }
494
495 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
496 {
497 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
498 unsigned latest = rctx->ws->query_value(rctx->ws,
499 RADEON_GPU_RESET_COUNTER);
500
501 if (rctx->gpu_reset_counter == latest)
502 return PIPE_NO_RESET;
503
504 rctx->gpu_reset_counter = latest;
505 return PIPE_UNKNOWN_CONTEXT_RESET;
506 }
507
508 static void r600_set_debug_callback(struct pipe_context *ctx,
509 const struct pipe_debug_callback *cb)
510 {
511 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
512
513 if (cb)
514 rctx->debug = *cb;
515 else
516 memset(&rctx->debug, 0, sizeof(rctx->debug));
517 }
518
519 static void r600_set_device_reset_callback(struct pipe_context *ctx,
520 const struct pipe_device_reset_callback *cb)
521 {
522 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
523
524 if (cb)
525 rctx->device_reset_callback = *cb;
526 else
527 memset(&rctx->device_reset_callback, 0,
528 sizeof(rctx->device_reset_callback));
529 }
530
531 bool r600_check_device_reset(struct r600_common_context *rctx)
532 {
533 enum pipe_reset_status status;
534
535 if (!rctx->device_reset_callback.reset)
536 return false;
537
538 if (!rctx->b.get_device_reset_status)
539 return false;
540
541 status = rctx->b.get_device_reset_status(&rctx->b);
542 if (status == PIPE_NO_RESET)
543 return false;
544
545 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
546 return true;
547 }
548
549 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
550 struct pipe_resource *dst,
551 uint64_t offset, uint64_t size,
552 unsigned value)
553 {
554 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
555
556 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
557 }
558
559 bool r600_common_context_init(struct r600_common_context *rctx,
560 struct r600_common_screen *rscreen,
561 unsigned context_flags)
562 {
563 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
564
565 rctx->screen = rscreen;
566 rctx->ws = rscreen->ws;
567 rctx->family = rscreen->family;
568 rctx->chip_class = rscreen->chip_class;
569
570 rctx->b.invalidate_resource = r600_invalidate_resource;
571 rctx->b.transfer_map = u_transfer_map_vtbl;
572 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
573 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
574 rctx->b.texture_subdata = u_default_texture_subdata;
575 rctx->b.memory_barrier = r600_memory_barrier;
576 rctx->b.flush = r600_flush_from_st;
577 rctx->b.set_debug_callback = r600_set_debug_callback;
578 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
579
580 /* evergreen_compute.c has a special codepath for global buffers.
581 * Everything else can use the direct path.
582 */
583 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
584 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
585 rctx->b.buffer_subdata = u_default_buffer_subdata;
586 else
587 rctx->b.buffer_subdata = r600_buffer_subdata;
588
589 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
590 rctx->b.get_device_reset_status = r600_get_reset_status;
591 rctx->gpu_reset_counter =
592 rctx->ws->query_value(rctx->ws,
593 RADEON_GPU_RESET_COUNTER);
594 }
595
596 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
597
598 r600_init_context_texture_functions(rctx);
599 r600_init_viewport_functions(rctx);
600 r600_streamout_init(rctx);
601 r600_query_init(rctx);
602 cayman_init_msaa(&rctx->b);
603
604 rctx->allocator_zeroed_memory =
605 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
606 0, PIPE_USAGE_DEFAULT, 0, true);
607 if (!rctx->allocator_zeroed_memory)
608 return false;
609
610 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
611 0, PIPE_USAGE_STREAM);
612 if (!rctx->b.stream_uploader)
613 return false;
614
615 rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024,
616 0, PIPE_USAGE_DEFAULT);
617 if (!rctx->b.const_uploader)
618 return false;
619
620 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
621 if (!rctx->ctx)
622 return false;
623
624 if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
625 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
626 r600_flush_dma_ring,
627 rctx);
628 rctx->dma.flush = r600_flush_dma_ring;
629 }
630
631 return true;
632 }
633
634 void r600_common_context_cleanup(struct r600_common_context *rctx)
635 {
636 unsigned i,j;
637
638 /* Release DCC stats. */
639 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
640 assert(!rctx->dcc_stats[i].query_active);
641
642 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
643 if (rctx->dcc_stats[i].ps_stats[j])
644 rctx->b.destroy_query(&rctx->b,
645 rctx->dcc_stats[i].ps_stats[j]);
646
647 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
648 }
649
650 if (rctx->query_result_shader)
651 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
652
653 if (rctx->gfx.cs)
654 rctx->ws->cs_destroy(rctx->gfx.cs);
655 if (rctx->dma.cs)
656 rctx->ws->cs_destroy(rctx->dma.cs);
657 if (rctx->ctx)
658 rctx->ws->ctx_destroy(rctx->ctx);
659
660 if (rctx->b.stream_uploader)
661 u_upload_destroy(rctx->b.stream_uploader);
662 if (rctx->b.const_uploader)
663 u_upload_destroy(rctx->b.const_uploader);
664
665 slab_destroy_child(&rctx->pool_transfers);
666
667 if (rctx->allocator_zeroed_memory) {
668 u_suballocator_destroy(rctx->allocator_zeroed_memory);
669 }
670 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
671 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
672 }
673
674 /*
675 * pipe_screen
676 */
677
678 static const struct debug_named_value common_debug_options[] = {
679 /* logging */
680 { "tex", DBG_TEX, "Print texture info" },
681 { "compute", DBG_COMPUTE, "Print compute info" },
682 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
683 { "info", DBG_INFO, "Print driver information" },
684
685 /* shaders */
686 { "fs", DBG_FS, "Print fetch shaders" },
687 { "vs", DBG_VS, "Print vertex shaders" },
688 { "gs", DBG_GS, "Print geometry shaders" },
689 { "ps", DBG_PS, "Print pixel shaders" },
690 { "cs", DBG_CS, "Print compute shaders" },
691 { "tcs", DBG_TCS, "Print tessellation control shaders" },
692 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
693 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
694 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
695 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
696 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
697 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
698 { "nooptvariant", DBG_NO_OPT_VARIANT, "Disable compiling optimized shader variants." },
699
700 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
701
702 /* features */
703 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
704 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
705 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
706 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
707 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
708 { "notiling", DBG_NO_TILING, "Disable tiling" },
709 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
710 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
711 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
712 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
713 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
714 { "nodcc", DBG_NO_DCC, "Disable DCC." },
715 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
716 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
717 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
718 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
719 { "noce", DBG_NO_CE, "Disable the constant engine"},
720 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
721 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
722
723 DEBUG_NAMED_VALUE_END /* must be last */
724 };
725
726 static const char* r600_get_vendor(struct pipe_screen* pscreen)
727 {
728 return "X.Org";
729 }
730
731 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
732 {
733 return "AMD";
734 }
735
736 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
737 {
738 switch (rscreen->info.family) {
739 case CHIP_R600: return "AMD R600";
740 case CHIP_RV610: return "AMD RV610";
741 case CHIP_RV630: return "AMD RV630";
742 case CHIP_RV670: return "AMD RV670";
743 case CHIP_RV620: return "AMD RV620";
744 case CHIP_RV635: return "AMD RV635";
745 case CHIP_RS780: return "AMD RS780";
746 case CHIP_RS880: return "AMD RS880";
747 case CHIP_RV770: return "AMD RV770";
748 case CHIP_RV730: return "AMD RV730";
749 case CHIP_RV710: return "AMD RV710";
750 case CHIP_RV740: return "AMD RV740";
751 case CHIP_CEDAR: return "AMD CEDAR";
752 case CHIP_REDWOOD: return "AMD REDWOOD";
753 case CHIP_JUNIPER: return "AMD JUNIPER";
754 case CHIP_CYPRESS: return "AMD CYPRESS";
755 case CHIP_HEMLOCK: return "AMD HEMLOCK";
756 case CHIP_PALM: return "AMD PALM";
757 case CHIP_SUMO: return "AMD SUMO";
758 case CHIP_SUMO2: return "AMD SUMO2";
759 case CHIP_BARTS: return "AMD BARTS";
760 case CHIP_TURKS: return "AMD TURKS";
761 case CHIP_CAICOS: return "AMD CAICOS";
762 case CHIP_CAYMAN: return "AMD CAYMAN";
763 case CHIP_ARUBA: return "AMD ARUBA";
764 case CHIP_TAHITI: return "AMD TAHITI";
765 case CHIP_PITCAIRN: return "AMD PITCAIRN";
766 case CHIP_VERDE: return "AMD CAPE VERDE";
767 case CHIP_OLAND: return "AMD OLAND";
768 case CHIP_HAINAN: return "AMD HAINAN";
769 case CHIP_BONAIRE: return "AMD BONAIRE";
770 case CHIP_KAVERI: return "AMD KAVERI";
771 case CHIP_KABINI: return "AMD KABINI";
772 case CHIP_HAWAII: return "AMD HAWAII";
773 case CHIP_MULLINS: return "AMD MULLINS";
774 case CHIP_TONGA: return "AMD TONGA";
775 case CHIP_ICELAND: return "AMD ICELAND";
776 case CHIP_CARRIZO: return "AMD CARRIZO";
777 case CHIP_FIJI: return "AMD FIJI";
778 case CHIP_POLARIS10: return "AMD POLARIS10";
779 case CHIP_POLARIS11: return "AMD POLARIS11";
780 case CHIP_POLARIS12: return "AMD POLARIS12";
781 case CHIP_STONEY: return "AMD STONEY";
782 default: return "AMD unknown";
783 }
784 }
785
786 static void r600_disk_cache_create(struct r600_common_screen *rscreen)
787 {
788 /* Don't use the cache if shader dumping is enabled. */
789 if (rscreen->debug_flags &
790 (DBG_FS | DBG_VS | DBG_TCS | DBG_TES | DBG_GS | DBG_PS | DBG_CS))
791 return;
792
793 uint32_t mesa_timestamp;
794 if (disk_cache_get_function_timestamp(r600_disk_cache_create,
795 &mesa_timestamp)) {
796 char *timestamp_str;
797 int res = -1;
798 if (rscreen->chip_class < SI) {
799 res = asprintf(&timestamp_str, "%u",mesa_timestamp);
800 }
801 #if HAVE_LLVM
802 else {
803 uint32_t llvm_timestamp;
804 if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
805 &llvm_timestamp)) {
806 res = asprintf(&timestamp_str, "%u_%u",
807 mesa_timestamp, llvm_timestamp);
808 }
809 }
810 #endif
811 if (res != -1) {
812 rscreen->disk_shader_cache =
813 disk_cache_create(r600_get_chip_name(rscreen),
814 timestamp_str);
815 free(timestamp_str);
816 }
817 }
818 }
819
820 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
821 {
822 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
823 return rscreen->disk_shader_cache;
824 }
825
826 static const char* r600_get_name(struct pipe_screen* pscreen)
827 {
828 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
829
830 return rscreen->renderer_string;
831 }
832
833 static float r600_get_paramf(struct pipe_screen* pscreen,
834 enum pipe_capf param)
835 {
836 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
837
838 switch (param) {
839 case PIPE_CAPF_MAX_LINE_WIDTH:
840 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
841 case PIPE_CAPF_MAX_POINT_WIDTH:
842 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
843 if (rscreen->family >= CHIP_CEDAR)
844 return 16384.0f;
845 else
846 return 8192.0f;
847 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
848 return 16.0f;
849 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
850 return 16.0f;
851 case PIPE_CAPF_GUARD_BAND_LEFT:
852 case PIPE_CAPF_GUARD_BAND_TOP:
853 case PIPE_CAPF_GUARD_BAND_RIGHT:
854 case PIPE_CAPF_GUARD_BAND_BOTTOM:
855 return 0.0f;
856 }
857 return 0.0f;
858 }
859
860 static int r600_get_video_param(struct pipe_screen *screen,
861 enum pipe_video_profile profile,
862 enum pipe_video_entrypoint entrypoint,
863 enum pipe_video_cap param)
864 {
865 switch (param) {
866 case PIPE_VIDEO_CAP_SUPPORTED:
867 return vl_profile_supported(screen, profile, entrypoint);
868 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
869 return 1;
870 case PIPE_VIDEO_CAP_MAX_WIDTH:
871 case PIPE_VIDEO_CAP_MAX_HEIGHT:
872 return vl_video_buffer_max_size(screen);
873 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
874 return PIPE_FORMAT_NV12;
875 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
876 return false;
877 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
878 return false;
879 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
880 return true;
881 case PIPE_VIDEO_CAP_MAX_LEVEL:
882 return vl_level_supported(screen, profile);
883 default:
884 return 0;
885 }
886 }
887
888 const char *r600_get_llvm_processor_name(enum radeon_family family)
889 {
890 switch (family) {
891 case CHIP_R600:
892 case CHIP_RV630:
893 case CHIP_RV635:
894 case CHIP_RV670:
895 return "r600";
896 case CHIP_RV610:
897 case CHIP_RV620:
898 case CHIP_RS780:
899 case CHIP_RS880:
900 return "rs880";
901 case CHIP_RV710:
902 return "rv710";
903 case CHIP_RV730:
904 return "rv730";
905 case CHIP_RV740:
906 case CHIP_RV770:
907 return "rv770";
908 case CHIP_PALM:
909 case CHIP_CEDAR:
910 return "cedar";
911 case CHIP_SUMO:
912 case CHIP_SUMO2:
913 return "sumo";
914 case CHIP_REDWOOD:
915 return "redwood";
916 case CHIP_JUNIPER:
917 return "juniper";
918 case CHIP_HEMLOCK:
919 case CHIP_CYPRESS:
920 return "cypress";
921 case CHIP_BARTS:
922 return "barts";
923 case CHIP_TURKS:
924 return "turks";
925 case CHIP_CAICOS:
926 return "caicos";
927 case CHIP_CAYMAN:
928 case CHIP_ARUBA:
929 return "cayman";
930
931 case CHIP_TAHITI: return "tahiti";
932 case CHIP_PITCAIRN: return "pitcairn";
933 case CHIP_VERDE: return "verde";
934 case CHIP_OLAND: return "oland";
935 case CHIP_HAINAN: return "hainan";
936 case CHIP_BONAIRE: return "bonaire";
937 case CHIP_KABINI: return "kabini";
938 case CHIP_KAVERI: return "kaveri";
939 case CHIP_HAWAII: return "hawaii";
940 case CHIP_MULLINS:
941 return "mullins";
942 case CHIP_TONGA: return "tonga";
943 case CHIP_ICELAND: return "iceland";
944 case CHIP_CARRIZO: return "carrizo";
945 case CHIP_FIJI:
946 return "fiji";
947 case CHIP_STONEY:
948 return "stoney";
949 case CHIP_POLARIS10:
950 return HAVE_LLVM >= 0x0309 ? "polaris10" : "carrizo";
951 case CHIP_POLARIS11:
952 case CHIP_POLARIS12: /* same as polaris11 */
953 return HAVE_LLVM >= 0x0309 ? "polaris11" : "carrizo";
954 default:
955 return "";
956 }
957 }
958
959 static int r600_get_compute_param(struct pipe_screen *screen,
960 enum pipe_shader_ir ir_type,
961 enum pipe_compute_cap param,
962 void *ret)
963 {
964 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
965
966 //TODO: select these params by asic
967 switch (param) {
968 case PIPE_COMPUTE_CAP_IR_TARGET: {
969 const char *gpu;
970 const char *triple;
971 if (rscreen->family <= CHIP_ARUBA) {
972 triple = "r600--";
973 } else {
974 if (HAVE_LLVM < 0x0400) {
975 triple = "amdgcn--";
976 } else {
977 triple = "amdgcn-mesa-mesa3d";
978 }
979 }
980 switch(rscreen->family) {
981 /* Clang < 3.6 is missing Hainan in its list of
982 * GPUs, so we need to use the name of a similar GPU.
983 */
984 default:
985 gpu = r600_get_llvm_processor_name(rscreen->family);
986 break;
987 }
988 if (ret) {
989 sprintf(ret, "%s-%s", gpu, triple);
990 }
991 /* +2 for dash and terminating NIL byte */
992 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
993 }
994 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
995 if (ret) {
996 uint64_t *grid_dimension = ret;
997 grid_dimension[0] = 3;
998 }
999 return 1 * sizeof(uint64_t);
1000
1001 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
1002 if (ret) {
1003 uint64_t *grid_size = ret;
1004 grid_size[0] = 65535;
1005 grid_size[1] = 65535;
1006 grid_size[2] = 65535;
1007 }
1008 return 3 * sizeof(uint64_t) ;
1009
1010 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
1011 if (ret) {
1012 uint64_t *block_size = ret;
1013 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
1014 ir_type == PIPE_SHADER_IR_TGSI) {
1015 block_size[0] = 2048;
1016 block_size[1] = 2048;
1017 block_size[2] = 2048;
1018 } else {
1019 block_size[0] = 256;
1020 block_size[1] = 256;
1021 block_size[2] = 256;
1022 }
1023 }
1024 return 3 * sizeof(uint64_t);
1025
1026 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
1027 if (ret) {
1028 uint64_t *max_threads_per_block = ret;
1029 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
1030 ir_type == PIPE_SHADER_IR_TGSI)
1031 *max_threads_per_block = 2048;
1032 else
1033 *max_threads_per_block = 256;
1034 }
1035 return sizeof(uint64_t);
1036 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
1037 if (ret) {
1038 uint32_t *address_bits = ret;
1039 address_bits[0] = 32;
1040 if (rscreen->chip_class >= SI)
1041 address_bits[0] = 64;
1042 }
1043 return 1 * sizeof(uint32_t);
1044
1045 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
1046 if (ret) {
1047 uint64_t *max_global_size = ret;
1048 uint64_t max_mem_alloc_size;
1049
1050 r600_get_compute_param(screen, ir_type,
1051 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
1052 &max_mem_alloc_size);
1053
1054 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1055 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1056 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1057 * make sure we never report more than
1058 * 4 * MAX_MEM_ALLOC_SIZE.
1059 */
1060 *max_global_size = MIN2(4 * max_mem_alloc_size,
1061 MAX2(rscreen->info.gart_size,
1062 rscreen->info.vram_size));
1063 }
1064 return sizeof(uint64_t);
1065
1066 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1067 if (ret) {
1068 uint64_t *max_local_size = ret;
1069 /* Value reported by the closed source driver. */
1070 *max_local_size = 32768;
1071 }
1072 return sizeof(uint64_t);
1073
1074 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1075 if (ret) {
1076 uint64_t *max_input_size = ret;
1077 /* Value reported by the closed source driver. */
1078 *max_input_size = 1024;
1079 }
1080 return sizeof(uint64_t);
1081
1082 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1083 if (ret) {
1084 uint64_t *max_mem_alloc_size = ret;
1085
1086 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1087 }
1088 return sizeof(uint64_t);
1089
1090 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1091 if (ret) {
1092 uint32_t *max_clock_frequency = ret;
1093 *max_clock_frequency = rscreen->info.max_shader_clock;
1094 }
1095 return sizeof(uint32_t);
1096
1097 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1098 if (ret) {
1099 uint32_t *max_compute_units = ret;
1100 *max_compute_units = rscreen->info.num_good_compute_units;
1101 }
1102 return sizeof(uint32_t);
1103
1104 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1105 if (ret) {
1106 uint32_t *images_supported = ret;
1107 *images_supported = 0;
1108 }
1109 return sizeof(uint32_t);
1110 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1111 break; /* unused */
1112 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1113 if (ret) {
1114 uint32_t *subgroup_size = ret;
1115 *subgroup_size = r600_wavefront_size(rscreen->family);
1116 }
1117 return sizeof(uint32_t);
1118 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1119 if (ret) {
1120 uint64_t *max_variable_threads_per_block = ret;
1121 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
1122 ir_type == PIPE_SHADER_IR_TGSI)
1123 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
1124 else
1125 *max_variable_threads_per_block = 0;
1126 }
1127 return sizeof(uint64_t);
1128 }
1129
1130 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1131 return 0;
1132 }
1133
1134 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1135 {
1136 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1137
1138 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1139 rscreen->info.clock_crystal_freq;
1140 }
1141
1142 static void r600_fence_reference(struct pipe_screen *screen,
1143 struct pipe_fence_handle **dst,
1144 struct pipe_fence_handle *src)
1145 {
1146 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1147 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1148 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1149
1150 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1151 ws->fence_reference(&(*rdst)->gfx, NULL);
1152 ws->fence_reference(&(*rdst)->sdma, NULL);
1153 FREE(*rdst);
1154 }
1155 *rdst = rsrc;
1156 }
1157
1158 static boolean r600_fence_finish(struct pipe_screen *screen,
1159 struct pipe_context *ctx,
1160 struct pipe_fence_handle *fence,
1161 uint64_t timeout)
1162 {
1163 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1164 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1165 struct r600_common_context *rctx =
1166 ctx ? (struct r600_common_context*)ctx : NULL;
1167 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1168
1169 if (rfence->sdma) {
1170 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1171 return false;
1172
1173 /* Recompute the timeout after waiting. */
1174 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1175 int64_t time = os_time_get_nano();
1176 timeout = abs_timeout > time ? abs_timeout - time : 0;
1177 }
1178 }
1179
1180 if (!rfence->gfx)
1181 return true;
1182
1183 /* Flush the gfx IB if it hasn't been flushed yet. */
1184 if (rctx &&
1185 rfence->gfx_unflushed.ctx == rctx &&
1186 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1187 rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
1188 rfence->gfx_unflushed.ctx = NULL;
1189
1190 if (!timeout)
1191 return false;
1192
1193 /* Recompute the timeout after all that. */
1194 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1195 int64_t time = os_time_get_nano();
1196 timeout = abs_timeout > time ? abs_timeout - time : 0;
1197 }
1198 }
1199
1200 return rws->fence_wait(rws, rfence->gfx, timeout);
1201 }
1202
1203 static void r600_query_memory_info(struct pipe_screen *screen,
1204 struct pipe_memory_info *info)
1205 {
1206 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1207 struct radeon_winsys *ws = rscreen->ws;
1208 unsigned vram_usage, gtt_usage;
1209
1210 info->total_device_memory = rscreen->info.vram_size / 1024;
1211 info->total_staging_memory = rscreen->info.gart_size / 1024;
1212
1213 /* The real TTM memory usage is somewhat random, because:
1214 *
1215 * 1) TTM delays freeing memory, because it can only free it after
1216 * fences expire.
1217 *
1218 * 2) The memory usage can be really low if big VRAM evictions are
1219 * taking place, but the real usage is well above the size of VRAM.
1220 *
1221 * Instead, return statistics of this process.
1222 */
1223 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1224 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1225
1226 info->avail_device_memory =
1227 vram_usage <= info->total_device_memory ?
1228 info->total_device_memory - vram_usage : 0;
1229 info->avail_staging_memory =
1230 gtt_usage <= info->total_staging_memory ?
1231 info->total_staging_memory - gtt_usage : 0;
1232
1233 info->device_memory_evicted =
1234 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1235
1236 if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
1237 info->nr_device_memory_evictions =
1238 ws->query_value(ws, RADEON_NUM_EVICTIONS);
1239 else
1240 /* Just return the number of evicted 64KB pages. */
1241 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1242 }
1243
1244 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1245 const struct pipe_resource *templ)
1246 {
1247 if (templ->target == PIPE_BUFFER) {
1248 return r600_buffer_create(screen, templ, 256);
1249 } else {
1250 return r600_texture_create(screen, templ);
1251 }
1252 }
1253
1254 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1255 struct radeon_winsys *ws)
1256 {
1257 char llvm_string[32] = {}, kernel_version[128] = {};
1258 struct utsname uname_data;
1259
1260 ws->query_info(ws, &rscreen->info);
1261
1262 if (uname(&uname_data) == 0)
1263 snprintf(kernel_version, sizeof(kernel_version),
1264 " / %s", uname_data.release);
1265
1266 if (HAVE_LLVM > 0) {
1267 snprintf(llvm_string, sizeof(llvm_string),
1268 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1269 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1270 }
1271
1272 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1273 "%s (DRM %i.%i.%i%s%s)",
1274 r600_get_chip_name(rscreen), rscreen->info.drm_major,
1275 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1276 kernel_version, llvm_string);
1277
1278 rscreen->b.get_name = r600_get_name;
1279 rscreen->b.get_vendor = r600_get_vendor;
1280 rscreen->b.get_device_vendor = r600_get_device_vendor;
1281 rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
1282 rscreen->b.get_compute_param = r600_get_compute_param;
1283 rscreen->b.get_paramf = r600_get_paramf;
1284 rscreen->b.get_timestamp = r600_get_timestamp;
1285 rscreen->b.fence_finish = r600_fence_finish;
1286 rscreen->b.fence_reference = r600_fence_reference;
1287 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1288 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1289 rscreen->b.query_memory_info = r600_query_memory_info;
1290
1291 if (rscreen->info.has_uvd) {
1292 rscreen->b.get_video_param = rvid_get_video_param;
1293 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1294 } else {
1295 rscreen->b.get_video_param = r600_get_video_param;
1296 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1297 }
1298
1299 r600_init_screen_texture_functions(rscreen);
1300 r600_init_screen_query_functions(rscreen);
1301
1302 rscreen->ws = ws;
1303 rscreen->family = rscreen->info.family;
1304 rscreen->chip_class = rscreen->info.chip_class;
1305 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1306
1307 r600_disk_cache_create(rscreen);
1308
1309 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1310
1311 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1312 if (rscreen->force_aniso >= 0) {
1313 printf("radeon: Forcing anisotropy filter to %ix\n",
1314 /* round down to a power of two */
1315 1 << util_logbase2(rscreen->force_aniso));
1316 }
1317
1318 util_format_s3tc_init();
1319 (void) mtx_init(&rscreen->aux_context_lock, mtx_plain);
1320 (void) mtx_init(&rscreen->gpu_load_mutex, mtx_plain);
1321
1322 if (rscreen->debug_flags & DBG_INFO) {
1323 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1324 printf("family = %i (%s)\n", rscreen->info.family,
1325 r600_get_chip_name(rscreen));
1326 printf("chip_class = %i\n", rscreen->info.chip_class);
1327 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1328 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1329 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024));
1330 printf("max_alloc_size = %i MB\n",
1331 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1332 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1333 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1334 printf("has_sdma = %i\n", rscreen->info.has_sdma);
1335 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1336 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1337 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1338 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1339 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1340 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1341 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1342 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1343 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1344 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1345
1346 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1347 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1348 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1349 printf("max_se = %i\n", rscreen->info.max_se);
1350 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1351
1352 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1353 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1354 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1355 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1356 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1357 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1358 printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask);
1359 }
1360 return true;
1361 }
1362
1363 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1364 {
1365 r600_perfcounters_destroy(rscreen);
1366 r600_gpu_load_kill_thread(rscreen);
1367
1368 mtx_destroy(&rscreen->gpu_load_mutex);
1369 mtx_destroy(&rscreen->aux_context_lock);
1370 rscreen->aux_context->destroy(rscreen->aux_context);
1371
1372 slab_destroy_parent(&rscreen->pool_transfers);
1373
1374 disk_cache_destroy(rscreen->disk_shader_cache);
1375 rscreen->ws->destroy(rscreen->ws);
1376 FREE(rscreen);
1377 }
1378
1379 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1380 unsigned processor)
1381 {
1382 switch (processor) {
1383 case PIPE_SHADER_VERTEX:
1384 return (rscreen->debug_flags & DBG_VS) != 0;
1385 case PIPE_SHADER_TESS_CTRL:
1386 return (rscreen->debug_flags & DBG_TCS) != 0;
1387 case PIPE_SHADER_TESS_EVAL:
1388 return (rscreen->debug_flags & DBG_TES) != 0;
1389 case PIPE_SHADER_GEOMETRY:
1390 return (rscreen->debug_flags & DBG_GS) != 0;
1391 case PIPE_SHADER_FRAGMENT:
1392 return (rscreen->debug_flags & DBG_PS) != 0;
1393 case PIPE_SHADER_COMPUTE:
1394 return (rscreen->debug_flags & DBG_CS) != 0;
1395 default:
1396 return false;
1397 }
1398 }
1399
1400 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1401 {
1402 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1403 r600_can_dump_shader(rscreen, processor);
1404 }
1405
1406 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1407 uint64_t offset, uint64_t size, unsigned value)
1408 {
1409 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1410
1411 mtx_lock(&rscreen->aux_context_lock);
1412 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1413 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1414 mtx_unlock(&rscreen->aux_context_lock);
1415 }