src/gallium/drivers/radeon/r600_pipe_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 #include "r600_pipe_common.h"
  28 #include "r600_cs.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_format_s3tc.h"
  32 #include "util/u_upload_mgr.h"
  33 #include "vl/vl_decoder.h"
  34 #include "vl/vl_video_buffer.h"
  35 #include "radeon/radeon_video.h"
  36 #include <inttypes.h>
  37
  38 /*
  39  * pipe_context
  40  */
  41
  42 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
  43 {
  44         /* The number of dwords we already used in the DMA so far. */
  45         num_dw += ctx->rings.dma.cs->cdw;
  46         /* Flush if there's not enough space. */
  47         if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
  48                 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
  49         }
  50 }
  51
  52 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
  53 {
  54 }
  55
  56 static void r600_flush_dma_ring(void *ctx, unsigned flags)
  57 {
  58         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
  59         struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
  60
  61         if (!cs->cdw) {
  62                 return;
  63         }
  64
  65         rctx->rings.dma.flushing = true;
  66         rctx->ws->cs_flush(cs, flags, 0);
  67         rctx->rings.dma.flushing = false;
  68 }
  69
  70 static void r600_flush_dma_from_winsys(void *ctx, unsigned flags)
  71 {
  72         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
  73
  74         rctx->rings.dma.flush(rctx, flags);
  75 }
  76
  77 bool r600_common_context_init(struct r600_common_context *rctx,
  78                               struct r600_common_screen *rscreen)
  79 {
  80         util_slab_create(&rctx->pool_transfers,
  81                          sizeof(struct r600_transfer), 64,
  82                          UTIL_SLAB_SINGLETHREADED);
  83
  84         rctx->screen = rscreen;
  85         rctx->ws = rscreen->ws;
  86         rctx->family = rscreen->family;
  87         rctx->chip_class = rscreen->chip_class;
  88         rctx->max_db = rscreen->chip_class >= EVERGREEN ? 8 : 4;
  89
  90         rctx->b.transfer_map = u_transfer_map_vtbl;
  91         rctx->b.transfer_flush_region = u_default_transfer_flush_region;
  92         rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
  93         rctx->b.transfer_inline_write = u_default_transfer_inline_write;
  94         rctx->b.memory_barrier = r600_memory_barrier;
  95
  96         r600_init_context_texture_functions(rctx);
  97         r600_streamout_init(rctx);
  98         r600_query_init(rctx);
  99
 100         rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
 101                                                                0, PIPE_USAGE_DEFAULT, TRUE);
 102         if (!rctx->allocator_so_filled_size)
 103                 return false;
 104
 105         rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
 106                                         PIPE_BIND_INDEX_BUFFER |
 107                                         PIPE_BIND_CONSTANT_BUFFER);
 108         if (!rctx->uploader)
 109                 return false;
 110
 111         if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
 112                 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA,
 113                                                          r600_flush_dma_from_winsys,
 114                                                          rctx, NULL);
 115                 rctx->rings.dma.flush = r600_flush_dma_ring;
 116         }
 117
 118         return true;
 119 }
 120
 121 void r600_common_context_cleanup(struct r600_common_context *rctx)
 122 {
 123         if (rctx->rings.gfx.cs) {
 124                 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
 125         }
 126         if (rctx->rings.dma.cs) {
 127                 rctx->ws->cs_destroy(rctx->rings.dma.cs);
 128         }
 129
 130         if (rctx->uploader) {
 131                 u_upload_destroy(rctx->uploader);
 132         }
 133
 134         util_slab_destroy(&rctx->pool_transfers);
 135
 136         if (rctx->allocator_so_filled_size) {
 137                 u_suballocator_destroy(rctx->allocator_so_filled_size);
 138         }
 139 }
 140
 141 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 142 {
 143         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 144         struct r600_resource *rr = (struct r600_resource *)r;
 145
 146         if (r == NULL) {
 147                 return;
 148         }
 149
 150         /*
 151          * The idea is to compute a gross estimate of memory requirement of
 152          * each draw call. After each draw call, memory will be precisely
 153          * accounted. So the uncertainty is only on the current draw call.
 154          * In practice this gave very good estimate (+/- 10% of the target
 155          * memory limit).
 156          */
 157         if (rr->domains & RADEON_DOMAIN_GTT) {
 158                 rctx->gtt += rr->buf->size;
 159         }
 160         if (rr->domains & RADEON_DOMAIN_VRAM) {
 161                 rctx->vram += rr->buf->size;
 162         }
 163 }
 164
 165 /*
 166  * pipe_screen
 167  */
 168
 169 static const struct debug_named_value common_debug_options[] = {
 170         /* logging */
 171         { "tex", DBG_TEX, "Print texture info" },
 172         { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
 173         { "compute", DBG_COMPUTE, "Print compute info" },
 174         { "vm", DBG_VM, "Print virtual addresses when creating resources" },
 175         { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
 176
 177         /* features */
 178         { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
 179
 180         /* shaders */
 181         { "fs", DBG_FS, "Print fetch shaders" },
 182         { "vs", DBG_VS, "Print vertex shaders" },
 183         { "gs", DBG_GS, "Print geometry shaders" },
 184         { "ps", DBG_PS, "Print pixel shaders" },
 185         { "cs", DBG_CS, "Print compute shaders" },
 186
 187         { "hyperz", DBG_HYPERZ, "Enable Hyper-Z" },
 188         /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
 189         { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
 190
 191         DEBUG_NAMED_VALUE_END /* must be last */
 192 };
 193
 194 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 195 {
 196         return "X.Org";
 197 }
 198
 199 static const char* r600_get_name(struct pipe_screen* pscreen)
 200 {
 201         struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
 202
 203         switch (rscreen->family) {
 204         case CHIP_R600: return "AMD R600";
 205         case CHIP_RV610: return "AMD RV610";
 206         case CHIP_RV630: return "AMD RV630";
 207         case CHIP_RV670: return "AMD RV670";
 208         case CHIP_RV620: return "AMD RV620";
 209         case CHIP_RV635: return "AMD RV635";
 210         case CHIP_RS780: return "AMD RS780";
 211         case CHIP_RS880: return "AMD RS880";
 212         case CHIP_RV770: return "AMD RV770";
 213         case CHIP_RV730: return "AMD RV730";
 214         case CHIP_RV710: return "AMD RV710";
 215         case CHIP_RV740: return "AMD RV740";
 216         case CHIP_CEDAR: return "AMD CEDAR";
 217         case CHIP_REDWOOD: return "AMD REDWOOD";
 218         case CHIP_JUNIPER: return "AMD JUNIPER";
 219         case CHIP_CYPRESS: return "AMD CYPRESS";
 220         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 221         case CHIP_PALM: return "AMD PALM";
 222         case CHIP_SUMO: return "AMD SUMO";
 223         case CHIP_SUMO2: return "AMD SUMO2";
 224         case CHIP_BARTS: return "AMD BARTS";
 225         case CHIP_TURKS: return "AMD TURKS";
 226         case CHIP_CAICOS: return "AMD CAICOS";
 227         case CHIP_CAYMAN: return "AMD CAYMAN";
 228         case CHIP_ARUBA: return "AMD ARUBA";
 229         case CHIP_TAHITI: return "AMD TAHITI";
 230         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 231         case CHIP_VERDE: return "AMD CAPE VERDE";
 232         case CHIP_OLAND: return "AMD OLAND";
 233         case CHIP_HAINAN: return "AMD HAINAN";
 234         case CHIP_BONAIRE: return "AMD BONAIRE";
 235         case CHIP_KAVERI: return "AMD KAVERI";
 236         case CHIP_KABINI: return "AMD KABINI";
 237         case CHIP_HAWAII: return "AMD HAWAII";
 238         default: return "AMD unknown";
 239         }
 240 }
 241
 242 static float r600_get_paramf(struct pipe_screen* pscreen,
 243                              enum pipe_capf param)
 244 {
 245         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 246
 247         switch (param) {
 248         case PIPE_CAPF_MAX_LINE_WIDTH:
 249         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 250         case PIPE_CAPF_MAX_POINT_WIDTH:
 251         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 252                 if (rscreen->family >= CHIP_CEDAR)
 253                         return 16384.0f;
 254                 else
 255                         return 8192.0f;
 256         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 257                 return 16.0f;
 258         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 259                 return 16.0f;
 260         case PIPE_CAPF_GUARD_BAND_LEFT:
 261         case PIPE_CAPF_GUARD_BAND_TOP:
 262         case PIPE_CAPF_GUARD_BAND_RIGHT:
 263         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 264                 return 0.0f;
 265         }
 266         return 0.0f;
 267 }
 268
 269 static int r600_get_video_param(struct pipe_screen *screen,
 270                                 enum pipe_video_profile profile,
 271                                 enum pipe_video_entrypoint entrypoint,
 272                                 enum pipe_video_cap param)
 273 {
 274         switch (param) {
 275         case PIPE_VIDEO_CAP_SUPPORTED:
 276                 return vl_profile_supported(screen, profile, entrypoint);
 277         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 278                 return 1;
 279         case PIPE_VIDEO_CAP_MAX_WIDTH:
 280         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 281                 return vl_video_buffer_max_size(screen);
 282         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 283                 return PIPE_FORMAT_NV12;
 284         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 285                 return false;
 286         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 287                 return false;
 288         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 289                 return true;
 290         case PIPE_VIDEO_CAP_MAX_LEVEL:
 291                 return vl_level_supported(screen, profile);
 292         default:
 293                 return 0;
 294         }
 295 }
 296
 297 const char *r600_get_llvm_processor_name(enum radeon_family family)
 298 {
 299         switch (family) {
 300         case CHIP_R600:
 301         case CHIP_RV630:
 302         case CHIP_RV635:
 303         case CHIP_RV670:
 304                 return "r600";
 305         case CHIP_RV610:
 306         case CHIP_RV620:
 307         case CHIP_RS780:
 308         case CHIP_RS880:
 309                 return "rs880";
 310         case CHIP_RV710:
 311                 return "rv710";
 312         case CHIP_RV730:
 313                 return "rv730";
 314         case CHIP_RV740:
 315         case CHIP_RV770:
 316                 return "rv770";
 317         case CHIP_PALM:
 318         case CHIP_CEDAR:
 319                 return "cedar";
 320         case CHIP_SUMO:
 321         case CHIP_SUMO2:
 322                 return "sumo";
 323         case CHIP_REDWOOD:
 324                 return "redwood";
 325         case CHIP_JUNIPER:
 326                 return "juniper";
 327         case CHIP_HEMLOCK:
 328         case CHIP_CYPRESS:
 329                 return "cypress";
 330         case CHIP_BARTS:
 331                 return "barts";
 332         case CHIP_TURKS:
 333                 return "turks";
 334         case CHIP_CAICOS:
 335                 return "caicos";
 336         case CHIP_CAYMAN:
 337         case CHIP_ARUBA:
 338                 return "cayman";
 339
 340         case CHIP_TAHITI: return "tahiti";
 341         case CHIP_PITCAIRN: return "pitcairn";
 342         case CHIP_VERDE: return "verde";
 343         case CHIP_OLAND: return "oland";
 344 #if HAVE_LLVM <= 0x0303
 345         default:
 346                 fprintf(stderr, "%s: Unknown chipset = %i, defaulting to Southern Islands\n",
 347                         __func__, family);
 348                 return "SI";
 349 #else
 350         case CHIP_HAINAN: return "hainan";
 351         case CHIP_BONAIRE: return "bonaire";
 352         case CHIP_KABINI: return "kabini";
 353         case CHIP_KAVERI: return "kaveri";
 354         case CHIP_HAWAII: return "hawaii";
 355         default: return "";
 356 #endif
 357         }
 358 }
 359
 360 static int r600_get_compute_param(struct pipe_screen *screen,
 361         enum pipe_compute_cap param,
 362         void *ret)
 363 {
 364         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
 365
 366         //TODO: select these params by asic
 367         switch (param) {
 368         case PIPE_COMPUTE_CAP_IR_TARGET: {
 369                 const char *gpu = r600_get_llvm_processor_name(rscreen->family);
 370                 if (ret) {
 371                         sprintf(ret, "%s-r600--", gpu);
 372                 }
 373                 return (8 + strlen(gpu)) * sizeof(char);
 374         }
 375         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 376                 if (ret) {
 377                         uint64_t *grid_dimension = ret;
 378                         grid_dimension[0] = 3;
 379                 }
 380                 return 1 * sizeof(uint64_t);
 381
 382         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 383                 if (ret) {
 384                         uint64_t *grid_size = ret;
 385                         grid_size[0] = 65535;
 386                         grid_size[1] = 65535;
 387                         grid_size[2] = 1;
 388                 }
 389                 return 3 * sizeof(uint64_t) ;
 390
 391         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 392                 if (ret) {
 393                         uint64_t *block_size = ret;
 394                         block_size[0] = 256;
 395                         block_size[1] = 256;
 396                         block_size[2] = 256;
 397                 }
 398                 return 3 * sizeof(uint64_t);
 399
 400         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 401                 if (ret) {
 402                         uint64_t *max_threads_per_block = ret;
 403                         *max_threads_per_block = 256;
 404                 }
 405                 return sizeof(uint64_t);
 406
 407         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 408                 if (ret) {
 409                         uint64_t *max_global_size = ret;
 410                         /* XXX: This is what the proprietary driver reports, we
 411                          * may want to use a different value. */
 412                         /* XXX: Not sure what to put here for SI. */
 413                         if (rscreen->chip_class >= SI)
 414                                 *max_global_size = 2000000000;
 415                         else
 416                                 *max_global_size = 201326592;
 417                 }
 418                 return sizeof(uint64_t);
 419
 420         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 421                 if (ret) {
 422                         uint64_t *max_local_size = ret;
 423                         /* Value reported by the closed source driver. */
 424                         *max_local_size = 32768;
 425                 }
 426                 return sizeof(uint64_t);
 427
 428         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 429                 if (ret) {
 430                         uint64_t *max_input_size = ret;
 431                         /* Value reported by the closed source driver. */
 432                         *max_input_size = 1024;
 433                 }
 434                 return sizeof(uint64_t);
 435
 436         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 437                 if (ret) {
 438                         uint64_t max_global_size;
 439                         uint64_t *max_mem_alloc_size = ret;
 440                         r600_get_compute_param(screen, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, &max_global_size);
 441                         /* OpenCL requres this value be at least
 442                          * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
 443                          * I'm really not sure what value to report here, but
 444                          * MAX_GLOBAL_SIZE / 4 seems resonable.
 445                          */
 446                         *max_mem_alloc_size = max_global_size / 4;
 447                 }
 448                 return sizeof(uint64_t);
 449
 450         default:
 451                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 452                 return 0;
 453         }
 454 }
 455
 456 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 457 {
 458         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 459
 460         return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
 461                         rscreen->info.r600_clock_crystal_freq;
 462 }
 463
 464 static int r600_get_driver_query_info(struct pipe_screen *screen,
 465                                       unsigned index,
 466                                       struct pipe_driver_query_info *info)
 467 {
 468         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 469         struct pipe_driver_query_info list[] = {
 470                 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
 471                 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->info.vram_size, TRUE},
 472                 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->info.gart_size, TRUE},
 473                 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE},
 474                 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, 0, FALSE},
 475                 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, 0, TRUE},
 476                 {"VRAM-usage", R600_QUERY_VRAM_USAGE, rscreen->info.vram_size, TRUE},
 477                 {"GTT-usage", R600_QUERY_GTT_USAGE, rscreen->info.gart_size, TRUE},
 478         };
 479
 480         if (!info)
 481                 return Elements(list);
 482
 483         if (index >= Elements(list))
 484                 return 0;
 485
 486         *info = list[index];
 487         return 1;
 488 }
 489
 490 static void r600_fence_reference(struct pipe_screen *screen,
 491                                  struct pipe_fence_handle **ptr,
 492                                  struct pipe_fence_handle *fence)
 493 {
 494         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 495
 496         rws->fence_reference(ptr, fence);
 497 }
 498
 499 static boolean r600_fence_signalled(struct pipe_screen *screen,
 500                                     struct pipe_fence_handle *fence)
 501 {
 502         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 503
 504         return rws->fence_wait(rws, fence, 0);
 505 }
 506
 507 static boolean r600_fence_finish(struct pipe_screen *screen,
 508                                  struct pipe_fence_handle *fence,
 509                                  uint64_t timeout)
 510 {
 511         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 512
 513         return rws->fence_wait(rws, fence, timeout);
 514 }
 515
 516 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
 517                                   uint32_t tiling_config)
 518 {
 519         switch ((tiling_config & 0xe) >> 1) {
 520         case 0:
 521                 rscreen->tiling_info.num_channels = 1;
 522                 break;
 523         case 1:
 524                 rscreen->tiling_info.num_channels = 2;
 525                 break;
 526         case 2:
 527                 rscreen->tiling_info.num_channels = 4;
 528                 break;
 529         case 3:
 530                 rscreen->tiling_info.num_channels = 8;
 531                 break;
 532         default:
 533                 return false;
 534         }
 535
 536         switch ((tiling_config & 0x30) >> 4) {
 537         case 0:
 538                 rscreen->tiling_info.num_banks = 4;
 539                 break;
 540         case 1:
 541                 rscreen->tiling_info.num_banks = 8;
 542                 break;
 543         default:
 544                 return false;
 545
 546         }
 547         switch ((tiling_config & 0xc0) >> 6) {
 548         case 0:
 549                 rscreen->tiling_info.group_bytes = 256;
 550                 break;
 551         case 1:
 552                 rscreen->tiling_info.group_bytes = 512;
 553                 break;
 554         default:
 555                 return false;
 556         }
 557         return true;
 558 }
 559
 560 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
 561                                        uint32_t tiling_config)
 562 {
 563         switch (tiling_config & 0xf) {
 564         case 0:
 565                 rscreen->tiling_info.num_channels = 1;
 566                 break;
 567         case 1:
 568                 rscreen->tiling_info.num_channels = 2;
 569                 break;
 570         case 2:
 571                 rscreen->tiling_info.num_channels = 4;
 572                 break;
 573         case 3:
 574                 rscreen->tiling_info.num_channels = 8;
 575                 break;
 576         default:
 577                 return false;
 578         }
 579
 580         switch ((tiling_config & 0xf0) >> 4) {
 581         case 0:
 582                 rscreen->tiling_info.num_banks = 4;
 583                 break;
 584         case 1:
 585                 rscreen->tiling_info.num_banks = 8;
 586                 break;
 587         case 2:
 588                 rscreen->tiling_info.num_banks = 16;
 589                 break;
 590         default:
 591                 return false;
 592         }
 593
 594         switch ((tiling_config & 0xf00) >> 8) {
 595         case 0:
 596                 rscreen->tiling_info.group_bytes = 256;
 597                 break;
 598         case 1:
 599                 rscreen->tiling_info.group_bytes = 512;
 600                 break;
 601         default:
 602                 return false;
 603         }
 604         return true;
 605 }
 606
 607 static bool r600_init_tiling(struct r600_common_screen *rscreen)
 608 {
 609         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 610
 611         /* set default group bytes, overridden by tiling info ioctl */
 612         if (rscreen->chip_class <= R700) {
 613                 rscreen->tiling_info.group_bytes = 256;
 614         } else {
 615                 rscreen->tiling_info.group_bytes = 512;
 616         }
 617
 618         if (!tiling_config)
 619                 return true;
 620
 621         if (rscreen->chip_class <= R700) {
 622                 return r600_interpret_tiling(rscreen, tiling_config);
 623         } else {
 624                 return evergreen_interpret_tiling(rscreen, tiling_config);
 625         }
 626 }
 627
 628 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 629                                                   const struct pipe_resource *templ)
 630 {
 631         if (templ->target == PIPE_BUFFER) {
 632                 return r600_buffer_create(screen, templ, 4096);
 633         } else {
 634                 return r600_texture_create(screen, templ);
 635         }
 636 }
 637
 638 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 639                              struct radeon_winsys *ws)
 640 {
 641         ws->query_info(ws, &rscreen->info);
 642
 643         rscreen->b.get_name = r600_get_name;
 644         rscreen->b.get_vendor = r600_get_vendor;
 645         rscreen->b.get_compute_param = r600_get_compute_param;
 646         rscreen->b.get_paramf = r600_get_paramf;
 647         rscreen->b.get_driver_query_info = r600_get_driver_query_info;
 648         rscreen->b.get_timestamp = r600_get_timestamp;
 649         rscreen->b.fence_finish = r600_fence_finish;
 650         rscreen->b.fence_reference = r600_fence_reference;
 651         rscreen->b.fence_signalled = r600_fence_signalled;
 652         rscreen->b.resource_destroy = u_resource_destroy_vtbl;
 653
 654         if (rscreen->info.has_uvd) {
 655                 rscreen->b.get_video_param = rvid_get_video_param;
 656                 rscreen->b.is_video_format_supported = rvid_is_format_supported;
 657         } else {
 658                 rscreen->b.get_video_param = r600_get_video_param;
 659                 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 660         }
 661
 662         r600_init_screen_texture_functions(rscreen);
 663
 664         rscreen->ws = ws;
 665         rscreen->family = rscreen->info.family;
 666         rscreen->chip_class = rscreen->info.chip_class;
 667         rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
 668
 669         if (!r600_init_tiling(rscreen)) {
 670                 return false;
 671         }
 672         util_format_s3tc_init();
 673         pipe_mutex_init(rscreen->aux_context_lock);
 674
 675         if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
 676                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
 677                                                                                 PIPE_BIND_CUSTOM,
 678                                                                                 PIPE_USAGE_STAGING,
 679                                                                                 4096);
 680                 if (rscreen->trace_bo) {
 681                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 682                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 683                 }
 684         }
 685
 686         return true;
 687 }
 688
 689 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
 690 {
 691         pipe_mutex_destroy(rscreen->aux_context_lock);
 692         rscreen->aux_context->destroy(rscreen->aux_context);
 693
 694         if (rscreen->trace_bo) {
 695                 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 696                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 697         }
 698
 699         rscreen->ws->destroy(rscreen->ws);
 700         FREE(rscreen);
 701 }
 702
 703 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
 704 {
 705         struct tgsi_parse_context parse;
 706
 707         if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
 708                 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
 709                 return ~0;
 710         }
 711         return parse.FullHeader.Processor.Processor;
 712 }
 713
 714 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 715                           const struct tgsi_token *tokens)
 716 {
 717         /* Compute shader don't have tgsi_tokens */
 718         if (!tokens)
 719                 return (rscreen->debug_flags & DBG_CS) != 0;
 720
 721         switch (tgsi_get_processor_type(tokens)) {
 722         case TGSI_PROCESSOR_VERTEX:
 723                 return (rscreen->debug_flags & DBG_VS) != 0;
 724         case TGSI_PROCESSOR_GEOMETRY:
 725                 return (rscreen->debug_flags & DBG_GS) != 0;
 726         case TGSI_PROCESSOR_FRAGMENT:
 727                 return (rscreen->debug_flags & DBG_PS) != 0;
 728         case TGSI_PROCESSOR_COMPUTE:
 729                 return (rscreen->debug_flags & DBG_CS) != 0;
 730         default:
 731                 return false;
 732         }
 733 }
 734
 735 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 736                               unsigned offset, unsigned size, unsigned value)
 737 {
 738         struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
 739
 740         pipe_mutex_lock(rscreen->aux_context_lock);
 741         rctx->clear_buffer(&rctx->b, dst, offset, size, value);
 742         rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
 743         pipe_mutex_unlock(rscreen->aux_context_lock);
 744 }