2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
27 #include "r600_pipe_common.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
40 #include <sys/utsname.h>
46 struct r600_multi_fence
{
47 struct pipe_reference reference
;
48 struct pipe_fence_handle
*gfx
;
49 struct pipe_fence_handle
*sdma
;
51 /* If the context wasn't flushed at fence creation, this is non-NULL. */
53 struct r600_common_context
*ctx
;
59 * shader binary helpers.
61 void radeon_shader_binary_init(struct radeon_shader_binary
*b
)
63 memset(b
, 0, sizeof(*b
));
66 void radeon_shader_binary_clean(struct radeon_shader_binary
*b
)
73 FREE(b
->global_symbol_offsets
);
75 FREE(b
->disasm_string
);
76 FREE(b
->llvm_ir_string
);
83 void r600_gfx_write_fence(struct r600_common_context
*ctx
, struct r600_resource
*buf
,
84 uint64_t va
, uint32_t old_value
, uint32_t new_value
)
86 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
88 if (ctx
->chip_class
== CIK
) {
89 /* Two EOP events are required to make all engines go idle
90 * (and optional cache flushes executed) before the timestamp
93 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0));
94 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS
) |
97 radeon_emit(cs
, (va
>> 32) | EOP_DATA_SEL(1));
98 radeon_emit(cs
, old_value
); /* immediate data */
99 radeon_emit(cs
, 0); /* unused */
102 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0));
103 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS
) |
106 radeon_emit(cs
, (va
>> 32) | EOP_DATA_SEL(1));
107 radeon_emit(cs
, new_value
); /* immediate data */
108 radeon_emit(cs
, 0); /* unused */
110 r600_emit_reloc(ctx
, &ctx
->gfx
, buf
, RADEON_USAGE_WRITE
, RADEON_PRIO_QUERY
);
113 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen
*screen
)
117 if (screen
->chip_class
== CIK
)
120 if (!screen
->info
.has_virtual_memory
)
126 void r600_gfx_wait_fence(struct r600_common_context
*ctx
,
127 uint64_t va
, uint32_t ref
, uint32_t mask
)
129 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
131 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
132 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
| WAIT_REG_MEM_MEM_SPACE(1));
134 radeon_emit(cs
, va
>> 32);
135 radeon_emit(cs
, ref
); /* reference value */
136 radeon_emit(cs
, mask
); /* mask */
137 radeon_emit(cs
, 4); /* poll interval */
140 void r600_draw_rectangle(struct blitter_context
*blitter
,
141 int x1
, int y1
, int x2
, int y2
, float depth
,
142 enum blitter_attrib_type type
,
143 const union pipe_color_union
*attrib
)
145 struct r600_common_context
*rctx
=
146 (struct r600_common_context
*)util_blitter_get_pipe(blitter
);
147 struct pipe_viewport_state viewport
;
148 struct pipe_resource
*buf
= NULL
;
152 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
153 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
157 /* Some operations (like color resolve on r6xx) don't work
158 * with the conventional primitive types.
159 * One that works is PT_RECTLIST, which we use here. */
162 viewport
.scale
[0] = 1.0f
;
163 viewport
.scale
[1] = 1.0f
;
164 viewport
.scale
[2] = 1.0f
;
165 viewport
.translate
[0] = 0.0f
;
166 viewport
.translate
[1] = 0.0f
;
167 viewport
.translate
[2] = 0.0f
;
168 rctx
->b
.set_viewport_states(&rctx
->b
, 0, 1, &viewport
);
170 /* Upload vertices. The hw rectangle has only 3 vertices,
171 * I guess the 4th one is derived from the first 3.
172 * The vertex specification should match u_blitter's vertex element state. */
173 u_upload_alloc(rctx
->uploader
, 0, sizeof(float) * 24, 256, &offset
, &buf
, (void**)&vb
);
193 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
194 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
195 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
199 util_draw_vertex_buffer(&rctx
->b
, NULL
, buf
, blitter
->vb_slot
, offset
,
200 R600_PRIM_RECTANGLE_LIST
, 3, 2);
201 pipe_resource_reference(&buf
, NULL
);
204 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
,
205 struct r600_resource
*dst
, struct r600_resource
*src
)
207 uint64_t vram
= 0, gtt
= 0;
210 vram
+= dst
->vram_usage
;
211 gtt
+= dst
->gart_usage
;
214 vram
+= src
->vram_usage
;
215 gtt
+= src
->gart_usage
;
218 /* Flush the GFX IB if DMA depends on it. */
219 if (radeon_emitted(ctx
->gfx
.cs
, ctx
->initial_gfx_cs_size
) &&
221 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
, dst
->buf
,
222 RADEON_USAGE_READWRITE
)) ||
224 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
, src
->buf
,
225 RADEON_USAGE_WRITE
))))
226 ctx
->gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
228 /* Flush if there's not enough space, or if the memory usage per IB
231 if (!ctx
->ws
->cs_check_space(ctx
->dma
.cs
, num_dw
) ||
232 !radeon_cs_memory_below_limit(ctx
->screen
, ctx
->dma
.cs
, vram
, gtt
)) {
233 ctx
->dma
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
234 assert((num_dw
+ ctx
->dma
.cs
->current
.cdw
) <= ctx
->dma
.cs
->current
.max_dw
);
237 /* If GPUVM is not supported, the CS checker needs 2 entries
238 * in the buffer list per packet, which has to be done manually.
240 if (ctx
->screen
->info
.has_virtual_memory
) {
242 radeon_add_to_buffer_list(ctx
, &ctx
->dma
, dst
,
244 RADEON_PRIO_SDMA_BUFFER
);
246 radeon_add_to_buffer_list(ctx
, &ctx
->dma
, src
,
248 RADEON_PRIO_SDMA_BUFFER
);
252 /* This is required to prevent read-after-write hazards. */
253 void r600_dma_emit_wait_idle(struct r600_common_context
*rctx
)
255 struct radeon_winsys_cs
*cs
= rctx
->dma
.cs
;
257 /* done at the end of DMA calls, so increment this. */
258 rctx
->num_dma_calls
++;
260 /* IBs using too little memory are limited by the IB submission overhead.
261 * IBs using too much memory are limited by the kernel/TTM overhead.
262 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
264 * This heuristic makes sure that DMA requests are executed
265 * very soon after the call is made and lowers memory usage.
266 * It improves texture upload performance by keeping the DMA
267 * engine busy while uploads are being submitted.
269 if (cs
->used_vram
+ cs
->used_gart
> 64 * 1024 * 1024) {
270 rctx
->dma
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
274 r600_need_dma_space(rctx
, 1, NULL
, NULL
);
276 if (!radeon_emitted(cs
, 0)) /* empty queue */
279 /* NOP waits for idle on Evergreen and later. */
280 if (rctx
->chip_class
>= CIK
)
281 radeon_emit(cs
, 0x00000000); /* NOP */
282 else if (rctx
->chip_class
>= EVERGREEN
)
283 radeon_emit(cs
, 0xf0000000); /* NOP */
285 /* TODO: R600-R700 should use the FENCE packet.
286 * CS checker support is required. */
290 static void r600_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
294 void r600_preflush_suspend_features(struct r600_common_context
*ctx
)
296 /* suspend queries */
297 if (!LIST_IS_EMPTY(&ctx
->active_queries
))
298 r600_suspend_queries(ctx
);
300 ctx
->streamout
.suspended
= false;
301 if (ctx
->streamout
.begin_emitted
) {
302 r600_emit_streamout_end(ctx
);
303 ctx
->streamout
.suspended
= true;
307 void r600_postflush_resume_features(struct r600_common_context
*ctx
)
309 if (ctx
->streamout
.suspended
) {
310 ctx
->streamout
.append_bitmask
= ctx
->streamout
.enabled_mask
;
311 r600_streamout_buffers_dirty(ctx
);
315 if (!LIST_IS_EMPTY(&ctx
->active_queries
))
316 r600_resume_queries(ctx
);
319 static void r600_flush_from_st(struct pipe_context
*ctx
,
320 struct pipe_fence_handle
**fence
,
323 struct pipe_screen
*screen
= ctx
->screen
;
324 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
325 struct radeon_winsys
*ws
= rctx
->ws
;
327 struct pipe_fence_handle
*gfx_fence
= NULL
;
328 struct pipe_fence_handle
*sdma_fence
= NULL
;
329 bool deferred_fence
= false;
331 if (flags
& PIPE_FLUSH_END_OF_FRAME
)
332 rflags
|= RADEON_FLUSH_END_OF_FRAME
;
333 if (flags
& PIPE_FLUSH_DEFERRED
)
334 rflags
|= RADEON_FLUSH_ASYNC
;
337 rctx
->dma
.flush(rctx
, rflags
, fence
? &sdma_fence
: NULL
);
340 if (!radeon_emitted(rctx
->gfx
.cs
, rctx
->initial_gfx_cs_size
)) {
342 ws
->fence_reference(&gfx_fence
, rctx
->last_gfx_fence
);
343 if (!(rflags
& RADEON_FLUSH_ASYNC
))
344 ws
->cs_sync_flush(rctx
->gfx
.cs
);
346 /* Instead of flushing, create a deferred fence. Constraints:
347 * - The state tracker must allow a deferred flush.
348 * - The state tracker must request a fence.
349 * Thread safety in fence_finish must be ensured by the state tracker.
351 if (flags
& PIPE_FLUSH_DEFERRED
&& fence
) {
352 gfx_fence
= rctx
->ws
->cs_get_next_fence(rctx
->gfx
.cs
);
353 deferred_fence
= true;
355 rctx
->gfx
.flush(rctx
, rflags
, fence
? &gfx_fence
: NULL
);
359 /* Both engines can signal out of order, so we need to keep both fences. */
361 struct r600_multi_fence
*multi_fence
=
362 CALLOC_STRUCT(r600_multi_fence
);
366 multi_fence
->reference
.count
= 1;
367 /* If both fences are NULL, fence_finish will always return true. */
368 multi_fence
->gfx
= gfx_fence
;
369 multi_fence
->sdma
= sdma_fence
;
371 if (deferred_fence
) {
372 multi_fence
->gfx_unflushed
.ctx
= rctx
;
373 multi_fence
->gfx_unflushed
.ib_index
= rctx
->num_gfx_cs_flushes
;
376 screen
->fence_reference(screen
, fence
, NULL
);
377 *fence
= (struct pipe_fence_handle
*)multi_fence
;
381 static void r600_flush_dma_ring(void *ctx
, unsigned flags
,
382 struct pipe_fence_handle
**fence
)
384 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
385 struct radeon_winsys_cs
*cs
= rctx
->dma
.cs
;
386 struct radeon_saved_cs saved
;
388 (rctx
->screen
->debug_flags
& DBG_CHECK_VM
) &&
389 rctx
->check_vm_faults
;
391 if (!radeon_emitted(cs
, 0)) {
393 rctx
->ws
->fence_reference(fence
, rctx
->last_sdma_fence
);
398 radeon_save_cs(rctx
->ws
, cs
, &saved
);
400 rctx
->ws
->cs_flush(cs
, flags
, &rctx
->last_sdma_fence
);
402 rctx
->ws
->fence_reference(fence
, rctx
->last_sdma_fence
);
405 /* Use conservative timeout 800ms, after which we won't wait any
406 * longer and assume the GPU is hung.
408 rctx
->ws
->fence_wait(rctx
->ws
, rctx
->last_sdma_fence
, 800*1000*1000);
410 rctx
->check_vm_faults(rctx
, &saved
, RING_DMA
);
411 radeon_clear_saved_cs(&saved
);
416 * Store a linearized copy of all chunks of \p cs together with the buffer
419 void radeon_save_cs(struct radeon_winsys
*ws
, struct radeon_winsys_cs
*cs
,
420 struct radeon_saved_cs
*saved
)
425 /* Save the IB chunks. */
426 saved
->num_dw
= cs
->prev_dw
+ cs
->current
.cdw
;
427 saved
->ib
= MALLOC(4 * saved
->num_dw
);
432 for (i
= 0; i
< cs
->num_prev
; ++i
) {
433 memcpy(buf
, cs
->prev
[i
].buf
, cs
->prev
[i
].cdw
* 4);
434 buf
+= cs
->prev
[i
].cdw
;
436 memcpy(buf
, cs
->current
.buf
, cs
->current
.cdw
* 4);
438 /* Save the buffer list. */
439 saved
->bo_count
= ws
->cs_get_buffer_list(cs
, NULL
);
440 saved
->bo_list
= CALLOC(saved
->bo_count
,
441 sizeof(saved
->bo_list
[0]));
442 if (!saved
->bo_list
) {
446 ws
->cs_get_buffer_list(cs
, saved
->bo_list
);
451 fprintf(stderr
, "%s: out of memory\n", __func__
);
452 memset(saved
, 0, sizeof(*saved
));
455 void radeon_clear_saved_cs(struct radeon_saved_cs
*saved
)
458 FREE(saved
->bo_list
);
460 memset(saved
, 0, sizeof(*saved
));
463 static enum pipe_reset_status
r600_get_reset_status(struct pipe_context
*ctx
)
465 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
466 unsigned latest
= rctx
->ws
->query_value(rctx
->ws
,
467 RADEON_GPU_RESET_COUNTER
);
469 if (rctx
->gpu_reset_counter
== latest
)
470 return PIPE_NO_RESET
;
472 rctx
->gpu_reset_counter
= latest
;
473 return PIPE_UNKNOWN_CONTEXT_RESET
;
476 static void r600_set_debug_callback(struct pipe_context
*ctx
,
477 const struct pipe_debug_callback
*cb
)
479 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
484 memset(&rctx
->debug
, 0, sizeof(rctx
->debug
));
487 bool r600_common_context_init(struct r600_common_context
*rctx
,
488 struct r600_common_screen
*rscreen
,
489 unsigned context_flags
)
491 slab_create_child(&rctx
->pool_transfers
, &rscreen
->pool_transfers
);
493 rctx
->screen
= rscreen
;
494 rctx
->ws
= rscreen
->ws
;
495 rctx
->family
= rscreen
->family
;
496 rctx
->chip_class
= rscreen
->chip_class
;
498 if (rscreen
->chip_class
>= CIK
)
499 rctx
->max_db
= MAX2(8, rscreen
->info
.num_render_backends
);
500 else if (rscreen
->chip_class
>= EVERGREEN
)
505 rctx
->b
.invalidate_resource
= r600_invalidate_resource
;
506 rctx
->b
.transfer_map
= u_transfer_map_vtbl
;
507 rctx
->b
.transfer_flush_region
= u_transfer_flush_region_vtbl
;
508 rctx
->b
.transfer_unmap
= u_transfer_unmap_vtbl
;
509 rctx
->b
.texture_subdata
= u_default_texture_subdata
;
510 rctx
->b
.memory_barrier
= r600_memory_barrier
;
511 rctx
->b
.flush
= r600_flush_from_st
;
512 rctx
->b
.set_debug_callback
= r600_set_debug_callback
;
514 /* evergreen_compute.c has a special codepath for global buffers.
515 * Everything else can use the direct path.
517 if ((rscreen
->chip_class
== EVERGREEN
|| rscreen
->chip_class
== CAYMAN
) &&
518 (context_flags
& PIPE_CONTEXT_COMPUTE_ONLY
))
519 rctx
->b
.buffer_subdata
= u_default_buffer_subdata
;
521 rctx
->b
.buffer_subdata
= r600_buffer_subdata
;
523 if (rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
>= 43) {
524 rctx
->b
.get_device_reset_status
= r600_get_reset_status
;
525 rctx
->gpu_reset_counter
=
526 rctx
->ws
->query_value(rctx
->ws
,
527 RADEON_GPU_RESET_COUNTER
);
530 r600_init_context_texture_functions(rctx
);
531 r600_init_viewport_functions(rctx
);
532 r600_streamout_init(rctx
);
533 r600_query_init(rctx
);
534 cayman_init_msaa(&rctx
->b
);
536 rctx
->allocator_zeroed_memory
=
537 u_suballocator_create(&rctx
->b
, rscreen
->info
.gart_page_size
,
538 0, PIPE_USAGE_DEFAULT
, true);
539 if (!rctx
->allocator_zeroed_memory
)
542 rctx
->uploader
= u_upload_create(&rctx
->b
, 1024 * 1024,
543 PIPE_BIND_INDEX_BUFFER
|
544 PIPE_BIND_CONSTANT_BUFFER
, PIPE_USAGE_STREAM
);
548 rctx
->ctx
= rctx
->ws
->ctx_create(rctx
->ws
);
552 if (rscreen
->info
.has_sdma
&& !(rscreen
->debug_flags
& DBG_NO_ASYNC_DMA
)) {
553 rctx
->dma
.cs
= rctx
->ws
->cs_create(rctx
->ctx
, RING_DMA
,
556 rctx
->dma
.flush
= r600_flush_dma_ring
;
562 void r600_common_context_cleanup(struct r600_common_context
*rctx
)
566 /* Release DCC stats. */
567 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
568 assert(!rctx
->dcc_stats
[i
].query_active
);
570 for (j
= 0; j
< ARRAY_SIZE(rctx
->dcc_stats
[i
].ps_stats
); j
++)
571 if (rctx
->dcc_stats
[i
].ps_stats
[j
])
572 rctx
->b
.destroy_query(&rctx
->b
,
573 rctx
->dcc_stats
[i
].ps_stats
[j
]);
575 r600_texture_reference(&rctx
->dcc_stats
[i
].tex
, NULL
);
578 if (rctx
->query_result_shader
)
579 rctx
->b
.delete_compute_state(&rctx
->b
, rctx
->query_result_shader
);
582 rctx
->ws
->cs_destroy(rctx
->gfx
.cs
);
584 rctx
->ws
->cs_destroy(rctx
->dma
.cs
);
586 rctx
->ws
->ctx_destroy(rctx
->ctx
);
588 if (rctx
->uploader
) {
589 u_upload_destroy(rctx
->uploader
);
592 slab_destroy_child(&rctx
->pool_transfers
);
594 if (rctx
->allocator_zeroed_memory
) {
595 u_suballocator_destroy(rctx
->allocator_zeroed_memory
);
597 rctx
->ws
->fence_reference(&rctx
->last_gfx_fence
, NULL
);
598 rctx
->ws
->fence_reference(&rctx
->last_sdma_fence
, NULL
);
605 static const struct debug_named_value common_debug_options
[] = {
607 { "tex", DBG_TEX
, "Print texture info" },
608 { "compute", DBG_COMPUTE
, "Print compute info" },
609 { "vm", DBG_VM
, "Print virtual addresses when creating resources" },
610 { "info", DBG_INFO
, "Print driver information" },
613 { "fs", DBG_FS
, "Print fetch shaders" },
614 { "vs", DBG_VS
, "Print vertex shaders" },
615 { "gs", DBG_GS
, "Print geometry shaders" },
616 { "ps", DBG_PS
, "Print pixel shaders" },
617 { "cs", DBG_CS
, "Print compute shaders" },
618 { "tcs", DBG_TCS
, "Print tessellation control shaders" },
619 { "tes", DBG_TES
, "Print tessellation evaluation shaders" },
620 { "noir", DBG_NO_IR
, "Don't print the LLVM IR"},
621 { "notgsi", DBG_NO_TGSI
, "Don't print the TGSI"},
622 { "noasm", DBG_NO_ASM
, "Don't print disassembled shaders"},
623 { "preoptir", DBG_PREOPT_IR
, "Print the LLVM IR before initial optimizations" },
624 { "checkir", DBG_CHECK_IR
, "Enable additional sanity checks on shader IR" },
626 { "testdma", DBG_TEST_DMA
, "Invoke SDMA tests and exit." },
629 { "nodma", DBG_NO_ASYNC_DMA
, "Disable asynchronous DMA" },
630 { "nohyperz", DBG_NO_HYPERZ
, "Disable Hyper-Z" },
631 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
632 { "noinvalrange", DBG_NO_DISCARD_RANGE
, "Disable handling of INVALIDATE_RANGE map flags" },
633 { "no2d", DBG_NO_2D_TILING
, "Disable 2D tiling" },
634 { "notiling", DBG_NO_TILING
, "Disable tiling" },
635 { "switch_on_eop", DBG_SWITCH_ON_EOP
, "Program WD/IA to switch on end-of-packet." },
636 { "forcedma", DBG_FORCE_DMA
, "Use asynchronous DMA for all operations when possible." },
637 { "precompile", DBG_PRECOMPILE
, "Compile one shader variant at shader creation." },
638 { "nowc", DBG_NO_WC
, "Disable GTT write combining" },
639 { "check_vm", DBG_CHECK_VM
, "Check VM faults and dump debug info." },
640 { "nodcc", DBG_NO_DCC
, "Disable DCC." },
641 { "nodccclear", DBG_NO_DCC_CLEAR
, "Disable DCC fast clear." },
642 { "norbplus", DBG_NO_RB_PLUS
, "Disable RB+ on Stoney." },
643 { "sisched", DBG_SI_SCHED
, "Enable LLVM SI Machine Instruction Scheduler." },
644 { "mono", DBG_MONOLITHIC_SHADERS
, "Use old-style monolithic shaders compiled on demand" },
645 { "noce", DBG_NO_CE
, "Disable the constant engine"},
646 { "unsafemath", DBG_UNSAFE_MATH
, "Enable unsafe math shader optimizations" },
647 { "nodccfb", DBG_NO_DCC_FB
, "Disable separate DCC on the main framebuffer" },
649 DEBUG_NAMED_VALUE_END
/* must be last */
652 static const char* r600_get_vendor(struct pipe_screen
* pscreen
)
657 static const char* r600_get_device_vendor(struct pipe_screen
* pscreen
)
662 static const char* r600_get_chip_name(struct r600_common_screen
*rscreen
)
664 switch (rscreen
->info
.family
) {
665 case CHIP_R600
: return "AMD R600";
666 case CHIP_RV610
: return "AMD RV610";
667 case CHIP_RV630
: return "AMD RV630";
668 case CHIP_RV670
: return "AMD RV670";
669 case CHIP_RV620
: return "AMD RV620";
670 case CHIP_RV635
: return "AMD RV635";
671 case CHIP_RS780
: return "AMD RS780";
672 case CHIP_RS880
: return "AMD RS880";
673 case CHIP_RV770
: return "AMD RV770";
674 case CHIP_RV730
: return "AMD RV730";
675 case CHIP_RV710
: return "AMD RV710";
676 case CHIP_RV740
: return "AMD RV740";
677 case CHIP_CEDAR
: return "AMD CEDAR";
678 case CHIP_REDWOOD
: return "AMD REDWOOD";
679 case CHIP_JUNIPER
: return "AMD JUNIPER";
680 case CHIP_CYPRESS
: return "AMD CYPRESS";
681 case CHIP_HEMLOCK
: return "AMD HEMLOCK";
682 case CHIP_PALM
: return "AMD PALM";
683 case CHIP_SUMO
: return "AMD SUMO";
684 case CHIP_SUMO2
: return "AMD SUMO2";
685 case CHIP_BARTS
: return "AMD BARTS";
686 case CHIP_TURKS
: return "AMD TURKS";
687 case CHIP_CAICOS
: return "AMD CAICOS";
688 case CHIP_CAYMAN
: return "AMD CAYMAN";
689 case CHIP_ARUBA
: return "AMD ARUBA";
690 case CHIP_TAHITI
: return "AMD TAHITI";
691 case CHIP_PITCAIRN
: return "AMD PITCAIRN";
692 case CHIP_VERDE
: return "AMD CAPE VERDE";
693 case CHIP_OLAND
: return "AMD OLAND";
694 case CHIP_HAINAN
: return "AMD HAINAN";
695 case CHIP_BONAIRE
: return "AMD BONAIRE";
696 case CHIP_KAVERI
: return "AMD KAVERI";
697 case CHIP_KABINI
: return "AMD KABINI";
698 case CHIP_HAWAII
: return "AMD HAWAII";
699 case CHIP_MULLINS
: return "AMD MULLINS";
700 case CHIP_TONGA
: return "AMD TONGA";
701 case CHIP_ICELAND
: return "AMD ICELAND";
702 case CHIP_CARRIZO
: return "AMD CARRIZO";
703 case CHIP_FIJI
: return "AMD FIJI";
704 case CHIP_POLARIS10
: return "AMD POLARIS10";
705 case CHIP_POLARIS11
: return "AMD POLARIS11";
706 case CHIP_STONEY
: return "AMD STONEY";
707 default: return "AMD unknown";
711 static const char* r600_get_name(struct pipe_screen
* pscreen
)
713 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
715 return rscreen
->renderer_string
;
718 static float r600_get_paramf(struct pipe_screen
* pscreen
,
719 enum pipe_capf param
)
721 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
724 case PIPE_CAPF_MAX_LINE_WIDTH
:
725 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
726 case PIPE_CAPF_MAX_POINT_WIDTH
:
727 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
728 if (rscreen
->family
>= CHIP_CEDAR
)
732 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
734 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
736 case PIPE_CAPF_GUARD_BAND_LEFT
:
737 case PIPE_CAPF_GUARD_BAND_TOP
:
738 case PIPE_CAPF_GUARD_BAND_RIGHT
:
739 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
745 static int r600_get_video_param(struct pipe_screen
*screen
,
746 enum pipe_video_profile profile
,
747 enum pipe_video_entrypoint entrypoint
,
748 enum pipe_video_cap param
)
751 case PIPE_VIDEO_CAP_SUPPORTED
:
752 return vl_profile_supported(screen
, profile
, entrypoint
);
753 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
755 case PIPE_VIDEO_CAP_MAX_WIDTH
:
756 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
757 return vl_video_buffer_max_size(screen
);
758 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
759 return PIPE_FORMAT_NV12
;
760 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
762 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
764 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
766 case PIPE_VIDEO_CAP_MAX_LEVEL
:
767 return vl_level_supported(screen
, profile
);
773 const char *r600_get_llvm_processor_name(enum radeon_family family
)
816 case CHIP_TAHITI
: return "tahiti";
817 case CHIP_PITCAIRN
: return "pitcairn";
818 case CHIP_VERDE
: return "verde";
819 case CHIP_OLAND
: return "oland";
820 case CHIP_HAINAN
: return "hainan";
821 case CHIP_BONAIRE
: return "bonaire";
822 case CHIP_KABINI
: return "kabini";
823 case CHIP_KAVERI
: return "kaveri";
824 case CHIP_HAWAII
: return "hawaii";
827 case CHIP_TONGA
: return "tonga";
828 case CHIP_ICELAND
: return "iceland";
829 case CHIP_CARRIZO
: return "carrizo";
830 #if HAVE_LLVM <= 0x0307
831 case CHIP_FIJI
: return "tonga";
832 case CHIP_STONEY
: return "carrizo";
834 case CHIP_FIJI
: return "fiji";
835 case CHIP_STONEY
: return "stoney";
837 #if HAVE_LLVM <= 0x0308
838 case CHIP_POLARIS10
: return "tonga";
839 case CHIP_POLARIS11
: return "tonga";
841 case CHIP_POLARIS10
: return "polaris10";
842 case CHIP_POLARIS11
: return "polaris11";
848 static int r600_get_compute_param(struct pipe_screen
*screen
,
849 enum pipe_shader_ir ir_type
,
850 enum pipe_compute_cap param
,
853 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
855 //TODO: select these params by asic
857 case PIPE_COMPUTE_CAP_IR_TARGET
: {
860 if (rscreen
->family
<= CHIP_ARUBA
) {
863 if (HAVE_LLVM
< 0x0400) {
866 triple
= "amdgcn-mesa-mesa3d";
869 switch(rscreen
->family
) {
870 /* Clang < 3.6 is missing Hainan in its list of
871 * GPUs, so we need to use the name of a similar GPU.
874 gpu
= r600_get_llvm_processor_name(rscreen
->family
);
878 sprintf(ret
, "%s-%s", gpu
, triple
);
880 /* +2 for dash and terminating NIL byte */
881 return (strlen(triple
) + strlen(gpu
) + 2) * sizeof(char);
883 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
885 uint64_t *grid_dimension
= ret
;
886 grid_dimension
[0] = 3;
888 return 1 * sizeof(uint64_t);
890 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
892 uint64_t *grid_size
= ret
;
893 grid_size
[0] = 65535;
894 grid_size
[1] = 65535;
895 grid_size
[2] = 65535;
897 return 3 * sizeof(uint64_t) ;
899 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
901 uint64_t *block_size
= ret
;
902 if (rscreen
->chip_class
>= SI
&& HAVE_LLVM
>= 0x309 &&
903 ir_type
== PIPE_SHADER_IR_TGSI
) {
904 block_size
[0] = 2048;
905 block_size
[1] = 2048;
906 block_size
[2] = 2048;
913 return 3 * sizeof(uint64_t);
915 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
917 uint64_t *max_threads_per_block
= ret
;
918 if (rscreen
->chip_class
>= SI
&& HAVE_LLVM
>= 0x309 &&
919 ir_type
== PIPE_SHADER_IR_TGSI
)
920 *max_threads_per_block
= 2048;
922 *max_threads_per_block
= 256;
924 return sizeof(uint64_t);
925 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
927 uint32_t *address_bits
= ret
;
928 address_bits
[0] = 32;
929 if (rscreen
->chip_class
>= SI
)
930 address_bits
[0] = 64;
932 return 1 * sizeof(uint32_t);
934 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
936 uint64_t *max_global_size
= ret
;
937 uint64_t max_mem_alloc_size
;
939 r600_get_compute_param(screen
, ir_type
,
940 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
941 &max_mem_alloc_size
);
943 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
944 * 1/4 of the MAX_GLOBAL_SIZE. Since the
945 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
946 * make sure we never report more than
947 * 4 * MAX_MEM_ALLOC_SIZE.
949 *max_global_size
= MIN2(4 * max_mem_alloc_size
,
950 MAX2(rscreen
->info
.gart_size
,
951 rscreen
->info
.vram_size
));
953 return sizeof(uint64_t);
955 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
957 uint64_t *max_local_size
= ret
;
958 /* Value reported by the closed source driver. */
959 *max_local_size
= 32768;
961 return sizeof(uint64_t);
963 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
965 uint64_t *max_input_size
= ret
;
966 /* Value reported by the closed source driver. */
967 *max_input_size
= 1024;
969 return sizeof(uint64_t);
971 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
973 uint64_t *max_mem_alloc_size
= ret
;
975 *max_mem_alloc_size
= rscreen
->info
.max_alloc_size
;
977 return sizeof(uint64_t);
979 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
981 uint32_t *max_clock_frequency
= ret
;
982 *max_clock_frequency
= rscreen
->info
.max_shader_clock
;
984 return sizeof(uint32_t);
986 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
988 uint32_t *max_compute_units
= ret
;
989 *max_compute_units
= rscreen
->info
.num_good_compute_units
;
991 return sizeof(uint32_t);
993 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
995 uint32_t *images_supported
= ret
;
996 *images_supported
= 0;
998 return sizeof(uint32_t);
999 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
1001 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
1003 uint32_t *subgroup_size
= ret
;
1004 *subgroup_size
= r600_wavefront_size(rscreen
->family
);
1006 return sizeof(uint32_t);
1009 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
1013 static uint64_t r600_get_timestamp(struct pipe_screen
*screen
)
1015 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1017 return 1000000 * rscreen
->ws
->query_value(rscreen
->ws
, RADEON_TIMESTAMP
) /
1018 rscreen
->info
.clock_crystal_freq
;
1021 static void r600_fence_reference(struct pipe_screen
*screen
,
1022 struct pipe_fence_handle
**dst
,
1023 struct pipe_fence_handle
*src
)
1025 struct radeon_winsys
*ws
= ((struct r600_common_screen
*)screen
)->ws
;
1026 struct r600_multi_fence
**rdst
= (struct r600_multi_fence
**)dst
;
1027 struct r600_multi_fence
*rsrc
= (struct r600_multi_fence
*)src
;
1029 if (pipe_reference(&(*rdst
)->reference
, &rsrc
->reference
)) {
1030 ws
->fence_reference(&(*rdst
)->gfx
, NULL
);
1031 ws
->fence_reference(&(*rdst
)->sdma
, NULL
);
1037 static boolean
r600_fence_finish(struct pipe_screen
*screen
,
1038 struct pipe_context
*ctx
,
1039 struct pipe_fence_handle
*fence
,
1042 struct radeon_winsys
*rws
= ((struct r600_common_screen
*)screen
)->ws
;
1043 struct r600_multi_fence
*rfence
= (struct r600_multi_fence
*)fence
;
1044 struct r600_common_context
*rctx
=
1045 ctx
? (struct r600_common_context
*)ctx
: NULL
;
1046 int64_t abs_timeout
= os_time_get_absolute_timeout(timeout
);
1049 if (!rws
->fence_wait(rws
, rfence
->sdma
, timeout
))
1052 /* Recompute the timeout after waiting. */
1053 if (timeout
&& timeout
!= PIPE_TIMEOUT_INFINITE
) {
1054 int64_t time
= os_time_get_nano();
1055 timeout
= abs_timeout
> time
? abs_timeout
- time
: 0;
1062 /* Flush the gfx IB if it hasn't been flushed yet. */
1064 rfence
->gfx_unflushed
.ctx
== rctx
&&
1065 rfence
->gfx_unflushed
.ib_index
== rctx
->num_gfx_cs_flushes
) {
1066 rctx
->gfx
.flush(rctx
, timeout
? 0 : RADEON_FLUSH_ASYNC
, NULL
);
1067 rfence
->gfx_unflushed
.ctx
= NULL
;
1072 /* Recompute the timeout after all that. */
1073 if (timeout
&& timeout
!= PIPE_TIMEOUT_INFINITE
) {
1074 int64_t time
= os_time_get_nano();
1075 timeout
= abs_timeout
> time
? abs_timeout
- time
: 0;
1079 return rws
->fence_wait(rws
, rfence
->gfx
, timeout
);
1082 static void r600_query_memory_info(struct pipe_screen
*screen
,
1083 struct pipe_memory_info
*info
)
1085 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1086 struct radeon_winsys
*ws
= rscreen
->ws
;
1087 unsigned vram_usage
, gtt_usage
;
1089 info
->total_device_memory
= rscreen
->info
.vram_size
/ 1024;
1090 info
->total_staging_memory
= rscreen
->info
.gart_size
/ 1024;
1092 /* The real TTM memory usage is somewhat random, because:
1094 * 1) TTM delays freeing memory, because it can only free it after
1097 * 2) The memory usage can be really low if big VRAM evictions are
1098 * taking place, but the real usage is well above the size of VRAM.
1100 * Instead, return statistics of this process.
1102 vram_usage
= ws
->query_value(ws
, RADEON_REQUESTED_VRAM_MEMORY
) / 1024;
1103 gtt_usage
= ws
->query_value(ws
, RADEON_REQUESTED_GTT_MEMORY
) / 1024;
1105 info
->avail_device_memory
=
1106 vram_usage
<= info
->total_device_memory
?
1107 info
->total_device_memory
- vram_usage
: 0;
1108 info
->avail_staging_memory
=
1109 gtt_usage
<= info
->total_staging_memory
?
1110 info
->total_staging_memory
- gtt_usage
: 0;
1112 info
->device_memory_evicted
=
1113 ws
->query_value(ws
, RADEON_NUM_BYTES_MOVED
) / 1024;
1115 if (rscreen
->info
.drm_major
== 3 && rscreen
->info
.drm_minor
>= 4)
1116 info
->nr_device_memory_evictions
=
1117 ws
->query_value(ws
, RADEON_NUM_EVICTIONS
);
1119 /* Just return the number of evicted 64KB pages. */
1120 info
->nr_device_memory_evictions
= info
->device_memory_evicted
/ 64;
1123 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
1124 const struct pipe_resource
*templ
)
1126 if (templ
->target
== PIPE_BUFFER
) {
1127 return r600_buffer_create(screen
, templ
, 256);
1129 return r600_texture_create(screen
, templ
);
1133 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
1134 struct radeon_winsys
*ws
)
1136 char llvm_string
[32] = {}, kernel_version
[128] = {};
1137 struct utsname uname_data
;
1139 ws
->query_info(ws
, &rscreen
->info
);
1141 if (uname(&uname_data
) == 0)
1142 snprintf(kernel_version
, sizeof(kernel_version
),
1143 " / %s", uname_data
.release
);
1146 snprintf(llvm_string
, sizeof(llvm_string
),
1147 ", LLVM %i.%i.%i", (HAVE_LLVM
>> 8) & 0xff,
1148 HAVE_LLVM
& 0xff, MESA_LLVM_VERSION_PATCH
);
1151 snprintf(rscreen
->renderer_string
, sizeof(rscreen
->renderer_string
),
1152 "%s (DRM %i.%i.%i%s%s)",
1153 r600_get_chip_name(rscreen
), rscreen
->info
.drm_major
,
1154 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
,
1155 kernel_version
, llvm_string
);
1157 rscreen
->b
.get_name
= r600_get_name
;
1158 rscreen
->b
.get_vendor
= r600_get_vendor
;
1159 rscreen
->b
.get_device_vendor
= r600_get_device_vendor
;
1160 rscreen
->b
.get_compute_param
= r600_get_compute_param
;
1161 rscreen
->b
.get_paramf
= r600_get_paramf
;
1162 rscreen
->b
.get_timestamp
= r600_get_timestamp
;
1163 rscreen
->b
.fence_finish
= r600_fence_finish
;
1164 rscreen
->b
.fence_reference
= r600_fence_reference
;
1165 rscreen
->b
.resource_destroy
= u_resource_destroy_vtbl
;
1166 rscreen
->b
.resource_from_user_memory
= r600_buffer_from_user_memory
;
1167 rscreen
->b
.query_memory_info
= r600_query_memory_info
;
1169 if (rscreen
->info
.has_uvd
) {
1170 rscreen
->b
.get_video_param
= rvid_get_video_param
;
1171 rscreen
->b
.is_video_format_supported
= rvid_is_format_supported
;
1173 rscreen
->b
.get_video_param
= r600_get_video_param
;
1174 rscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
1177 r600_init_screen_texture_functions(rscreen
);
1178 r600_init_screen_query_functions(rscreen
);
1181 rscreen
->family
= rscreen
->info
.family
;
1182 rscreen
->chip_class
= rscreen
->info
.chip_class
;
1183 rscreen
->debug_flags
= debug_get_flags_option("R600_DEBUG", common_debug_options
, 0);
1185 slab_create_parent(&rscreen
->pool_transfers
, sizeof(struct r600_transfer
), 64);
1187 rscreen
->force_aniso
= MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1188 if (rscreen
->force_aniso
>= 0) {
1189 printf("radeon: Forcing anisotropy filter to %ix\n",
1190 /* round down to a power of two */
1191 1 << util_logbase2(rscreen
->force_aniso
));
1194 util_format_s3tc_init();
1195 pipe_mutex_init(rscreen
->aux_context_lock
);
1196 pipe_mutex_init(rscreen
->gpu_load_mutex
);
1198 if (rscreen
->debug_flags
& DBG_INFO
) {
1199 printf("pci_id = 0x%x\n", rscreen
->info
.pci_id
);
1200 printf("family = %i (%s)\n", rscreen
->info
.family
,
1201 r600_get_chip_name(rscreen
));
1202 printf("chip_class = %i\n", rscreen
->info
.chip_class
);
1203 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen
->info
.gart_size
, 1024*1024));
1204 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen
->info
.vram_size
, 1024*1024));
1205 printf("max_alloc_size = %i MB\n",
1206 (int)DIV_ROUND_UP(rscreen
->info
.max_alloc_size
, 1024*1024));
1207 printf("has_virtual_memory = %i\n", rscreen
->info
.has_virtual_memory
);
1208 printf("gfx_ib_pad_with_type2 = %i\n", rscreen
->info
.gfx_ib_pad_with_type2
);
1209 printf("has_sdma = %i\n", rscreen
->info
.has_sdma
);
1210 printf("has_uvd = %i\n", rscreen
->info
.has_uvd
);
1211 printf("me_fw_version = %i\n", rscreen
->info
.me_fw_version
);
1212 printf("pfp_fw_version = %i\n", rscreen
->info
.pfp_fw_version
);
1213 printf("ce_fw_version = %i\n", rscreen
->info
.ce_fw_version
);
1214 printf("vce_fw_version = %i\n", rscreen
->info
.vce_fw_version
);
1215 printf("vce_harvest_config = %i\n", rscreen
->info
.vce_harvest_config
);
1216 printf("clock_crystal_freq = %i\n", rscreen
->info
.clock_crystal_freq
);
1217 printf("drm = %i.%i.%i\n", rscreen
->info
.drm_major
,
1218 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
);
1219 printf("has_userptr = %i\n", rscreen
->info
.has_userptr
);
1221 printf("r600_max_quad_pipes = %i\n", rscreen
->info
.r600_max_quad_pipes
);
1222 printf("max_shader_clock = %i\n", rscreen
->info
.max_shader_clock
);
1223 printf("num_good_compute_units = %i\n", rscreen
->info
.num_good_compute_units
);
1224 printf("max_se = %i\n", rscreen
->info
.max_se
);
1225 printf("max_sh_per_se = %i\n", rscreen
->info
.max_sh_per_se
);
1227 printf("r600_gb_backend_map = %i\n", rscreen
->info
.r600_gb_backend_map
);
1228 printf("r600_gb_backend_map_valid = %i\n", rscreen
->info
.r600_gb_backend_map_valid
);
1229 printf("r600_num_banks = %i\n", rscreen
->info
.r600_num_banks
);
1230 printf("num_render_backends = %i\n", rscreen
->info
.num_render_backends
);
1231 printf("num_tile_pipes = %i\n", rscreen
->info
.num_tile_pipes
);
1232 printf("pipe_interleave_bytes = %i\n", rscreen
->info
.pipe_interleave_bytes
);
1237 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
)
1239 r600_perfcounters_destroy(rscreen
);
1240 r600_gpu_load_kill_thread(rscreen
);
1242 pipe_mutex_destroy(rscreen
->gpu_load_mutex
);
1243 pipe_mutex_destroy(rscreen
->aux_context_lock
);
1244 rscreen
->aux_context
->destroy(rscreen
->aux_context
);
1246 slab_destroy_parent(&rscreen
->pool_transfers
);
1248 rscreen
->ws
->destroy(rscreen
->ws
);
1252 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
1255 switch (processor
) {
1256 case PIPE_SHADER_VERTEX
:
1257 return (rscreen
->debug_flags
& DBG_VS
) != 0;
1258 case PIPE_SHADER_TESS_CTRL
:
1259 return (rscreen
->debug_flags
& DBG_TCS
) != 0;
1260 case PIPE_SHADER_TESS_EVAL
:
1261 return (rscreen
->debug_flags
& DBG_TES
) != 0;
1262 case PIPE_SHADER_GEOMETRY
:
1263 return (rscreen
->debug_flags
& DBG_GS
) != 0;
1264 case PIPE_SHADER_FRAGMENT
:
1265 return (rscreen
->debug_flags
& DBG_PS
) != 0;
1266 case PIPE_SHADER_COMPUTE
:
1267 return (rscreen
->debug_flags
& DBG_CS
) != 0;
1273 bool r600_extra_shader_checks(struct r600_common_screen
*rscreen
, unsigned processor
)
1275 return (rscreen
->debug_flags
& DBG_CHECK_IR
) ||
1276 r600_can_dump_shader(rscreen
, processor
);
1279 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
1280 uint64_t offset
, uint64_t size
, unsigned value
,
1281 enum r600_coherency coher
)
1283 struct r600_common_context
*rctx
= (struct r600_common_context
*)rscreen
->aux_context
;
1285 pipe_mutex_lock(rscreen
->aux_context_lock
);
1286 rctx
->clear_buffer(&rctx
->b
, dst
, offset
, size
, value
, coher
);
1287 rscreen
->aux_context
->flush(rscreen
->aux_context
, NULL
, 0);
1288 pipe_mutex_unlock(rscreen
->aux_context_lock
);