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radeonsi/gfx9: EVENT_WRITE_EOP -> RELEASE_MEM
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 #if HAVE_LLVM
47 #include <llvm-c/TargetMachine.h>
48 #endif
49
50 #ifndef MESA_LLVM_VERSION_PATCH
51 #define MESA_LLVM_VERSION_PATCH 0
52 #endif
53
54 struct r600_multi_fence {
55 struct pipe_reference reference;
56 struct pipe_fence_handle *gfx;
57 struct pipe_fence_handle *sdma;
58
59 /* If the context wasn't flushed at fence creation, this is non-NULL. */
60 struct {
61 struct r600_common_context *ctx;
62 unsigned ib_index;
63 } gfx_unflushed;
64 };
65
66 /*
67 * shader binary helpers.
68 */
69 void radeon_shader_binary_init(struct ac_shader_binary *b)
70 {
71 memset(b, 0, sizeof(*b));
72 }
73
74 void radeon_shader_binary_clean(struct ac_shader_binary *b)
75 {
76 if (!b)
77 return;
78 FREE(b->code);
79 FREE(b->config);
80 FREE(b->rodata);
81 FREE(b->global_symbol_offsets);
82 FREE(b->relocs);
83 FREE(b->disasm_string);
84 FREE(b->llvm_ir_string);
85 }
86
87 /*
88 * pipe_context
89 */
90
91 /**
92 * Write an EOP event.
93 *
94 * \param event EVENT_TYPE_*
95 * \param event_flags Optional cache flush flags (TC)
96 * \param data_sel 1 = fence, 3 = timestamp
97 * \param buf Buffer
98 * \param va GPU address
99 * \param old_value Previous fence value (for a bug workaround)
100 * \param new_value Fence value to write for this event.
101 */
102 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
103 unsigned event, unsigned event_flags,
104 unsigned data_sel,
105 struct r600_resource *buf, uint64_t va,
106 uint32_t old_fence, uint32_t new_fence)
107 {
108 struct radeon_winsys_cs *cs = ctx->gfx.cs;
109 unsigned op = EVENT_TYPE(event) |
110 EVENT_INDEX(5) |
111 event_flags;
112
113 if (ctx->chip_class >= GFX9) {
114 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 6, 0));
115 radeon_emit(cs, op);
116 radeon_emit(cs, EOP_DATA_SEL(data_sel));
117 radeon_emit(cs, va); /* address lo */
118 radeon_emit(cs, va >> 32); /* address hi */
119 radeon_emit(cs, new_fence); /* immediate data lo */
120 radeon_emit(cs, 0); /* immediate data hi */
121 radeon_emit(cs, 0); /* unused */
122 } else {
123 if (ctx->chip_class == CIK ||
124 ctx->chip_class == VI) {
125 /* Two EOP events are required to make all engines go idle
126 * (and optional cache flushes executed) before the timestamp
127 * is written.
128 */
129 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
130 radeon_emit(cs, op);
131 radeon_emit(cs, va);
132 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
133 radeon_emit(cs, old_fence); /* immediate data */
134 radeon_emit(cs, 0); /* unused */
135 }
136
137 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
138 radeon_emit(cs, op);
139 radeon_emit(cs, va);
140 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
141 radeon_emit(cs, new_fence); /* immediate data */
142 radeon_emit(cs, 0); /* unused */
143 }
144
145 if (buf)
146 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
147 RADEON_PRIO_QUERY);
148 }
149
150 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
151 {
152 unsigned dwords = 6;
153
154 if (screen->chip_class == CIK ||
155 screen->chip_class == VI)
156 dwords *= 2;
157
158 if (!screen->info.has_virtual_memory)
159 dwords += 2;
160
161 return dwords;
162 }
163
164 void r600_gfx_wait_fence(struct r600_common_context *ctx,
165 uint64_t va, uint32_t ref, uint32_t mask)
166 {
167 struct radeon_winsys_cs *cs = ctx->gfx.cs;
168
169 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
170 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
171 radeon_emit(cs, va);
172 radeon_emit(cs, va >> 32);
173 radeon_emit(cs, ref); /* reference value */
174 radeon_emit(cs, mask); /* mask */
175 radeon_emit(cs, 4); /* poll interval */
176 }
177
178 void r600_draw_rectangle(struct blitter_context *blitter,
179 int x1, int y1, int x2, int y2, float depth,
180 enum blitter_attrib_type type,
181 const union pipe_color_union *attrib)
182 {
183 struct r600_common_context *rctx =
184 (struct r600_common_context*)util_blitter_get_pipe(blitter);
185 struct pipe_viewport_state viewport;
186 struct pipe_resource *buf = NULL;
187 unsigned offset = 0;
188 float *vb;
189
190 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
191 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
192 return;
193 }
194
195 /* Some operations (like color resolve on r6xx) don't work
196 * with the conventional primitive types.
197 * One that works is PT_RECTLIST, which we use here. */
198
199 /* setup viewport */
200 viewport.scale[0] = 1.0f;
201 viewport.scale[1] = 1.0f;
202 viewport.scale[2] = 1.0f;
203 viewport.translate[0] = 0.0f;
204 viewport.translate[1] = 0.0f;
205 viewport.translate[2] = 0.0f;
206 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
207
208 /* Upload vertices. The hw rectangle has only 3 vertices,
209 * I guess the 4th one is derived from the first 3.
210 * The vertex specification should match u_blitter's vertex element state. */
211 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
212 rctx->screen->info.tcc_cache_line_size,
213 &offset, &buf, (void**)&vb);
214 if (!buf)
215 return;
216
217 vb[0] = x1;
218 vb[1] = y1;
219 vb[2] = depth;
220 vb[3] = 1;
221
222 vb[8] = x1;
223 vb[9] = y2;
224 vb[10] = depth;
225 vb[11] = 1;
226
227 vb[16] = x2;
228 vb[17] = y1;
229 vb[18] = depth;
230 vb[19] = 1;
231
232 if (attrib) {
233 memcpy(vb+4, attrib->f, sizeof(float)*4);
234 memcpy(vb+12, attrib->f, sizeof(float)*4);
235 memcpy(vb+20, attrib->f, sizeof(float)*4);
236 }
237
238 /* draw */
239 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
240 R600_PRIM_RECTANGLE_LIST, 3, 2);
241 pipe_resource_reference(&buf, NULL);
242 }
243
244 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
245 {
246 struct radeon_winsys_cs *cs = rctx->dma.cs;
247
248 /* NOP waits for idle on Evergreen and later. */
249 if (rctx->chip_class >= CIK)
250 radeon_emit(cs, 0x00000000); /* NOP */
251 else if (rctx->chip_class >= EVERGREEN)
252 radeon_emit(cs, 0xf0000000); /* NOP */
253 else {
254 /* TODO: R600-R700 should use the FENCE packet.
255 * CS checker support is required. */
256 }
257 }
258
259 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
260 struct r600_resource *dst, struct r600_resource *src)
261 {
262 uint64_t vram = ctx->dma.cs->used_vram;
263 uint64_t gtt = ctx->dma.cs->used_gart;
264
265 if (dst) {
266 vram += dst->vram_usage;
267 gtt += dst->gart_usage;
268 }
269 if (src) {
270 vram += src->vram_usage;
271 gtt += src->gart_usage;
272 }
273
274 /* Flush the GFX IB if DMA depends on it. */
275 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
276 ((dst &&
277 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
278 RADEON_USAGE_READWRITE)) ||
279 (src &&
280 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
281 RADEON_USAGE_WRITE))))
282 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
283
284 /* Flush if there's not enough space, or if the memory usage per IB
285 * is too large.
286 *
287 * IBs using too little memory are limited by the IB submission overhead.
288 * IBs using too much memory are limited by the kernel/TTM overhead.
289 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
290 *
291 * This heuristic makes sure that DMA requests are executed
292 * very soon after the call is made and lowers memory usage.
293 * It improves texture upload performance by keeping the DMA
294 * engine busy while uploads are being submitted.
295 */
296 num_dw++; /* for emit_wait_idle below */
297 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
298 ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 ||
299 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
300 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
301 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
302 }
303
304 /* Wait for idle if either buffer has been used in the IB before to
305 * prevent read-after-write hazards.
306 */
307 if ((dst &&
308 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, dst->buf,
309 RADEON_USAGE_READWRITE)) ||
310 (src &&
311 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, src->buf,
312 RADEON_USAGE_WRITE)))
313 r600_dma_emit_wait_idle(ctx);
314
315 /* If GPUVM is not supported, the CS checker needs 2 entries
316 * in the buffer list per packet, which has to be done manually.
317 */
318 if (ctx->screen->info.has_virtual_memory) {
319 if (dst)
320 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
321 RADEON_USAGE_WRITE,
322 RADEON_PRIO_SDMA_BUFFER);
323 if (src)
324 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
325 RADEON_USAGE_READ,
326 RADEON_PRIO_SDMA_BUFFER);
327 }
328
329 /* this function is called before all DMA calls, so increment this. */
330 ctx->num_dma_calls++;
331 }
332
333 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
334 {
335 }
336
337 void r600_preflush_suspend_features(struct r600_common_context *ctx)
338 {
339 /* suspend queries */
340 if (!LIST_IS_EMPTY(&ctx->active_queries))
341 r600_suspend_queries(ctx);
342
343 ctx->streamout.suspended = false;
344 if (ctx->streamout.begin_emitted) {
345 r600_emit_streamout_end(ctx);
346 ctx->streamout.suspended = true;
347 }
348 }
349
350 void r600_postflush_resume_features(struct r600_common_context *ctx)
351 {
352 if (ctx->streamout.suspended) {
353 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
354 r600_streamout_buffers_dirty(ctx);
355 }
356
357 /* resume queries */
358 if (!LIST_IS_EMPTY(&ctx->active_queries))
359 r600_resume_queries(ctx);
360 }
361
362 static void r600_flush_from_st(struct pipe_context *ctx,
363 struct pipe_fence_handle **fence,
364 unsigned flags)
365 {
366 struct pipe_screen *screen = ctx->screen;
367 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
368 struct radeon_winsys *ws = rctx->ws;
369 unsigned rflags = 0;
370 struct pipe_fence_handle *gfx_fence = NULL;
371 struct pipe_fence_handle *sdma_fence = NULL;
372 bool deferred_fence = false;
373
374 if (flags & PIPE_FLUSH_END_OF_FRAME)
375 rflags |= RADEON_FLUSH_END_OF_FRAME;
376 if (flags & PIPE_FLUSH_DEFERRED)
377 rflags |= RADEON_FLUSH_ASYNC;
378
379 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
380 if (rctx->dma.cs)
381 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
382
383 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
384 if (fence)
385 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
386 if (!(rflags & RADEON_FLUSH_ASYNC))
387 ws->cs_sync_flush(rctx->gfx.cs);
388 } else {
389 /* Instead of flushing, create a deferred fence. Constraints:
390 * - The state tracker must allow a deferred flush.
391 * - The state tracker must request a fence.
392 * Thread safety in fence_finish must be ensured by the state tracker.
393 */
394 if (flags & PIPE_FLUSH_DEFERRED && fence) {
395 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
396 deferred_fence = true;
397 } else {
398 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
399 }
400 }
401
402 /* Both engines can signal out of order, so we need to keep both fences. */
403 if (fence) {
404 struct r600_multi_fence *multi_fence =
405 CALLOC_STRUCT(r600_multi_fence);
406 if (!multi_fence)
407 return;
408
409 multi_fence->reference.count = 1;
410 /* If both fences are NULL, fence_finish will always return true. */
411 multi_fence->gfx = gfx_fence;
412 multi_fence->sdma = sdma_fence;
413
414 if (deferred_fence) {
415 multi_fence->gfx_unflushed.ctx = rctx;
416 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
417 }
418
419 screen->fence_reference(screen, fence, NULL);
420 *fence = (struct pipe_fence_handle*)multi_fence;
421 }
422 }
423
424 static void r600_flush_dma_ring(void *ctx, unsigned flags,
425 struct pipe_fence_handle **fence)
426 {
427 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
428 struct radeon_winsys_cs *cs = rctx->dma.cs;
429 struct radeon_saved_cs saved;
430 bool check_vm =
431 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
432 rctx->check_vm_faults;
433
434 if (!radeon_emitted(cs, 0)) {
435 if (fence)
436 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
437 return;
438 }
439
440 if (check_vm)
441 radeon_save_cs(rctx->ws, cs, &saved);
442
443 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
444 if (fence)
445 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
446
447 if (check_vm) {
448 /* Use conservative timeout 800ms, after which we won't wait any
449 * longer and assume the GPU is hung.
450 */
451 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
452
453 rctx->check_vm_faults(rctx, &saved, RING_DMA);
454 radeon_clear_saved_cs(&saved);
455 }
456 }
457
458 /**
459 * Store a linearized copy of all chunks of \p cs together with the buffer
460 * list in \p saved.
461 */
462 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
463 struct radeon_saved_cs *saved)
464 {
465 void *buf;
466 unsigned i;
467
468 /* Save the IB chunks. */
469 saved->num_dw = cs->prev_dw + cs->current.cdw;
470 saved->ib = MALLOC(4 * saved->num_dw);
471 if (!saved->ib)
472 goto oom;
473
474 buf = saved->ib;
475 for (i = 0; i < cs->num_prev; ++i) {
476 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
477 buf += cs->prev[i].cdw;
478 }
479 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
480
481 /* Save the buffer list. */
482 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
483 saved->bo_list = CALLOC(saved->bo_count,
484 sizeof(saved->bo_list[0]));
485 if (!saved->bo_list) {
486 FREE(saved->ib);
487 goto oom;
488 }
489 ws->cs_get_buffer_list(cs, saved->bo_list);
490
491 return;
492
493 oom:
494 fprintf(stderr, "%s: out of memory\n", __func__);
495 memset(saved, 0, sizeof(*saved));
496 }
497
498 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
499 {
500 FREE(saved->ib);
501 FREE(saved->bo_list);
502
503 memset(saved, 0, sizeof(*saved));
504 }
505
506 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
507 {
508 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
509 unsigned latest = rctx->ws->query_value(rctx->ws,
510 RADEON_GPU_RESET_COUNTER);
511
512 if (rctx->gpu_reset_counter == latest)
513 return PIPE_NO_RESET;
514
515 rctx->gpu_reset_counter = latest;
516 return PIPE_UNKNOWN_CONTEXT_RESET;
517 }
518
519 static void r600_set_debug_callback(struct pipe_context *ctx,
520 const struct pipe_debug_callback *cb)
521 {
522 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
523
524 if (cb)
525 rctx->debug = *cb;
526 else
527 memset(&rctx->debug, 0, sizeof(rctx->debug));
528 }
529
530 static void r600_set_device_reset_callback(struct pipe_context *ctx,
531 const struct pipe_device_reset_callback *cb)
532 {
533 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
534
535 if (cb)
536 rctx->device_reset_callback = *cb;
537 else
538 memset(&rctx->device_reset_callback, 0,
539 sizeof(rctx->device_reset_callback));
540 }
541
542 bool r600_check_device_reset(struct r600_common_context *rctx)
543 {
544 enum pipe_reset_status status;
545
546 if (!rctx->device_reset_callback.reset)
547 return false;
548
549 if (!rctx->b.get_device_reset_status)
550 return false;
551
552 status = rctx->b.get_device_reset_status(&rctx->b);
553 if (status == PIPE_NO_RESET)
554 return false;
555
556 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
557 return true;
558 }
559
560 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
561 struct pipe_resource *dst,
562 uint64_t offset, uint64_t size,
563 unsigned value)
564 {
565 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
566
567 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
568 }
569
570 bool r600_common_context_init(struct r600_common_context *rctx,
571 struct r600_common_screen *rscreen,
572 unsigned context_flags)
573 {
574 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
575
576 rctx->screen = rscreen;
577 rctx->ws = rscreen->ws;
578 rctx->family = rscreen->family;
579 rctx->chip_class = rscreen->chip_class;
580
581 rctx->b.invalidate_resource = r600_invalidate_resource;
582 rctx->b.transfer_map = u_transfer_map_vtbl;
583 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
584 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
585 rctx->b.texture_subdata = u_default_texture_subdata;
586 rctx->b.memory_barrier = r600_memory_barrier;
587 rctx->b.flush = r600_flush_from_st;
588 rctx->b.set_debug_callback = r600_set_debug_callback;
589 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
590
591 /* evergreen_compute.c has a special codepath for global buffers.
592 * Everything else can use the direct path.
593 */
594 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
595 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
596 rctx->b.buffer_subdata = u_default_buffer_subdata;
597 else
598 rctx->b.buffer_subdata = r600_buffer_subdata;
599
600 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
601 rctx->b.get_device_reset_status = r600_get_reset_status;
602 rctx->gpu_reset_counter =
603 rctx->ws->query_value(rctx->ws,
604 RADEON_GPU_RESET_COUNTER);
605 }
606
607 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
608
609 r600_init_context_texture_functions(rctx);
610 r600_init_viewport_functions(rctx);
611 r600_streamout_init(rctx);
612 r600_query_init(rctx);
613 cayman_init_msaa(&rctx->b);
614
615 rctx->allocator_zeroed_memory =
616 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
617 0, PIPE_USAGE_DEFAULT, 0, true);
618 if (!rctx->allocator_zeroed_memory)
619 return false;
620
621 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
622 0, PIPE_USAGE_STREAM);
623 if (!rctx->b.stream_uploader)
624 return false;
625
626 rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024,
627 0, PIPE_USAGE_DEFAULT);
628 if (!rctx->b.const_uploader)
629 return false;
630
631 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
632 if (!rctx->ctx)
633 return false;
634
635 if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
636 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
637 r600_flush_dma_ring,
638 rctx);
639 rctx->dma.flush = r600_flush_dma_ring;
640 }
641
642 return true;
643 }
644
645 void r600_common_context_cleanup(struct r600_common_context *rctx)
646 {
647 unsigned i,j;
648
649 /* Release DCC stats. */
650 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
651 assert(!rctx->dcc_stats[i].query_active);
652
653 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
654 if (rctx->dcc_stats[i].ps_stats[j])
655 rctx->b.destroy_query(&rctx->b,
656 rctx->dcc_stats[i].ps_stats[j]);
657
658 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
659 }
660
661 if (rctx->query_result_shader)
662 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
663
664 if (rctx->gfx.cs)
665 rctx->ws->cs_destroy(rctx->gfx.cs);
666 if (rctx->dma.cs)
667 rctx->ws->cs_destroy(rctx->dma.cs);
668 if (rctx->ctx)
669 rctx->ws->ctx_destroy(rctx->ctx);
670
671 if (rctx->b.stream_uploader)
672 u_upload_destroy(rctx->b.stream_uploader);
673 if (rctx->b.const_uploader)
674 u_upload_destroy(rctx->b.const_uploader);
675
676 slab_destroy_child(&rctx->pool_transfers);
677
678 if (rctx->allocator_zeroed_memory) {
679 u_suballocator_destroy(rctx->allocator_zeroed_memory);
680 }
681 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
682 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
683 }
684
685 /*
686 * pipe_screen
687 */
688
689 static const struct debug_named_value common_debug_options[] = {
690 /* logging */
691 { "tex", DBG_TEX, "Print texture info" },
692 { "compute", DBG_COMPUTE, "Print compute info" },
693 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
694 { "info", DBG_INFO, "Print driver information" },
695
696 /* shaders */
697 { "fs", DBG_FS, "Print fetch shaders" },
698 { "vs", DBG_VS, "Print vertex shaders" },
699 { "gs", DBG_GS, "Print geometry shaders" },
700 { "ps", DBG_PS, "Print pixel shaders" },
701 { "cs", DBG_CS, "Print compute shaders" },
702 { "tcs", DBG_TCS, "Print tessellation control shaders" },
703 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
704 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
705 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
706 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
707 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
708 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
709 { "nooptvariant", DBG_NO_OPT_VARIANT, "Disable compiling optimized shader variants." },
710
711 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
712
713 /* features */
714 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
715 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
716 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
717 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
718 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
719 { "notiling", DBG_NO_TILING, "Disable tiling" },
720 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
721 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
722 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
723 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
724 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
725 { "nodcc", DBG_NO_DCC, "Disable DCC." },
726 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
727 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
728 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
729 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
730 { "noce", DBG_NO_CE, "Disable the constant engine"},
731 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
732 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
733
734 DEBUG_NAMED_VALUE_END /* must be last */
735 };
736
737 static const char* r600_get_vendor(struct pipe_screen* pscreen)
738 {
739 return "X.Org";
740 }
741
742 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
743 {
744 return "AMD";
745 }
746
747 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
748 {
749 switch (rscreen->info.family) {
750 case CHIP_R600: return "AMD R600";
751 case CHIP_RV610: return "AMD RV610";
752 case CHIP_RV630: return "AMD RV630";
753 case CHIP_RV670: return "AMD RV670";
754 case CHIP_RV620: return "AMD RV620";
755 case CHIP_RV635: return "AMD RV635";
756 case CHIP_RS780: return "AMD RS780";
757 case CHIP_RS880: return "AMD RS880";
758 case CHIP_RV770: return "AMD RV770";
759 case CHIP_RV730: return "AMD RV730";
760 case CHIP_RV710: return "AMD RV710";
761 case CHIP_RV740: return "AMD RV740";
762 case CHIP_CEDAR: return "AMD CEDAR";
763 case CHIP_REDWOOD: return "AMD REDWOOD";
764 case CHIP_JUNIPER: return "AMD JUNIPER";
765 case CHIP_CYPRESS: return "AMD CYPRESS";
766 case CHIP_HEMLOCK: return "AMD HEMLOCK";
767 case CHIP_PALM: return "AMD PALM";
768 case CHIP_SUMO: return "AMD SUMO";
769 case CHIP_SUMO2: return "AMD SUMO2";
770 case CHIP_BARTS: return "AMD BARTS";
771 case CHIP_TURKS: return "AMD TURKS";
772 case CHIP_CAICOS: return "AMD CAICOS";
773 case CHIP_CAYMAN: return "AMD CAYMAN";
774 case CHIP_ARUBA: return "AMD ARUBA";
775 case CHIP_TAHITI: return "AMD TAHITI";
776 case CHIP_PITCAIRN: return "AMD PITCAIRN";
777 case CHIP_VERDE: return "AMD CAPE VERDE";
778 case CHIP_OLAND: return "AMD OLAND";
779 case CHIP_HAINAN: return "AMD HAINAN";
780 case CHIP_BONAIRE: return "AMD BONAIRE";
781 case CHIP_KAVERI: return "AMD KAVERI";
782 case CHIP_KABINI: return "AMD KABINI";
783 case CHIP_HAWAII: return "AMD HAWAII";
784 case CHIP_MULLINS: return "AMD MULLINS";
785 case CHIP_TONGA: return "AMD TONGA";
786 case CHIP_ICELAND: return "AMD ICELAND";
787 case CHIP_CARRIZO: return "AMD CARRIZO";
788 case CHIP_FIJI: return "AMD FIJI";
789 case CHIP_POLARIS10: return "AMD POLARIS10";
790 case CHIP_POLARIS11: return "AMD POLARIS11";
791 case CHIP_POLARIS12: return "AMD POLARIS12";
792 case CHIP_STONEY: return "AMD STONEY";
793 case CHIP_VEGA10: return "AMD VEGA10";
794 default: return "AMD unknown";
795 }
796 }
797
798 static void r600_disk_cache_create(struct r600_common_screen *rscreen)
799 {
800 /* Don't use the cache if shader dumping is enabled. */
801 if (rscreen->debug_flags &
802 (DBG_FS | DBG_VS | DBG_TCS | DBG_TES | DBG_GS | DBG_PS | DBG_CS))
803 return;
804
805 uint32_t mesa_timestamp;
806 if (disk_cache_get_function_timestamp(r600_disk_cache_create,
807 &mesa_timestamp)) {
808 char *timestamp_str;
809 int res = -1;
810 if (rscreen->chip_class < SI) {
811 res = asprintf(&timestamp_str, "%u",mesa_timestamp);
812 }
813 #if HAVE_LLVM
814 else {
815 uint32_t llvm_timestamp;
816 if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
817 &llvm_timestamp)) {
818 res = asprintf(&timestamp_str, "%u_%u",
819 mesa_timestamp, llvm_timestamp);
820 }
821 }
822 #endif
823 if (res != -1) {
824 rscreen->disk_shader_cache =
825 disk_cache_create(r600_get_chip_name(rscreen),
826 timestamp_str);
827 free(timestamp_str);
828 }
829 }
830 }
831
832 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
833 {
834 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
835 return rscreen->disk_shader_cache;
836 }
837
838 static const char* r600_get_name(struct pipe_screen* pscreen)
839 {
840 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
841
842 return rscreen->renderer_string;
843 }
844
845 static float r600_get_paramf(struct pipe_screen* pscreen,
846 enum pipe_capf param)
847 {
848 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
849
850 switch (param) {
851 case PIPE_CAPF_MAX_LINE_WIDTH:
852 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
853 case PIPE_CAPF_MAX_POINT_WIDTH:
854 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
855 if (rscreen->family >= CHIP_CEDAR)
856 return 16384.0f;
857 else
858 return 8192.0f;
859 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
860 return 16.0f;
861 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
862 return 16.0f;
863 case PIPE_CAPF_GUARD_BAND_LEFT:
864 case PIPE_CAPF_GUARD_BAND_TOP:
865 case PIPE_CAPF_GUARD_BAND_RIGHT:
866 case PIPE_CAPF_GUARD_BAND_BOTTOM:
867 return 0.0f;
868 }
869 return 0.0f;
870 }
871
872 static int r600_get_video_param(struct pipe_screen *screen,
873 enum pipe_video_profile profile,
874 enum pipe_video_entrypoint entrypoint,
875 enum pipe_video_cap param)
876 {
877 switch (param) {
878 case PIPE_VIDEO_CAP_SUPPORTED:
879 return vl_profile_supported(screen, profile, entrypoint);
880 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
881 return 1;
882 case PIPE_VIDEO_CAP_MAX_WIDTH:
883 case PIPE_VIDEO_CAP_MAX_HEIGHT:
884 return vl_video_buffer_max_size(screen);
885 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
886 return PIPE_FORMAT_NV12;
887 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
888 return false;
889 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
890 return false;
891 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
892 return true;
893 case PIPE_VIDEO_CAP_MAX_LEVEL:
894 return vl_level_supported(screen, profile);
895 default:
896 return 0;
897 }
898 }
899
900 const char *r600_get_llvm_processor_name(enum radeon_family family)
901 {
902 switch (family) {
903 case CHIP_R600:
904 case CHIP_RV630:
905 case CHIP_RV635:
906 case CHIP_RV670:
907 return "r600";
908 case CHIP_RV610:
909 case CHIP_RV620:
910 case CHIP_RS780:
911 case CHIP_RS880:
912 return "rs880";
913 case CHIP_RV710:
914 return "rv710";
915 case CHIP_RV730:
916 return "rv730";
917 case CHIP_RV740:
918 case CHIP_RV770:
919 return "rv770";
920 case CHIP_PALM:
921 case CHIP_CEDAR:
922 return "cedar";
923 case CHIP_SUMO:
924 case CHIP_SUMO2:
925 return "sumo";
926 case CHIP_REDWOOD:
927 return "redwood";
928 case CHIP_JUNIPER:
929 return "juniper";
930 case CHIP_HEMLOCK:
931 case CHIP_CYPRESS:
932 return "cypress";
933 case CHIP_BARTS:
934 return "barts";
935 case CHIP_TURKS:
936 return "turks";
937 case CHIP_CAICOS:
938 return "caicos";
939 case CHIP_CAYMAN:
940 case CHIP_ARUBA:
941 return "cayman";
942
943 case CHIP_TAHITI: return "tahiti";
944 case CHIP_PITCAIRN: return "pitcairn";
945 case CHIP_VERDE: return "verde";
946 case CHIP_OLAND: return "oland";
947 case CHIP_HAINAN: return "hainan";
948 case CHIP_BONAIRE: return "bonaire";
949 case CHIP_KABINI: return "kabini";
950 case CHIP_KAVERI: return "kaveri";
951 case CHIP_HAWAII: return "hawaii";
952 case CHIP_MULLINS:
953 return "mullins";
954 case CHIP_TONGA: return "tonga";
955 case CHIP_ICELAND: return "iceland";
956 case CHIP_CARRIZO: return "carrizo";
957 case CHIP_FIJI:
958 return "fiji";
959 case CHIP_STONEY:
960 return "stoney";
961 case CHIP_POLARIS10:
962 return HAVE_LLVM >= 0x0309 ? "polaris10" : "carrizo";
963 case CHIP_POLARIS11:
964 case CHIP_POLARIS12: /* same as polaris11 */
965 return HAVE_LLVM >= 0x0309 ? "polaris11" : "carrizo";
966 case CHIP_VEGA10:
967 return "gfx900";
968 default:
969 return "";
970 }
971 }
972
973 static int r600_get_compute_param(struct pipe_screen *screen,
974 enum pipe_shader_ir ir_type,
975 enum pipe_compute_cap param,
976 void *ret)
977 {
978 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
979
980 //TODO: select these params by asic
981 switch (param) {
982 case PIPE_COMPUTE_CAP_IR_TARGET: {
983 const char *gpu;
984 const char *triple;
985 if (rscreen->family <= CHIP_ARUBA) {
986 triple = "r600--";
987 } else {
988 if (HAVE_LLVM < 0x0400) {
989 triple = "amdgcn--";
990 } else {
991 triple = "amdgcn-mesa-mesa3d";
992 }
993 }
994 switch(rscreen->family) {
995 /* Clang < 3.6 is missing Hainan in its list of
996 * GPUs, so we need to use the name of a similar GPU.
997 */
998 default:
999 gpu = r600_get_llvm_processor_name(rscreen->family);
1000 break;
1001 }
1002 if (ret) {
1003 sprintf(ret, "%s-%s", gpu, triple);
1004 }
1005 /* +2 for dash and terminating NIL byte */
1006 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
1007 }
1008 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
1009 if (ret) {
1010 uint64_t *grid_dimension = ret;
1011 grid_dimension[0] = 3;
1012 }
1013 return 1 * sizeof(uint64_t);
1014
1015 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
1016 if (ret) {
1017 uint64_t *grid_size = ret;
1018 grid_size[0] = 65535;
1019 grid_size[1] = 65535;
1020 grid_size[2] = 65535;
1021 }
1022 return 3 * sizeof(uint64_t) ;
1023
1024 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
1025 if (ret) {
1026 uint64_t *block_size = ret;
1027 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
1028 ir_type == PIPE_SHADER_IR_TGSI) {
1029 block_size[0] = 2048;
1030 block_size[1] = 2048;
1031 block_size[2] = 2048;
1032 } else {
1033 block_size[0] = 256;
1034 block_size[1] = 256;
1035 block_size[2] = 256;
1036 }
1037 }
1038 return 3 * sizeof(uint64_t);
1039
1040 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
1041 if (ret) {
1042 uint64_t *max_threads_per_block = ret;
1043 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
1044 ir_type == PIPE_SHADER_IR_TGSI)
1045 *max_threads_per_block = 2048;
1046 else
1047 *max_threads_per_block = 256;
1048 }
1049 return sizeof(uint64_t);
1050 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
1051 if (ret) {
1052 uint32_t *address_bits = ret;
1053 address_bits[0] = 32;
1054 if (rscreen->chip_class >= SI)
1055 address_bits[0] = 64;
1056 }
1057 return 1 * sizeof(uint32_t);
1058
1059 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
1060 if (ret) {
1061 uint64_t *max_global_size = ret;
1062 uint64_t max_mem_alloc_size;
1063
1064 r600_get_compute_param(screen, ir_type,
1065 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
1066 &max_mem_alloc_size);
1067
1068 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1069 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1070 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1071 * make sure we never report more than
1072 * 4 * MAX_MEM_ALLOC_SIZE.
1073 */
1074 *max_global_size = MIN2(4 * max_mem_alloc_size,
1075 MAX2(rscreen->info.gart_size,
1076 rscreen->info.vram_size));
1077 }
1078 return sizeof(uint64_t);
1079
1080 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1081 if (ret) {
1082 uint64_t *max_local_size = ret;
1083 /* Value reported by the closed source driver. */
1084 *max_local_size = 32768;
1085 }
1086 return sizeof(uint64_t);
1087
1088 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1089 if (ret) {
1090 uint64_t *max_input_size = ret;
1091 /* Value reported by the closed source driver. */
1092 *max_input_size = 1024;
1093 }
1094 return sizeof(uint64_t);
1095
1096 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1097 if (ret) {
1098 uint64_t *max_mem_alloc_size = ret;
1099
1100 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1101 }
1102 return sizeof(uint64_t);
1103
1104 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1105 if (ret) {
1106 uint32_t *max_clock_frequency = ret;
1107 *max_clock_frequency = rscreen->info.max_shader_clock;
1108 }
1109 return sizeof(uint32_t);
1110
1111 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1112 if (ret) {
1113 uint32_t *max_compute_units = ret;
1114 *max_compute_units = rscreen->info.num_good_compute_units;
1115 }
1116 return sizeof(uint32_t);
1117
1118 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1119 if (ret) {
1120 uint32_t *images_supported = ret;
1121 *images_supported = 0;
1122 }
1123 return sizeof(uint32_t);
1124 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1125 break; /* unused */
1126 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1127 if (ret) {
1128 uint32_t *subgroup_size = ret;
1129 *subgroup_size = r600_wavefront_size(rscreen->family);
1130 }
1131 return sizeof(uint32_t);
1132 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1133 if (ret) {
1134 uint64_t *max_variable_threads_per_block = ret;
1135 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
1136 ir_type == PIPE_SHADER_IR_TGSI)
1137 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
1138 else
1139 *max_variable_threads_per_block = 0;
1140 }
1141 return sizeof(uint64_t);
1142 }
1143
1144 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1145 return 0;
1146 }
1147
1148 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1149 {
1150 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1151
1152 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1153 rscreen->info.clock_crystal_freq;
1154 }
1155
1156 static void r600_fence_reference(struct pipe_screen *screen,
1157 struct pipe_fence_handle **dst,
1158 struct pipe_fence_handle *src)
1159 {
1160 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1161 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1162 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1163
1164 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1165 ws->fence_reference(&(*rdst)->gfx, NULL);
1166 ws->fence_reference(&(*rdst)->sdma, NULL);
1167 FREE(*rdst);
1168 }
1169 *rdst = rsrc;
1170 }
1171
1172 static boolean r600_fence_finish(struct pipe_screen *screen,
1173 struct pipe_context *ctx,
1174 struct pipe_fence_handle *fence,
1175 uint64_t timeout)
1176 {
1177 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1178 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1179 struct r600_common_context *rctx =
1180 ctx ? (struct r600_common_context*)ctx : NULL;
1181 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1182
1183 if (rfence->sdma) {
1184 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1185 return false;
1186
1187 /* Recompute the timeout after waiting. */
1188 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1189 int64_t time = os_time_get_nano();
1190 timeout = abs_timeout > time ? abs_timeout - time : 0;
1191 }
1192 }
1193
1194 if (!rfence->gfx)
1195 return true;
1196
1197 /* Flush the gfx IB if it hasn't been flushed yet. */
1198 if (rctx &&
1199 rfence->gfx_unflushed.ctx == rctx &&
1200 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1201 rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
1202 rfence->gfx_unflushed.ctx = NULL;
1203
1204 if (!timeout)
1205 return false;
1206
1207 /* Recompute the timeout after all that. */
1208 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1209 int64_t time = os_time_get_nano();
1210 timeout = abs_timeout > time ? abs_timeout - time : 0;
1211 }
1212 }
1213
1214 return rws->fence_wait(rws, rfence->gfx, timeout);
1215 }
1216
1217 static void r600_query_memory_info(struct pipe_screen *screen,
1218 struct pipe_memory_info *info)
1219 {
1220 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1221 struct radeon_winsys *ws = rscreen->ws;
1222 unsigned vram_usage, gtt_usage;
1223
1224 info->total_device_memory = rscreen->info.vram_size / 1024;
1225 info->total_staging_memory = rscreen->info.gart_size / 1024;
1226
1227 /* The real TTM memory usage is somewhat random, because:
1228 *
1229 * 1) TTM delays freeing memory, because it can only free it after
1230 * fences expire.
1231 *
1232 * 2) The memory usage can be really low if big VRAM evictions are
1233 * taking place, but the real usage is well above the size of VRAM.
1234 *
1235 * Instead, return statistics of this process.
1236 */
1237 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1238 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1239
1240 info->avail_device_memory =
1241 vram_usage <= info->total_device_memory ?
1242 info->total_device_memory - vram_usage : 0;
1243 info->avail_staging_memory =
1244 gtt_usage <= info->total_staging_memory ?
1245 info->total_staging_memory - gtt_usage : 0;
1246
1247 info->device_memory_evicted =
1248 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1249
1250 if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
1251 info->nr_device_memory_evictions =
1252 ws->query_value(ws, RADEON_NUM_EVICTIONS);
1253 else
1254 /* Just return the number of evicted 64KB pages. */
1255 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1256 }
1257
1258 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1259 const struct pipe_resource *templ)
1260 {
1261 if (templ->target == PIPE_BUFFER) {
1262 return r600_buffer_create(screen, templ, 256);
1263 } else {
1264 return r600_texture_create(screen, templ);
1265 }
1266 }
1267
1268 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1269 struct radeon_winsys *ws)
1270 {
1271 char llvm_string[32] = {}, kernel_version[128] = {};
1272 struct utsname uname_data;
1273
1274 ws->query_info(ws, &rscreen->info);
1275
1276 if (uname(&uname_data) == 0)
1277 snprintf(kernel_version, sizeof(kernel_version),
1278 " / %s", uname_data.release);
1279
1280 if (HAVE_LLVM > 0) {
1281 snprintf(llvm_string, sizeof(llvm_string),
1282 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1283 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1284 }
1285
1286 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1287 "%s (DRM %i.%i.%i%s%s)",
1288 r600_get_chip_name(rscreen), rscreen->info.drm_major,
1289 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1290 kernel_version, llvm_string);
1291
1292 rscreen->b.get_name = r600_get_name;
1293 rscreen->b.get_vendor = r600_get_vendor;
1294 rscreen->b.get_device_vendor = r600_get_device_vendor;
1295 rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
1296 rscreen->b.get_compute_param = r600_get_compute_param;
1297 rscreen->b.get_paramf = r600_get_paramf;
1298 rscreen->b.get_timestamp = r600_get_timestamp;
1299 rscreen->b.fence_finish = r600_fence_finish;
1300 rscreen->b.fence_reference = r600_fence_reference;
1301 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1302 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1303 rscreen->b.query_memory_info = r600_query_memory_info;
1304
1305 if (rscreen->info.has_uvd) {
1306 rscreen->b.get_video_param = rvid_get_video_param;
1307 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1308 } else {
1309 rscreen->b.get_video_param = r600_get_video_param;
1310 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1311 }
1312
1313 r600_init_screen_texture_functions(rscreen);
1314 r600_init_screen_query_functions(rscreen);
1315
1316 rscreen->ws = ws;
1317 rscreen->family = rscreen->info.family;
1318 rscreen->chip_class = rscreen->info.chip_class;
1319 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1320
1321 r600_disk_cache_create(rscreen);
1322
1323 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1324
1325 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1326 if (rscreen->force_aniso >= 0) {
1327 printf("radeon: Forcing anisotropy filter to %ix\n",
1328 /* round down to a power of two */
1329 1 << util_logbase2(rscreen->force_aniso));
1330 }
1331
1332 util_format_s3tc_init();
1333 (void) mtx_init(&rscreen->aux_context_lock, mtx_plain);
1334 (void) mtx_init(&rscreen->gpu_load_mutex, mtx_plain);
1335
1336 if (rscreen->debug_flags & DBG_INFO) {
1337 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1338 printf("family = %i (%s)\n", rscreen->info.family,
1339 r600_get_chip_name(rscreen));
1340 printf("chip_class = %i\n", rscreen->info.chip_class);
1341 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1342 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1343 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024));
1344 printf("max_alloc_size = %i MB\n",
1345 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1346 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1347 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1348 printf("has_sdma = %i\n", rscreen->info.has_sdma);
1349 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1350 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1351 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1352 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1353 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1354 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1355 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1356 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1357 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1358 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1359
1360 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1361 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1362 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1363 printf("max_se = %i\n", rscreen->info.max_se);
1364 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1365
1366 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1367 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1368 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1369 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1370 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1371 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1372 printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask);
1373 }
1374 return true;
1375 }
1376
1377 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1378 {
1379 r600_perfcounters_destroy(rscreen);
1380 r600_gpu_load_kill_thread(rscreen);
1381
1382 mtx_destroy(&rscreen->gpu_load_mutex);
1383 mtx_destroy(&rscreen->aux_context_lock);
1384 rscreen->aux_context->destroy(rscreen->aux_context);
1385
1386 slab_destroy_parent(&rscreen->pool_transfers);
1387
1388 disk_cache_destroy(rscreen->disk_shader_cache);
1389 rscreen->ws->destroy(rscreen->ws);
1390 FREE(rscreen);
1391 }
1392
1393 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1394 unsigned processor)
1395 {
1396 switch (processor) {
1397 case PIPE_SHADER_VERTEX:
1398 return (rscreen->debug_flags & DBG_VS) != 0;
1399 case PIPE_SHADER_TESS_CTRL:
1400 return (rscreen->debug_flags & DBG_TCS) != 0;
1401 case PIPE_SHADER_TESS_EVAL:
1402 return (rscreen->debug_flags & DBG_TES) != 0;
1403 case PIPE_SHADER_GEOMETRY:
1404 return (rscreen->debug_flags & DBG_GS) != 0;
1405 case PIPE_SHADER_FRAGMENT:
1406 return (rscreen->debug_flags & DBG_PS) != 0;
1407 case PIPE_SHADER_COMPUTE:
1408 return (rscreen->debug_flags & DBG_CS) != 0;
1409 default:
1410 return false;
1411 }
1412 }
1413
1414 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1415 {
1416 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1417 r600_can_dump_shader(rscreen, processor);
1418 }
1419
1420 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1421 uint64_t offset, uint64_t size, unsigned value)
1422 {
1423 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1424
1425 mtx_lock(&rscreen->aux_context_lock);
1426 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1427 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1428 mtx_unlock(&rscreen->aux_context_lock);
1429 }