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gallium/radeon: remove the percentage symbol from HUD temperature
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_memory.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_upload_mgr.h"
34 #include "vl/vl_decoder.h"
35 #include "vl/vl_video_buffer.h"
36 #include "radeon/radeon_video.h"
37 #include <inttypes.h>
38
39 #ifndef HAVE_LLVM
40 #define HAVE_LLVM 0
41 #endif
42
43 /*
44 * pipe_context
45 */
46
47 void r600_draw_rectangle(struct blitter_context *blitter,
48 int x1, int y1, int x2, int y2, float depth,
49 enum blitter_attrib_type type,
50 const union pipe_color_union *attrib)
51 {
52 struct r600_common_context *rctx =
53 (struct r600_common_context*)util_blitter_get_pipe(blitter);
54 struct pipe_viewport_state viewport;
55 struct pipe_resource *buf = NULL;
56 unsigned offset = 0;
57 float *vb;
58
59 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
60 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
61 return;
62 }
63
64 /* Some operations (like color resolve on r6xx) don't work
65 * with the conventional primitive types.
66 * One that works is PT_RECTLIST, which we use here. */
67
68 /* setup viewport */
69 viewport.scale[0] = 1.0f;
70 viewport.scale[1] = 1.0f;
71 viewport.scale[2] = 1.0f;
72 viewport.translate[0] = 0.0f;
73 viewport.translate[1] = 0.0f;
74 viewport.translate[2] = 0.0f;
75 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
76
77 /* Upload vertices. The hw rectangle has only 3 vertices,
78 * I guess the 4th one is derived from the first 3.
79 * The vertex specification should match u_blitter's vertex element state. */
80 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
81 if (!buf)
82 return;
83
84 vb[0] = x1;
85 vb[1] = y1;
86 vb[2] = depth;
87 vb[3] = 1;
88
89 vb[8] = x1;
90 vb[9] = y2;
91 vb[10] = depth;
92 vb[11] = 1;
93
94 vb[16] = x2;
95 vb[17] = y1;
96 vb[18] = depth;
97 vb[19] = 1;
98
99 if (attrib) {
100 memcpy(vb+4, attrib->f, sizeof(float)*4);
101 memcpy(vb+12, attrib->f, sizeof(float)*4);
102 memcpy(vb+20, attrib->f, sizeof(float)*4);
103 }
104
105 /* draw */
106 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
107 R600_PRIM_RECTANGLE_LIST, 3, 2);
108 pipe_resource_reference(&buf, NULL);
109 }
110
111 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
112 {
113 /* Flush if there's not enough space. */
114 if ((num_dw + ctx->rings.dma.cs->cdw) > ctx->rings.dma.cs->max_dw) {
115 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
116 assert((num_dw + ctx->rings.dma.cs->cdw) <= ctx->rings.dma.cs->max_dw);
117 }
118 }
119
120 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
121 {
122 }
123
124 void r600_preflush_suspend_features(struct r600_common_context *ctx)
125 {
126 /* Disable render condition. */
127 ctx->saved_render_cond = NULL;
128 ctx->saved_render_cond_cond = FALSE;
129 ctx->saved_render_cond_mode = 0;
130 if (ctx->current_render_cond) {
131 ctx->saved_render_cond = ctx->current_render_cond;
132 ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
133 ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
134 ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
135 }
136
137 /* suspend queries */
138 ctx->queries_suspended_for_flush = false;
139 if (ctx->num_cs_dw_nontimer_queries_suspend) {
140 r600_suspend_nontimer_queries(ctx);
141 r600_suspend_timer_queries(ctx);
142 ctx->queries_suspended_for_flush = true;
143 }
144
145 ctx->streamout.suspended = false;
146 if (ctx->streamout.begin_emitted) {
147 r600_emit_streamout_end(ctx);
148 ctx->streamout.suspended = true;
149 }
150 }
151
152 void r600_postflush_resume_features(struct r600_common_context *ctx)
153 {
154 if (ctx->streamout.suspended) {
155 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
156 r600_streamout_buffers_dirty(ctx);
157 }
158
159 /* resume queries */
160 if (ctx->queries_suspended_for_flush) {
161 r600_resume_nontimer_queries(ctx);
162 r600_resume_timer_queries(ctx);
163 }
164
165 /* Re-enable render condition. */
166 if (ctx->saved_render_cond) {
167 ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
168 ctx->saved_render_cond_cond,
169 ctx->saved_render_cond_mode);
170 }
171 }
172
173 static void r600_flush_from_st(struct pipe_context *ctx,
174 struct pipe_fence_handle **fence,
175 unsigned flags)
176 {
177 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
178 unsigned rflags = 0;
179
180 if (flags & PIPE_FLUSH_END_OF_FRAME)
181 rflags |= RADEON_FLUSH_END_OF_FRAME;
182
183 if (rctx->rings.dma.cs) {
184 rctx->rings.dma.flush(rctx, rflags, NULL);
185 }
186 rctx->rings.gfx.flush(rctx, rflags, fence);
187 }
188
189 static void r600_flush_dma_ring(void *ctx, unsigned flags,
190 struct pipe_fence_handle **fence)
191 {
192 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
193 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
194
195 if (!cs->cdw) {
196 return;
197 }
198
199 rctx->rings.dma.flushing = true;
200 rctx->ws->cs_flush(cs, flags, fence, 0);
201 rctx->rings.dma.flushing = false;
202 }
203
204 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
205 {
206 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
207 unsigned latest = rctx->ws->query_value(rctx->ws,
208 RADEON_GPU_RESET_COUNTER);
209
210 if (rctx->gpu_reset_counter == latest)
211 return PIPE_NO_RESET;
212
213 rctx->gpu_reset_counter = latest;
214 return PIPE_UNKNOWN_CONTEXT_RESET;
215 }
216
217 bool r600_common_context_init(struct r600_common_context *rctx,
218 struct r600_common_screen *rscreen)
219 {
220 util_slab_create(&rctx->pool_transfers,
221 sizeof(struct r600_transfer), 64,
222 UTIL_SLAB_SINGLETHREADED);
223
224 rctx->screen = rscreen;
225 rctx->ws = rscreen->ws;
226 rctx->family = rscreen->family;
227 rctx->chip_class = rscreen->chip_class;
228
229 if (rscreen->family == CHIP_HAWAII)
230 rctx->max_db = 16;
231 else if (rscreen->chip_class >= EVERGREEN)
232 rctx->max_db = 8;
233 else
234 rctx->max_db = 4;
235
236 rctx->b.transfer_map = u_transfer_map_vtbl;
237 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
238 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
239 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
240 rctx->b.memory_barrier = r600_memory_barrier;
241 rctx->b.flush = r600_flush_from_st;
242
243 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
244 rctx->b.get_device_reset_status = r600_get_reset_status;
245 rctx->gpu_reset_counter =
246 rctx->ws->query_value(rctx->ws,
247 RADEON_GPU_RESET_COUNTER);
248 }
249
250 LIST_INITHEAD(&rctx->texture_buffers);
251
252 r600_init_context_texture_functions(rctx);
253 r600_streamout_init(rctx);
254 r600_query_init(rctx);
255 cayman_init_msaa(&rctx->b);
256
257 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
258 0, PIPE_USAGE_DEFAULT, TRUE);
259 if (!rctx->allocator_so_filled_size)
260 return false;
261
262 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
263 PIPE_BIND_INDEX_BUFFER |
264 PIPE_BIND_CONSTANT_BUFFER);
265 if (!rctx->uploader)
266 return false;
267
268 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
269 if (!rctx->ctx)
270 return false;
271
272 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
273 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
274 r600_flush_dma_ring,
275 rctx, NULL);
276 rctx->rings.dma.flush = r600_flush_dma_ring;
277 }
278
279 return true;
280 }
281
282 void r600_common_context_cleanup(struct r600_common_context *rctx)
283 {
284 if (rctx->rings.gfx.cs)
285 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
286 if (rctx->rings.dma.cs)
287 rctx->ws->cs_destroy(rctx->rings.dma.cs);
288 if (rctx->ctx)
289 rctx->ws->ctx_destroy(rctx->ctx);
290
291 if (rctx->uploader) {
292 u_upload_destroy(rctx->uploader);
293 }
294
295 util_slab_destroy(&rctx->pool_transfers);
296
297 if (rctx->allocator_so_filled_size) {
298 u_suballocator_destroy(rctx->allocator_so_filled_size);
299 }
300 }
301
302 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
303 {
304 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
305 struct r600_resource *rr = (struct r600_resource *)r;
306
307 if (r == NULL) {
308 return;
309 }
310
311 /*
312 * The idea is to compute a gross estimate of memory requirement of
313 * each draw call. After each draw call, memory will be precisely
314 * accounted. So the uncertainty is only on the current draw call.
315 * In practice this gave very good estimate (+/- 10% of the target
316 * memory limit).
317 */
318 if (rr->domains & RADEON_DOMAIN_GTT) {
319 rctx->gtt += rr->buf->size;
320 }
321 if (rr->domains & RADEON_DOMAIN_VRAM) {
322 rctx->vram += rr->buf->size;
323 }
324 }
325
326 /*
327 * pipe_screen
328 */
329
330 static const struct debug_named_value common_debug_options[] = {
331 /* logging */
332 { "tex", DBG_TEX, "Print texture info" },
333 { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
334 { "compute", DBG_COMPUTE, "Print compute info" },
335 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
336 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
337 { "info", DBG_INFO, "Print driver information" },
338
339 /* shaders */
340 { "fs", DBG_FS, "Print fetch shaders" },
341 { "vs", DBG_VS, "Print vertex shaders" },
342 { "gs", DBG_GS, "Print geometry shaders" },
343 { "ps", DBG_PS, "Print pixel shaders" },
344 { "cs", DBG_CS, "Print compute shaders" },
345 { "tcs", DBG_TCS, "Print tessellation control shaders" },
346 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
347 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
348 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
349 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
350
351 /* features */
352 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
353 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
354 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
355 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
356 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
357 { "notiling", DBG_NO_TILING, "Disable tiling" },
358 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
359 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
360 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
361 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
362
363 DEBUG_NAMED_VALUE_END /* must be last */
364 };
365
366 static const char* r600_get_vendor(struct pipe_screen* pscreen)
367 {
368 return "X.Org";
369 }
370
371 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
372 {
373 return "AMD";
374 }
375
376 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
377 {
378 switch (rscreen->info.family) {
379 case CHIP_R600: return "AMD R600";
380 case CHIP_RV610: return "AMD RV610";
381 case CHIP_RV630: return "AMD RV630";
382 case CHIP_RV670: return "AMD RV670";
383 case CHIP_RV620: return "AMD RV620";
384 case CHIP_RV635: return "AMD RV635";
385 case CHIP_RS780: return "AMD RS780";
386 case CHIP_RS880: return "AMD RS880";
387 case CHIP_RV770: return "AMD RV770";
388 case CHIP_RV730: return "AMD RV730";
389 case CHIP_RV710: return "AMD RV710";
390 case CHIP_RV740: return "AMD RV740";
391 case CHIP_CEDAR: return "AMD CEDAR";
392 case CHIP_REDWOOD: return "AMD REDWOOD";
393 case CHIP_JUNIPER: return "AMD JUNIPER";
394 case CHIP_CYPRESS: return "AMD CYPRESS";
395 case CHIP_HEMLOCK: return "AMD HEMLOCK";
396 case CHIP_PALM: return "AMD PALM";
397 case CHIP_SUMO: return "AMD SUMO";
398 case CHIP_SUMO2: return "AMD SUMO2";
399 case CHIP_BARTS: return "AMD BARTS";
400 case CHIP_TURKS: return "AMD TURKS";
401 case CHIP_CAICOS: return "AMD CAICOS";
402 case CHIP_CAYMAN: return "AMD CAYMAN";
403 case CHIP_ARUBA: return "AMD ARUBA";
404 case CHIP_TAHITI: return "AMD TAHITI";
405 case CHIP_PITCAIRN: return "AMD PITCAIRN";
406 case CHIP_VERDE: return "AMD CAPE VERDE";
407 case CHIP_OLAND: return "AMD OLAND";
408 case CHIP_HAINAN: return "AMD HAINAN";
409 case CHIP_BONAIRE: return "AMD BONAIRE";
410 case CHIP_KAVERI: return "AMD KAVERI";
411 case CHIP_KABINI: return "AMD KABINI";
412 case CHIP_HAWAII: return "AMD HAWAII";
413 case CHIP_MULLINS: return "AMD MULLINS";
414 case CHIP_TONGA: return "AMD TONGA";
415 case CHIP_ICELAND: return "AMD ICELAND";
416 case CHIP_CARRIZO: return "AMD CARRIZO";
417 case CHIP_FIJI: return "AMD FIJI";
418 default: return "AMD unknown";
419 }
420 }
421
422 static const char* r600_get_name(struct pipe_screen* pscreen)
423 {
424 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
425
426 return rscreen->renderer_string;
427 }
428
429 static float r600_get_paramf(struct pipe_screen* pscreen,
430 enum pipe_capf param)
431 {
432 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
433
434 switch (param) {
435 case PIPE_CAPF_MAX_LINE_WIDTH:
436 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
437 case PIPE_CAPF_MAX_POINT_WIDTH:
438 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
439 if (rscreen->family >= CHIP_CEDAR)
440 return 16384.0f;
441 else
442 return 8192.0f;
443 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
444 return 16.0f;
445 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
446 return 16.0f;
447 case PIPE_CAPF_GUARD_BAND_LEFT:
448 case PIPE_CAPF_GUARD_BAND_TOP:
449 case PIPE_CAPF_GUARD_BAND_RIGHT:
450 case PIPE_CAPF_GUARD_BAND_BOTTOM:
451 return 0.0f;
452 }
453 return 0.0f;
454 }
455
456 static int r600_get_video_param(struct pipe_screen *screen,
457 enum pipe_video_profile profile,
458 enum pipe_video_entrypoint entrypoint,
459 enum pipe_video_cap param)
460 {
461 switch (param) {
462 case PIPE_VIDEO_CAP_SUPPORTED:
463 return vl_profile_supported(screen, profile, entrypoint);
464 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
465 return 1;
466 case PIPE_VIDEO_CAP_MAX_WIDTH:
467 case PIPE_VIDEO_CAP_MAX_HEIGHT:
468 return vl_video_buffer_max_size(screen);
469 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
470 return PIPE_FORMAT_NV12;
471 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
472 return false;
473 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
474 return false;
475 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
476 return true;
477 case PIPE_VIDEO_CAP_MAX_LEVEL:
478 return vl_level_supported(screen, profile);
479 default:
480 return 0;
481 }
482 }
483
484 const char *r600_get_llvm_processor_name(enum radeon_family family)
485 {
486 switch (family) {
487 case CHIP_R600:
488 case CHIP_RV630:
489 case CHIP_RV635:
490 case CHIP_RV670:
491 return "r600";
492 case CHIP_RV610:
493 case CHIP_RV620:
494 case CHIP_RS780:
495 case CHIP_RS880:
496 return "rs880";
497 case CHIP_RV710:
498 return "rv710";
499 case CHIP_RV730:
500 return "rv730";
501 case CHIP_RV740:
502 case CHIP_RV770:
503 return "rv770";
504 case CHIP_PALM:
505 case CHIP_CEDAR:
506 return "cedar";
507 case CHIP_SUMO:
508 case CHIP_SUMO2:
509 return "sumo";
510 case CHIP_REDWOOD:
511 return "redwood";
512 case CHIP_JUNIPER:
513 return "juniper";
514 case CHIP_HEMLOCK:
515 case CHIP_CYPRESS:
516 return "cypress";
517 case CHIP_BARTS:
518 return "barts";
519 case CHIP_TURKS:
520 return "turks";
521 case CHIP_CAICOS:
522 return "caicos";
523 case CHIP_CAYMAN:
524 case CHIP_ARUBA:
525 return "cayman";
526
527 case CHIP_TAHITI: return "tahiti";
528 case CHIP_PITCAIRN: return "pitcairn";
529 case CHIP_VERDE: return "verde";
530 case CHIP_OLAND: return "oland";
531 case CHIP_HAINAN: return "hainan";
532 case CHIP_BONAIRE: return "bonaire";
533 case CHIP_KABINI: return "kabini";
534 case CHIP_KAVERI: return "kaveri";
535 case CHIP_HAWAII: return "hawaii";
536 case CHIP_MULLINS:
537 return "mullins";
538 case CHIP_TONGA: return "tonga";
539 case CHIP_ICELAND: return "iceland";
540 case CHIP_CARRIZO: return "carrizo";
541 case CHIP_FIJI: return "fiji";
542 default: return "";
543 }
544 }
545
546 static int r600_get_compute_param(struct pipe_screen *screen,
547 enum pipe_compute_cap param,
548 void *ret)
549 {
550 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
551
552 //TODO: select these params by asic
553 switch (param) {
554 case PIPE_COMPUTE_CAP_IR_TARGET: {
555 const char *gpu;
556 const char *triple;
557 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
558 triple = "r600--";
559 } else {
560 triple = "amdgcn--";
561 }
562 switch(rscreen->family) {
563 /* Clang < 3.6 is missing Hainan in its list of
564 * GPUs, so we need to use the name of a similar GPU.
565 */
566 #if HAVE_LLVM < 0x0306
567 case CHIP_HAINAN:
568 gpu = "oland";
569 break;
570 #endif
571 default:
572 gpu = r600_get_llvm_processor_name(rscreen->family);
573 break;
574 }
575 if (ret) {
576 sprintf(ret, "%s-%s", gpu, triple);
577 }
578 /* +2 for dash and terminating NIL byte */
579 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
580 }
581 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
582 if (ret) {
583 uint64_t *grid_dimension = ret;
584 grid_dimension[0] = 3;
585 }
586 return 1 * sizeof(uint64_t);
587
588 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
589 if (ret) {
590 uint64_t *grid_size = ret;
591 grid_size[0] = 65535;
592 grid_size[1] = 65535;
593 grid_size[2] = 1;
594 }
595 return 3 * sizeof(uint64_t) ;
596
597 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
598 if (ret) {
599 uint64_t *block_size = ret;
600 block_size[0] = 256;
601 block_size[1] = 256;
602 block_size[2] = 256;
603 }
604 return 3 * sizeof(uint64_t);
605
606 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
607 if (ret) {
608 uint64_t *max_threads_per_block = ret;
609 *max_threads_per_block = 256;
610 }
611 return sizeof(uint64_t);
612
613 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
614 if (ret) {
615 uint64_t *max_global_size = ret;
616 uint64_t max_mem_alloc_size;
617
618 r600_get_compute_param(screen,
619 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
620 &max_mem_alloc_size);
621
622 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
623 * 1/4 of the MAX_GLOBAL_SIZE. Since the
624 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
625 * make sure we never report more than
626 * 4 * MAX_MEM_ALLOC_SIZE.
627 */
628 *max_global_size = MIN2(4 * max_mem_alloc_size,
629 rscreen->info.gart_size +
630 rscreen->info.vram_size);
631 }
632 return sizeof(uint64_t);
633
634 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
635 if (ret) {
636 uint64_t *max_local_size = ret;
637 /* Value reported by the closed source driver. */
638 *max_local_size = 32768;
639 }
640 return sizeof(uint64_t);
641
642 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
643 if (ret) {
644 uint64_t *max_input_size = ret;
645 /* Value reported by the closed source driver. */
646 *max_input_size = 1024;
647 }
648 return sizeof(uint64_t);
649
650 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
651 if (ret) {
652 uint64_t *max_mem_alloc_size = ret;
653
654 /* XXX: The limit in older kernels is 256 MB. We
655 * should add a query here for newer kernels.
656 */
657 *max_mem_alloc_size = 256 * 1024 * 1024;
658 }
659 return sizeof(uint64_t);
660
661 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
662 if (ret) {
663 uint32_t *max_clock_frequency = ret;
664 *max_clock_frequency = rscreen->info.max_sclk;
665 }
666 return sizeof(uint32_t);
667
668 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
669 if (ret) {
670 uint32_t *max_compute_units = ret;
671 *max_compute_units = rscreen->info.max_compute_units;
672 }
673 return sizeof(uint32_t);
674
675 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
676 if (ret) {
677 uint32_t *images_supported = ret;
678 *images_supported = 0;
679 }
680 return sizeof(uint32_t);
681 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
682 break; /* unused */
683 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
684 if (ret) {
685 uint32_t *subgroup_size = ret;
686 *subgroup_size = r600_wavefront_size(rscreen->family);
687 }
688 return sizeof(uint32_t);
689 }
690
691 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
692 return 0;
693 }
694
695 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
696 {
697 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
698
699 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
700 rscreen->info.r600_clock_crystal_freq;
701 }
702
703 static int r600_get_driver_query_info(struct pipe_screen *screen,
704 unsigned index,
705 struct pipe_driver_query_info *info)
706 {
707 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
708 struct pipe_driver_query_info list[] = {
709 {"num-compilations", R600_QUERY_NUM_COMPILATIONS, {0}, PIPE_DRIVER_QUERY_TYPE_UINT64,
710 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
711 {"num-shaders-created", R600_QUERY_NUM_SHADERS_CREATED, {0}, PIPE_DRIVER_QUERY_TYPE_UINT64,
712 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
713 {"draw-calls", R600_QUERY_DRAW_CALLS, {0}},
714 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
715 {"requested-GTT", R600_QUERY_REQUESTED_GTT, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
716 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, {0}, PIPE_DRIVER_QUERY_TYPE_MICROSECONDS,
717 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
718 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, {0}},
719 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, {0}, PIPE_DRIVER_QUERY_TYPE_BYTES,
720 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
721 {"VRAM-usage", R600_QUERY_VRAM_USAGE, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
722 {"GTT-usage", R600_QUERY_GTT_USAGE, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
723 {"GPU-load", R600_QUERY_GPU_LOAD, {100}},
724 {"temperature", R600_QUERY_GPU_TEMPERATURE, {125}},
725 {"shader-clock", R600_QUERY_CURRENT_GPU_SCLK, {0}, PIPE_DRIVER_QUERY_TYPE_HZ},
726 {"memory-clock", R600_QUERY_CURRENT_GPU_MCLK, {0}, PIPE_DRIVER_QUERY_TYPE_HZ},
727 };
728 unsigned num_queries;
729
730 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
731 num_queries = Elements(list);
732 else if (rscreen->info.drm_major == 3)
733 num_queries = Elements(list) - 3;
734 else
735 num_queries = Elements(list) - 4;
736
737 if (!info)
738 return num_queries;
739
740 if (index >= num_queries)
741 return 0;
742
743 *info = list[index];
744 return 1;
745 }
746
747 static void r600_fence_reference(struct pipe_screen *screen,
748 struct pipe_fence_handle **ptr,
749 struct pipe_fence_handle *fence)
750 {
751 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
752
753 rws->fence_reference(ptr, fence);
754 }
755
756 static boolean r600_fence_finish(struct pipe_screen *screen,
757 struct pipe_fence_handle *fence,
758 uint64_t timeout)
759 {
760 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
761
762 return rws->fence_wait(rws, fence, timeout);
763 }
764
765 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
766 uint32_t tiling_config)
767 {
768 switch ((tiling_config & 0xe) >> 1) {
769 case 0:
770 rscreen->tiling_info.num_channels = 1;
771 break;
772 case 1:
773 rscreen->tiling_info.num_channels = 2;
774 break;
775 case 2:
776 rscreen->tiling_info.num_channels = 4;
777 break;
778 case 3:
779 rscreen->tiling_info.num_channels = 8;
780 break;
781 default:
782 return false;
783 }
784
785 switch ((tiling_config & 0x30) >> 4) {
786 case 0:
787 rscreen->tiling_info.num_banks = 4;
788 break;
789 case 1:
790 rscreen->tiling_info.num_banks = 8;
791 break;
792 default:
793 return false;
794
795 }
796 switch ((tiling_config & 0xc0) >> 6) {
797 case 0:
798 rscreen->tiling_info.group_bytes = 256;
799 break;
800 case 1:
801 rscreen->tiling_info.group_bytes = 512;
802 break;
803 default:
804 return false;
805 }
806 return true;
807 }
808
809 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
810 uint32_t tiling_config)
811 {
812 switch (tiling_config & 0xf) {
813 case 0:
814 rscreen->tiling_info.num_channels = 1;
815 break;
816 case 1:
817 rscreen->tiling_info.num_channels = 2;
818 break;
819 case 2:
820 rscreen->tiling_info.num_channels = 4;
821 break;
822 case 3:
823 rscreen->tiling_info.num_channels = 8;
824 break;
825 default:
826 return false;
827 }
828
829 switch ((tiling_config & 0xf0) >> 4) {
830 case 0:
831 rscreen->tiling_info.num_banks = 4;
832 break;
833 case 1:
834 rscreen->tiling_info.num_banks = 8;
835 break;
836 case 2:
837 rscreen->tiling_info.num_banks = 16;
838 break;
839 default:
840 return false;
841 }
842
843 switch ((tiling_config & 0xf00) >> 8) {
844 case 0:
845 rscreen->tiling_info.group_bytes = 256;
846 break;
847 case 1:
848 rscreen->tiling_info.group_bytes = 512;
849 break;
850 default:
851 return false;
852 }
853 return true;
854 }
855
856 static bool r600_init_tiling(struct r600_common_screen *rscreen)
857 {
858 uint32_t tiling_config = rscreen->info.r600_tiling_config;
859
860 /* set default group bytes, overridden by tiling info ioctl */
861 if (rscreen->chip_class <= R700) {
862 rscreen->tiling_info.group_bytes = 256;
863 } else {
864 rscreen->tiling_info.group_bytes = 512;
865 }
866
867 if (!tiling_config)
868 return true;
869
870 if (rscreen->chip_class <= R700) {
871 return r600_interpret_tiling(rscreen, tiling_config);
872 } else {
873 return evergreen_interpret_tiling(rscreen, tiling_config);
874 }
875 }
876
877 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
878 const struct pipe_resource *templ)
879 {
880 if (templ->target == PIPE_BUFFER) {
881 return r600_buffer_create(screen, templ, 4096);
882 } else {
883 return r600_texture_create(screen, templ);
884 }
885 }
886
887 bool r600_common_screen_init(struct r600_common_screen *rscreen,
888 struct radeon_winsys *ws)
889 {
890 char llvm_string[32] = {};
891
892 ws->query_info(ws, &rscreen->info);
893
894 #if HAVE_LLVM
895 snprintf(llvm_string, sizeof(llvm_string),
896 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
897 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
898 #endif
899
900 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
901 "%s (DRM %i.%i.%i%s)",
902 r600_get_chip_name(rscreen), rscreen->info.drm_major,
903 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
904 llvm_string);
905
906 rscreen->b.get_name = r600_get_name;
907 rscreen->b.get_vendor = r600_get_vendor;
908 rscreen->b.get_device_vendor = r600_get_device_vendor;
909 rscreen->b.get_compute_param = r600_get_compute_param;
910 rscreen->b.get_paramf = r600_get_paramf;
911 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
912 rscreen->b.get_timestamp = r600_get_timestamp;
913 rscreen->b.fence_finish = r600_fence_finish;
914 rscreen->b.fence_reference = r600_fence_reference;
915 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
916 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
917
918 if (rscreen->info.has_uvd) {
919 rscreen->b.get_video_param = rvid_get_video_param;
920 rscreen->b.is_video_format_supported = rvid_is_format_supported;
921 } else {
922 rscreen->b.get_video_param = r600_get_video_param;
923 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
924 }
925
926 r600_init_screen_texture_functions(rscreen);
927
928 rscreen->ws = ws;
929 rscreen->family = rscreen->info.family;
930 rscreen->chip_class = rscreen->info.chip_class;
931 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
932
933 if (!r600_init_tiling(rscreen)) {
934 return false;
935 }
936 util_format_s3tc_init();
937 pipe_mutex_init(rscreen->aux_context_lock);
938 pipe_mutex_init(rscreen->gpu_load_mutex);
939
940 if (((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 28) ||
941 rscreen->info.drm_major == 3) &&
942 (rscreen->debug_flags & DBG_TRACE_CS)) {
943 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
944 PIPE_BIND_CUSTOM,
945 PIPE_USAGE_STAGING,
946 4096);
947 if (rscreen->trace_bo) {
948 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
949 PIPE_TRANSFER_UNSYNCHRONIZED);
950 }
951 }
952
953 if (rscreen->debug_flags & DBG_INFO) {
954 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
955 printf("family = %i\n", rscreen->info.family);
956 printf("chip_class = %i\n", rscreen->info.chip_class);
957 printf("gart_size = %i MB\n", (int)(rscreen->info.gart_size >> 20));
958 printf("vram_size = %i MB\n", (int)(rscreen->info.vram_size >> 20));
959 printf("max_sclk = %i\n", rscreen->info.max_sclk);
960 printf("max_compute_units = %i\n", rscreen->info.max_compute_units);
961 printf("max_se = %i\n", rscreen->info.max_se);
962 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
963 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
964 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
965 printf("has_uvd = %i\n", rscreen->info.has_uvd);
966 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
967 printf("r600_num_backends = %i\n", rscreen->info.r600_num_backends);
968 printf("r600_clock_crystal_freq = %i\n", rscreen->info.r600_clock_crystal_freq);
969 printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
970 printf("r600_num_tile_pipes = %i\n", rscreen->info.r600_num_tile_pipes);
971 printf("r600_max_pipes = %i\n", rscreen->info.r600_max_pipes);
972 printf("r600_virtual_address = %i\n", rscreen->info.r600_virtual_address);
973 printf("r600_has_dma = %i\n", rscreen->info.r600_has_dma);
974 printf("r600_backend_map = %i\n", rscreen->info.r600_backend_map);
975 printf("r600_backend_map_valid = %i\n", rscreen->info.r600_backend_map_valid);
976 printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
977 printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
978 }
979 return true;
980 }
981
982 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
983 {
984 r600_gpu_load_kill_thread(rscreen);
985
986 pipe_mutex_destroy(rscreen->gpu_load_mutex);
987 pipe_mutex_destroy(rscreen->aux_context_lock);
988 rscreen->aux_context->destroy(rscreen->aux_context);
989
990 if (rscreen->trace_bo)
991 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
992
993 rscreen->ws->destroy(rscreen->ws);
994 FREE(rscreen);
995 }
996
997 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
998 const struct tgsi_token *tokens)
999 {
1000 /* Compute shader don't have tgsi_tokens */
1001 if (!tokens)
1002 return (rscreen->debug_flags & DBG_CS) != 0;
1003
1004 switch (tgsi_get_processor_type(tokens)) {
1005 case TGSI_PROCESSOR_VERTEX:
1006 return (rscreen->debug_flags & DBG_VS) != 0;
1007 case TGSI_PROCESSOR_TESS_CTRL:
1008 return (rscreen->debug_flags & DBG_TCS) != 0;
1009 case TGSI_PROCESSOR_TESS_EVAL:
1010 return (rscreen->debug_flags & DBG_TES) != 0;
1011 case TGSI_PROCESSOR_GEOMETRY:
1012 return (rscreen->debug_flags & DBG_GS) != 0;
1013 case TGSI_PROCESSOR_FRAGMENT:
1014 return (rscreen->debug_flags & DBG_PS) != 0;
1015 case TGSI_PROCESSOR_COMPUTE:
1016 return (rscreen->debug_flags & DBG_CS) != 0;
1017 default:
1018 return false;
1019 }
1020 }
1021
1022 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1023 unsigned offset, unsigned size, unsigned value,
1024 bool is_framebuffer)
1025 {
1026 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1027
1028 pipe_mutex_lock(rscreen->aux_context_lock);
1029 rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
1030 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1031 pipe_mutex_unlock(rscreen->aux_context_lock);
1032 }