src/gallium/drivers/radeon/r600_pipe_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 #include "r600_pipe_common.h"
  28 #include "r600_cs.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "util/list.h"
  31 #include "util/u_draw_quad.h"
  32 #include "util/u_memory.h"
  33 #include "util/u_format_s3tc.h"
  34 #include "util/u_upload_mgr.h"
  35 #include "os/os_time.h"
  36 #include "vl/vl_decoder.h"
  37 #include "vl/vl_video_buffer.h"
  38 #include "radeon/radeon_video.h"
  39 #include <inttypes.h>
  40 #include <sys/utsname.h>
  41
  42 #ifndef HAVE_LLVM
  43 #define HAVE_LLVM 0
  44 #endif
  45
  46 struct r600_multi_fence {
  47         struct pipe_reference reference;
  48         struct pipe_fence_handle *gfx;
  49         struct pipe_fence_handle *sdma;
  50 };
  51
  52 /*
  53  * shader binary helpers.
  54  */
  55 void radeon_shader_binary_init(struct radeon_shader_binary *b)
  56 {
  57         memset(b, 0, sizeof(*b));
  58 }
  59
  60 void radeon_shader_binary_clean(struct radeon_shader_binary *b)
  61 {
  62         if (!b)
  63                 return;
  64         FREE(b->code);
  65         FREE(b->config);
  66         FREE(b->rodata);
  67         FREE(b->global_symbol_offsets);
  68         FREE(b->relocs);
  69         FREE(b->disasm_string);
  70         FREE(b->llvm_ir_string);
  71 }
  72
  73 /*
  74  * pipe_context
  75  */
  76
  77 void r600_draw_rectangle(struct blitter_context *blitter,
  78                          int x1, int y1, int x2, int y2, float depth,
  79                          enum blitter_attrib_type type,
  80                          const union pipe_color_union *attrib)
  81 {
  82         struct r600_common_context *rctx =
  83                 (struct r600_common_context*)util_blitter_get_pipe(blitter);
  84         struct pipe_viewport_state viewport;
  85         struct pipe_resource *buf = NULL;
  86         unsigned offset = 0;
  87         float *vb;
  88
  89         if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
  90                 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
  91                 return;
  92         }
  93
  94         /* Some operations (like color resolve on r6xx) don't work
  95          * with the conventional primitive types.
  96          * One that works is PT_RECTLIST, which we use here. */
  97
  98         /* setup viewport */
  99         viewport.scale[0] = 1.0f;
 100         viewport.scale[1] = 1.0f;
 101         viewport.scale[2] = 1.0f;
 102         viewport.translate[0] = 0.0f;
 103         viewport.translate[1] = 0.0f;
 104         viewport.translate[2] = 0.0f;
 105         rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
 106
 107         /* Upload vertices. The hw rectangle has only 3 vertices,
 108          * I guess the 4th one is derived from the first 3.
 109          * The vertex specification should match u_blitter's vertex element state. */
 110         u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, 256, &offset, &buf, (void**)&vb);
 111         if (!buf)
 112                 return;
 113
 114         vb[0] = x1;
 115         vb[1] = y1;
 116         vb[2] = depth;
 117         vb[3] = 1;
 118
 119         vb[8] = x1;
 120         vb[9] = y2;
 121         vb[10] = depth;
 122         vb[11] = 1;
 123
 124         vb[16] = x2;
 125         vb[17] = y1;
 126         vb[18] = depth;
 127         vb[19] = 1;
 128
 129         if (attrib) {
 130                 memcpy(vb+4, attrib->f, sizeof(float)*4);
 131                 memcpy(vb+12, attrib->f, sizeof(float)*4);
 132                 memcpy(vb+20, attrib->f, sizeof(float)*4);
 133         }
 134
 135         /* draw */
 136         util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
 137                                 R600_PRIM_RECTANGLE_LIST, 3, 2);
 138         pipe_resource_reference(&buf, NULL);
 139 }
 140
 141 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
 142                          struct r600_resource *dst, struct r600_resource *src)
 143 {
 144         uint64_t vram = 0, gtt = 0;
 145
 146         if (dst) {
 147                 if (dst->domains & RADEON_DOMAIN_VRAM)
 148                         vram += dst->buf->size;
 149                 else if (dst->domains & RADEON_DOMAIN_GTT)
 150                         gtt += dst->buf->size;
 151         }
 152         if (src) {
 153                 if (src->domains & RADEON_DOMAIN_VRAM)
 154                         vram += src->buf->size;
 155                 else if (src->domains & RADEON_DOMAIN_GTT)
 156                         gtt += src->buf->size;
 157         }
 158
 159         /* Flush the GFX IB if DMA depends on it. */
 160         if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
 161             ((dst &&
 162               ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
 163                                                RADEON_USAGE_READWRITE)) ||
 164              (src &&
 165               ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
 166                                                RADEON_USAGE_WRITE))))
 167                 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
 168
 169         /* Flush if there's not enough space, or if the memory usage per IB
 170          * is too large.
 171          */
 172         if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
 173             !ctx->ws->cs_memory_below_limit(ctx->dma.cs, vram, gtt)) {
 174                 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
 175                 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
 176         }
 177
 178         /* If GPUVM is not supported, the CS checker needs 2 entries
 179          * in the buffer list per packet, which has to be done manually.
 180          */
 181         if (ctx->screen->info.has_virtual_memory) {
 182                 if (dst)
 183                         radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
 184                                                   RADEON_USAGE_WRITE,
 185                                                   RADEON_PRIO_SDMA_BUFFER);
 186                 if (src)
 187                         radeon_add_to_buffer_list(ctx, &ctx->dma, src,
 188                                                   RADEON_USAGE_READ,
 189                                                   RADEON_PRIO_SDMA_BUFFER);
 190         }
 191 }
 192
 193 /* This is required to prevent read-after-write hazards. */
 194 void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
 195 {
 196         struct radeon_winsys_cs *cs = rctx->dma.cs;
 197
 198         /* done at the end of DMA calls, so increment this. */
 199         rctx->num_dma_calls++;
 200
 201         /* IBs using too little memory are limited by the IB submission overhead.
 202          * IBs using too much memory are limited by the kernel/TTM overhead.
 203          * Too long IBs create CPU-GPU pipeline bubbles and add latency.
 204          *
 205          * This heuristic makes sure that DMA requests are executed
 206          * very soon after the call is made and lowers memory usage.
 207          * It improves texture upload performance by keeping the DMA
 208          * engine busy while uploads are being submitted.
 209          */
 210         if (rctx->ws->cs_query_memory_usage(rctx->dma.cs) > 64 * 1024 * 1024) {
 211                 rctx->dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
 212                 return;
 213         }
 214
 215         r600_need_dma_space(rctx, 1, NULL, NULL);
 216
 217         if (!radeon_emitted(cs, 0)) /* empty queue */
 218                 return;
 219
 220         /* NOP waits for idle on Evergreen and later. */
 221         if (rctx->chip_class >= CIK)
 222                 radeon_emit(cs, 0x00000000); /* NOP */
 223         else if (rctx->chip_class >= EVERGREEN)
 224                 radeon_emit(cs, 0xf0000000); /* NOP */
 225         else {
 226                 /* TODO: R600-R700 should use the FENCE packet.
 227                  * CS checker support is required. */
 228         }
 229 }
 230
 231 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
 232 {
 233 }
 234
 235 void r600_preflush_suspend_features(struct r600_common_context *ctx)
 236 {
 237         /* suspend queries */
 238         if (!LIST_IS_EMPTY(&ctx->active_queries))
 239                 r600_suspend_queries(ctx);
 240
 241         ctx->streamout.suspended = false;
 242         if (ctx->streamout.begin_emitted) {
 243                 r600_emit_streamout_end(ctx);
 244                 ctx->streamout.suspended = true;
 245         }
 246 }
 247
 248 void r600_postflush_resume_features(struct r600_common_context *ctx)
 249 {
 250         if (ctx->streamout.suspended) {
 251                 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
 252                 r600_streamout_buffers_dirty(ctx);
 253         }
 254
 255         /* resume queries */
 256         if (!LIST_IS_EMPTY(&ctx->active_queries))
 257                 r600_resume_queries(ctx);
 258 }
 259
 260 static void r600_flush_from_st(struct pipe_context *ctx,
 261                                struct pipe_fence_handle **fence,
 262                                unsigned flags)
 263 {
 264         struct pipe_screen *screen = ctx->screen;
 265         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 266         unsigned rflags = 0;
 267         struct pipe_fence_handle *gfx_fence = NULL;
 268         struct pipe_fence_handle *sdma_fence = NULL;
 269
 270         if (flags & PIPE_FLUSH_END_OF_FRAME)
 271                 rflags |= RADEON_FLUSH_END_OF_FRAME;
 272
 273         if (rctx->dma.cs) {
 274                 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
 275         }
 276         rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
 277
 278         /* Both engines can signal out of order, so we need to keep both fences. */
 279         if (gfx_fence || sdma_fence) {
 280                 struct r600_multi_fence *multi_fence =
 281                         CALLOC_STRUCT(r600_multi_fence);
 282                 if (!multi_fence)
 283                         return;
 284
 285                 multi_fence->reference.count = 1;
 286                 multi_fence->gfx = gfx_fence;
 287                 multi_fence->sdma = sdma_fence;
 288
 289                 screen->fence_reference(screen, fence, NULL);
 290                 *fence = (struct pipe_fence_handle*)multi_fence;
 291         }
 292 }
 293
 294 static void r600_flush_dma_ring(void *ctx, unsigned flags,
 295                                 struct pipe_fence_handle **fence)
 296 {
 297         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 298         struct radeon_winsys_cs *cs = rctx->dma.cs;
 299         struct radeon_saved_cs saved;
 300         bool check_vm =
 301                 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
 302                 rctx->check_vm_faults;
 303
 304         if (!radeon_emitted(cs, 0)) {
 305                 if (fence)
 306                         rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
 307                 return;
 308         }
 309
 310         if (check_vm)
 311                 radeon_save_cs(rctx->ws, cs, &saved);
 312
 313         rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
 314         if (fence)
 315                 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
 316
 317         if (check_vm) {
 318                 /* Use conservative timeout 800ms, after which we won't wait any
 319                  * longer and assume the GPU is hung.
 320                  */
 321                 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
 322
 323                 rctx->check_vm_faults(rctx, &saved, RING_DMA);
 324                 radeon_clear_saved_cs(&saved);
 325         }
 326 }
 327
 328 /**
 329  * Store a linearized copy of all chunks of \p cs together with the buffer
 330  * list in \p saved.
 331  */
 332 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
 333                     struct radeon_saved_cs *saved)
 334 {
 335         void *buf;
 336         unsigned i;
 337
 338         /* Save the IB chunks. */
 339         saved->num_dw = cs->prev_dw + cs->current.cdw;
 340         saved->ib = MALLOC(4 * saved->num_dw);
 341         if (!saved->ib)
 342                 goto oom;
 343
 344         buf = saved->ib;
 345         for (i = 0; i < cs->num_prev; ++i) {
 346                 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
 347                 buf += cs->prev[i].cdw;
 348         }
 349         memcpy(buf, cs->current.buf, cs->current.cdw * 4);
 350
 351         /* Save the buffer list. */
 352         saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
 353         saved->bo_list = CALLOC(saved->bo_count,
 354                                 sizeof(saved->bo_list[0]));
 355         if (!saved->bo_list) {
 356                 FREE(saved->ib);
 357                 goto oom;
 358         }
 359         ws->cs_get_buffer_list(cs, saved->bo_list);
 360
 361         return;
 362
 363 oom:
 364         fprintf(stderr, "%s: out of memory\n", __func__);
 365         memset(saved, 0, sizeof(*saved));
 366 }
 367
 368 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
 369 {
 370         FREE(saved->ib);
 371         FREE(saved->bo_list);
 372
 373         memset(saved, 0, sizeof(*saved));
 374 }
 375
 376 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
 377 {
 378         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 379         unsigned latest = rctx->ws->query_value(rctx->ws,
 380                                                 RADEON_GPU_RESET_COUNTER);
 381
 382         if (rctx->gpu_reset_counter == latest)
 383                 return PIPE_NO_RESET;
 384
 385         rctx->gpu_reset_counter = latest;
 386         return PIPE_UNKNOWN_CONTEXT_RESET;
 387 }
 388
 389 static void r600_set_debug_callback(struct pipe_context *ctx,
 390                                     const struct pipe_debug_callback *cb)
 391 {
 392         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 393
 394         if (cb)
 395                 rctx->debug = *cb;
 396         else
 397                 memset(&rctx->debug, 0, sizeof(rctx->debug));
 398 }
 399
 400 bool r600_common_context_init(struct r600_common_context *rctx,
 401                               struct r600_common_screen *rscreen)
 402 {
 403         util_slab_create(&rctx->pool_transfers,
 404                          sizeof(struct r600_transfer), 64,
 405                          UTIL_SLAB_SINGLETHREADED);
 406
 407         rctx->screen = rscreen;
 408         rctx->ws = rscreen->ws;
 409         rctx->family = rscreen->family;
 410         rctx->chip_class = rscreen->chip_class;
 411
 412         if (rscreen->chip_class >= CIK)
 413                 rctx->max_db = MAX2(8, rscreen->info.num_render_backends);
 414         else if (rscreen->chip_class >= EVERGREEN)
 415                 rctx->max_db = 8;
 416         else
 417                 rctx->max_db = 4;
 418
 419         rctx->b.invalidate_resource = r600_invalidate_resource;
 420         rctx->b.transfer_map = u_transfer_map_vtbl;
 421         rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
 422         rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
 423         rctx->b.transfer_inline_write = u_default_transfer_inline_write;
 424         rctx->b.memory_barrier = r600_memory_barrier;
 425         rctx->b.flush = r600_flush_from_st;
 426         rctx->b.set_debug_callback = r600_set_debug_callback;
 427
 428         if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
 429                 rctx->b.get_device_reset_status = r600_get_reset_status;
 430                 rctx->gpu_reset_counter =
 431                         rctx->ws->query_value(rctx->ws,
 432                                               RADEON_GPU_RESET_COUNTER);
 433         }
 434
 435         LIST_INITHEAD(&rctx->texture_buffers);
 436
 437         r600_init_context_texture_functions(rctx);
 438         r600_init_viewport_functions(rctx);
 439         r600_streamout_init(rctx);
 440         r600_query_init(rctx);
 441         cayman_init_msaa(&rctx->b);
 442
 443         rctx->allocator_zeroed_memory =
 444                 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
 445                                       0, PIPE_USAGE_DEFAULT, true);
 446         if (!rctx->allocator_zeroed_memory)
 447                 return false;
 448
 449         rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024,
 450                                         PIPE_BIND_INDEX_BUFFER |
 451                                         PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
 452         if (!rctx->uploader)
 453                 return false;
 454
 455         rctx->ctx = rctx->ws->ctx_create(rctx->ws);
 456         if (!rctx->ctx)
 457                 return false;
 458
 459         if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
 460                 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
 461                                                    r600_flush_dma_ring,
 462                                                    rctx);
 463                 rctx->dma.flush = r600_flush_dma_ring;
 464         }
 465
 466         return true;
 467 }
 468
 469 void r600_common_context_cleanup(struct r600_common_context *rctx)
 470 {
 471         unsigned i,j;
 472
 473         /* Release DCC stats. */
 474         for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
 475                 assert(!rctx->dcc_stats[i].query_active);
 476
 477                 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
 478                         if (rctx->dcc_stats[i].ps_stats[j])
 479                                 rctx->b.destroy_query(&rctx->b,
 480                                                       rctx->dcc_stats[i].ps_stats[j]);
 481
 482                 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
 483         }
 484
 485         if (rctx->gfx.cs)
 486                 rctx->ws->cs_destroy(rctx->gfx.cs);
 487         if (rctx->dma.cs)
 488                 rctx->ws->cs_destroy(rctx->dma.cs);
 489         if (rctx->ctx)
 490                 rctx->ws->ctx_destroy(rctx->ctx);
 491
 492         if (rctx->uploader) {
 493                 u_upload_destroy(rctx->uploader);
 494         }
 495
 496         util_slab_destroy(&rctx->pool_transfers);
 497
 498         if (rctx->allocator_zeroed_memory) {
 499                 u_suballocator_destroy(rctx->allocator_zeroed_memory);
 500         }
 501         rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
 502 }
 503
 504 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 505 {
 506         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 507         struct r600_resource *rr = (struct r600_resource *)r;
 508
 509         if (!r) {
 510                 return;
 511         }
 512
 513         /*
 514          * The idea is to compute a gross estimate of memory requirement of
 515          * each draw call. After each draw call, memory will be precisely
 516          * accounted. So the uncertainty is only on the current draw call.
 517          * In practice this gave very good estimate (+/- 10% of the target
 518          * memory limit).
 519          */
 520         if (rr->domains & RADEON_DOMAIN_VRAM)
 521                 rctx->vram += rr->buf->size;
 522         else if (rr->domains & RADEON_DOMAIN_GTT)
 523                 rctx->gtt += rr->buf->size;
 524 }
 525
 526 /*
 527  * pipe_screen
 528  */
 529
 530 static const struct debug_named_value common_debug_options[] = {
 531         /* logging */
 532         { "tex", DBG_TEX, "Print texture info" },
 533         { "compute", DBG_COMPUTE, "Print compute info" },
 534         { "vm", DBG_VM, "Print virtual addresses when creating resources" },
 535         { "info", DBG_INFO, "Print driver information" },
 536
 537         /* shaders */
 538         { "fs", DBG_FS, "Print fetch shaders" },
 539         { "vs", DBG_VS, "Print vertex shaders" },
 540         { "gs", DBG_GS, "Print geometry shaders" },
 541         { "ps", DBG_PS, "Print pixel shaders" },
 542         { "cs", DBG_CS, "Print compute shaders" },
 543         { "tcs", DBG_TCS, "Print tessellation control shaders" },
 544         { "tes", DBG_TES, "Print tessellation evaluation shaders" },
 545         { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
 546         { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
 547         { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
 548         { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
 549
 550         { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
 551
 552         /* features */
 553         { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
 554         { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
 555         /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
 556         { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
 557         { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
 558         { "notiling", DBG_NO_TILING, "Disable tiling" },
 559         { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
 560         { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
 561         { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
 562         { "nowc", DBG_NO_WC, "Disable GTT write combining" },
 563         { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
 564         { "nodcc", DBG_NO_DCC, "Disable DCC." },
 565         { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
 566         { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
 567         { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
 568         { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
 569         { "noce", DBG_NO_CE, "Disable the constant engine"},
 570         { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
 571         { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
 572
 573         DEBUG_NAMED_VALUE_END /* must be last */
 574 };
 575
 576 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 577 {
 578         return "X.Org";
 579 }
 580
 581 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
 582 {
 583         return "AMD";
 584 }
 585
 586 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
 587 {
 588         switch (rscreen->info.family) {
 589         case CHIP_R600: return "AMD R600";
 590         case CHIP_RV610: return "AMD RV610";
 591         case CHIP_RV630: return "AMD RV630";
 592         case CHIP_RV670: return "AMD RV670";
 593         case CHIP_RV620: return "AMD RV620";
 594         case CHIP_RV635: return "AMD RV635";
 595         case CHIP_RS780: return "AMD RS780";
 596         case CHIP_RS880: return "AMD RS880";
 597         case CHIP_RV770: return "AMD RV770";
 598         case CHIP_RV730: return "AMD RV730";
 599         case CHIP_RV710: return "AMD RV710";
 600         case CHIP_RV740: return "AMD RV740";
 601         case CHIP_CEDAR: return "AMD CEDAR";
 602         case CHIP_REDWOOD: return "AMD REDWOOD";
 603         case CHIP_JUNIPER: return "AMD JUNIPER";
 604         case CHIP_CYPRESS: return "AMD CYPRESS";
 605         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 606         case CHIP_PALM: return "AMD PALM";
 607         case CHIP_SUMO: return "AMD SUMO";
 608         case CHIP_SUMO2: return "AMD SUMO2";
 609         case CHIP_BARTS: return "AMD BARTS";
 610         case CHIP_TURKS: return "AMD TURKS";
 611         case CHIP_CAICOS: return "AMD CAICOS";
 612         case CHIP_CAYMAN: return "AMD CAYMAN";
 613         case CHIP_ARUBA: return "AMD ARUBA";
 614         case CHIP_TAHITI: return "AMD TAHITI";
 615         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 616         case CHIP_VERDE: return "AMD CAPE VERDE";
 617         case CHIP_OLAND: return "AMD OLAND";
 618         case CHIP_HAINAN: return "AMD HAINAN";
 619         case CHIP_BONAIRE: return "AMD BONAIRE";
 620         case CHIP_KAVERI: return "AMD KAVERI";
 621         case CHIP_KABINI: return "AMD KABINI";
 622         case CHIP_HAWAII: return "AMD HAWAII";
 623         case CHIP_MULLINS: return "AMD MULLINS";
 624         case CHIP_TONGA: return "AMD TONGA";
 625         case CHIP_ICELAND: return "AMD ICELAND";
 626         case CHIP_CARRIZO: return "AMD CARRIZO";
 627         case CHIP_FIJI: return "AMD FIJI";
 628         case CHIP_POLARIS10: return "AMD POLARIS10";
 629         case CHIP_POLARIS11: return "AMD POLARIS11";
 630         case CHIP_STONEY: return "AMD STONEY";
 631         default: return "AMD unknown";
 632         }
 633 }
 634
 635 static const char* r600_get_name(struct pipe_screen* pscreen)
 636 {
 637         struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
 638
 639         return rscreen->renderer_string;
 640 }
 641
 642 static float r600_get_paramf(struct pipe_screen* pscreen,
 643                              enum pipe_capf param)
 644 {
 645         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 646
 647         switch (param) {
 648         case PIPE_CAPF_MAX_LINE_WIDTH:
 649         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 650         case PIPE_CAPF_MAX_POINT_WIDTH:
 651         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 652                 if (rscreen->family >= CHIP_CEDAR)
 653                         return 16384.0f;
 654                 else
 655                         return 8192.0f;
 656         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 657                 return 16.0f;
 658         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 659                 return 16.0f;
 660         case PIPE_CAPF_GUARD_BAND_LEFT:
 661         case PIPE_CAPF_GUARD_BAND_TOP:
 662         case PIPE_CAPF_GUARD_BAND_RIGHT:
 663         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 664                 return 0.0f;
 665         }
 666         return 0.0f;
 667 }
 668
 669 static int r600_get_video_param(struct pipe_screen *screen,
 670                                 enum pipe_video_profile profile,
 671                                 enum pipe_video_entrypoint entrypoint,
 672                                 enum pipe_video_cap param)
 673 {
 674         switch (param) {
 675         case PIPE_VIDEO_CAP_SUPPORTED:
 676                 return vl_profile_supported(screen, profile, entrypoint);
 677         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 678                 return 1;
 679         case PIPE_VIDEO_CAP_MAX_WIDTH:
 680         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 681                 return vl_video_buffer_max_size(screen);
 682         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 683                 return PIPE_FORMAT_NV12;
 684         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 685                 return false;
 686         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 687                 return false;
 688         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 689                 return true;
 690         case PIPE_VIDEO_CAP_MAX_LEVEL:
 691                 return vl_level_supported(screen, profile);
 692         default:
 693                 return 0;
 694         }
 695 }
 696
 697 const char *r600_get_llvm_processor_name(enum radeon_family family)
 698 {
 699         switch (family) {
 700         case CHIP_R600:
 701         case CHIP_RV630:
 702         case CHIP_RV635:
 703         case CHIP_RV670:
 704                 return "r600";
 705         case CHIP_RV610:
 706         case CHIP_RV620:
 707         case CHIP_RS780:
 708         case CHIP_RS880:
 709                 return "rs880";
 710         case CHIP_RV710:
 711                 return "rv710";
 712         case CHIP_RV730:
 713                 return "rv730";
 714         case CHIP_RV740:
 715         case CHIP_RV770:
 716                 return "rv770";
 717         case CHIP_PALM:
 718         case CHIP_CEDAR:
 719                 return "cedar";
 720         case CHIP_SUMO:
 721         case CHIP_SUMO2:
 722                 return "sumo";
 723         case CHIP_REDWOOD:
 724                 return "redwood";
 725         case CHIP_JUNIPER:
 726                 return "juniper";
 727         case CHIP_HEMLOCK:
 728         case CHIP_CYPRESS:
 729                 return "cypress";
 730         case CHIP_BARTS:
 731                 return "barts";
 732         case CHIP_TURKS:
 733                 return "turks";
 734         case CHIP_CAICOS:
 735                 return "caicos";
 736         case CHIP_CAYMAN:
 737         case CHIP_ARUBA:
 738                 return "cayman";
 739
 740         case CHIP_TAHITI: return "tahiti";
 741         case CHIP_PITCAIRN: return "pitcairn";
 742         case CHIP_VERDE: return "verde";
 743         case CHIP_OLAND: return "oland";
 744         case CHIP_HAINAN: return "hainan";
 745         case CHIP_BONAIRE: return "bonaire";
 746         case CHIP_KABINI: return "kabini";
 747         case CHIP_KAVERI: return "kaveri";
 748         case CHIP_HAWAII: return "hawaii";
 749         case CHIP_MULLINS:
 750                 return "mullins";
 751         case CHIP_TONGA: return "tonga";
 752         case CHIP_ICELAND: return "iceland";
 753         case CHIP_CARRIZO: return "carrizo";
 754 #if HAVE_LLVM <= 0x0307
 755         case CHIP_FIJI: return "tonga";
 756         case CHIP_STONEY: return "carrizo";
 757 #else
 758         case CHIP_FIJI: return "fiji";
 759         case CHIP_STONEY: return "stoney";
 760 #endif
 761 #if HAVE_LLVM <= 0x0308
 762         case CHIP_POLARIS10: return "tonga";
 763         case CHIP_POLARIS11: return "tonga";
 764 #else
 765         case CHIP_POLARIS10: return "polaris10";
 766         case CHIP_POLARIS11: return "polaris11";
 767 #endif
 768         default: return "";
 769         }
 770 }
 771
 772 static int r600_get_compute_param(struct pipe_screen *screen,
 773         enum pipe_shader_ir ir_type,
 774         enum pipe_compute_cap param,
 775         void *ret)
 776 {
 777         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
 778
 779         //TODO: select these params by asic
 780         switch (param) {
 781         case PIPE_COMPUTE_CAP_IR_TARGET: {
 782                 const char *gpu;
 783                 const char *triple;
 784                 if (rscreen->family <= CHIP_ARUBA) {
 785                         triple = "r600--";
 786                 } else {
 787                         triple = "amdgcn--";
 788                 }
 789                 switch(rscreen->family) {
 790                 /* Clang < 3.6 is missing Hainan in its list of
 791                  * GPUs, so we need to use the name of a similar GPU.
 792                  */
 793                 default:
 794                         gpu = r600_get_llvm_processor_name(rscreen->family);
 795                         break;
 796                 }
 797                 if (ret) {
 798                         sprintf(ret, "%s-%s", gpu, triple);
 799                 }
 800                 /* +2 for dash and terminating NIL byte */
 801                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 802         }
 803         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 804                 if (ret) {
 805                         uint64_t *grid_dimension = ret;
 806                         grid_dimension[0] = 3;
 807                 }
 808                 return 1 * sizeof(uint64_t);
 809
 810         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 811                 if (ret) {
 812                         uint64_t *grid_size = ret;
 813                         grid_size[0] = 65535;
 814                         grid_size[1] = 65535;
 815                         grid_size[2] = 65535;
 816                 }
 817                 return 3 * sizeof(uint64_t) ;
 818
 819         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 820                 if (ret) {
 821                         uint64_t *block_size = ret;
 822                         if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
 823                             ir_type == PIPE_SHADER_IR_TGSI) {
 824                                 block_size[0] = 2048;
 825                                 block_size[1] = 2048;
 826                                 block_size[2] = 2048;
 827                         } else {
 828                                 block_size[0] = 256;
 829                                 block_size[1] = 256;
 830                                 block_size[2] = 256;
 831                         }
 832                 }
 833                 return 3 * sizeof(uint64_t);
 834
 835         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 836                 if (ret) {
 837                         uint64_t *max_threads_per_block = ret;
 838                         if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
 839                             ir_type == PIPE_SHADER_IR_TGSI)
 840                                 *max_threads_per_block = 2048;
 841                         else
 842                                 *max_threads_per_block = 256;
 843                 }
 844                 return sizeof(uint64_t);
 845
 846         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 847                 if (ret) {
 848                         uint64_t *max_global_size = ret;
 849                         uint64_t max_mem_alloc_size;
 850
 851                         r600_get_compute_param(screen, ir_type,
 852                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 853                                 &max_mem_alloc_size);
 854
 855                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 856                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 857                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 858                          * make sure we never report more than
 859                          * 4 * MAX_MEM_ALLOC_SIZE.
 860                          */
 861                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 862                                                 MAX2(rscreen->info.gart_size,
 863                                                      rscreen->info.vram_size));
 864                 }
 865                 return sizeof(uint64_t);
 866
 867         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 868                 if (ret) {
 869                         uint64_t *max_local_size = ret;
 870                         /* Value reported by the closed source driver. */
 871                         *max_local_size = 32768;
 872                 }
 873                 return sizeof(uint64_t);
 874
 875         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 876                 if (ret) {
 877                         uint64_t *max_input_size = ret;
 878                         /* Value reported by the closed source driver. */
 879                         *max_input_size = 1024;
 880                 }
 881                 return sizeof(uint64_t);
 882
 883         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 884                 if (ret) {
 885                         uint64_t *max_mem_alloc_size = ret;
 886
 887                         *max_mem_alloc_size = rscreen->info.max_alloc_size;
 888                 }
 889                 return sizeof(uint64_t);
 890
 891         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 892                 if (ret) {
 893                         uint32_t *max_clock_frequency = ret;
 894                         *max_clock_frequency = rscreen->info.max_shader_clock;
 895                 }
 896                 return sizeof(uint32_t);
 897
 898         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 899                 if (ret) {
 900                         uint32_t *max_compute_units = ret;
 901                         *max_compute_units = rscreen->info.num_good_compute_units;
 902                 }
 903                 return sizeof(uint32_t);
 904
 905         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 906                 if (ret) {
 907                         uint32_t *images_supported = ret;
 908                         *images_supported = 0;
 909                 }
 910                 return sizeof(uint32_t);
 911         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 912                 break; /* unused */
 913         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 914                 if (ret) {
 915                         uint32_t *subgroup_size = ret;
 916                         *subgroup_size = r600_wavefront_size(rscreen->family);
 917                 }
 918                 return sizeof(uint32_t);
 919         }
 920
 921         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 922         return 0;
 923 }
 924
 925 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 926 {
 927         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 928
 929         return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
 930                         rscreen->info.clock_crystal_freq;
 931 }
 932
 933 static void r600_fence_reference(struct pipe_screen *screen,
 934                                  struct pipe_fence_handle **dst,
 935                                  struct pipe_fence_handle *src)
 936 {
 937         struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
 938         struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
 939         struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
 940
 941         if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
 942                 ws->fence_reference(&(*rdst)->gfx, NULL);
 943                 ws->fence_reference(&(*rdst)->sdma, NULL);
 944                 FREE(*rdst);
 945         }
 946         *rdst = rsrc;
 947 }
 948
 949 static boolean r600_fence_finish(struct pipe_screen *screen,
 950                                  struct pipe_fence_handle *fence,
 951                                  uint64_t timeout)
 952 {
 953         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 954         struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
 955         int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
 956
 957         if (rfence->sdma) {
 958                 if (!rws->fence_wait(rws, rfence->sdma, timeout))
 959                         return false;
 960
 961                 /* Recompute the timeout after waiting. */
 962                 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
 963                         int64_t time = os_time_get_nano();
 964                         timeout = abs_timeout > time ? abs_timeout - time : 0;
 965                 }
 966         }
 967
 968         if (!rfence->gfx)
 969                 return true;
 970
 971         return rws->fence_wait(rws, rfence->gfx, timeout);
 972 }
 973
 974 static void r600_query_memory_info(struct pipe_screen *screen,
 975                                    struct pipe_memory_info *info)
 976 {
 977         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 978         struct radeon_winsys *ws = rscreen->ws;
 979         unsigned vram_usage, gtt_usage;
 980
 981         info->total_device_memory = rscreen->info.vram_size / 1024;
 982         info->total_staging_memory = rscreen->info.gart_size / 1024;
 983
 984         /* The real TTM memory usage is somewhat random, because:
 985          *
 986          * 1) TTM delays freeing memory, because it can only free it after
 987          *    fences expire.
 988          *
 989          * 2) The memory usage can be really low if big VRAM evictions are
 990          *    taking place, but the real usage is well above the size of VRAM.
 991          *
 992          * Instead, return statistics of this process.
 993          */
 994         vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
 995         gtt_usage =  ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
 996
 997         info->avail_device_memory =
 998                 vram_usage <= info->total_device_memory ?
 999                                 info->total_device_memory - vram_usage : 0;
1000         info->avail_staging_memory =
1001                 gtt_usage <= info->total_staging_memory ?
1002                                 info->total_staging_memory - gtt_usage : 0;
1003
1004         info->device_memory_evicted =
1005                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1006         /* Just return the number of evicted 64KB pages. */
1007         info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1008 }
1009
1010 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1011                                                   const struct pipe_resource *templ)
1012 {
1013         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1014
1015         if (templ->target == PIPE_BUFFER) {
1016                 return r600_buffer_create(screen, templ,
1017                                           rscreen->info.gart_page_size);
1018         } else {
1019                 return r600_texture_create(screen, templ);
1020         }
1021 }
1022
1023 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1024                              struct radeon_winsys *ws)
1025 {
1026         char llvm_string[32] = {}, kernel_version[128] = {};
1027         struct utsname uname_data;
1028
1029         ws->query_info(ws, &rscreen->info);
1030
1031         if (uname(&uname_data) == 0)
1032                 snprintf(kernel_version, sizeof(kernel_version),
1033                          " / %s", uname_data.release);
1034
1035 #if HAVE_LLVM
1036         snprintf(llvm_string, sizeof(llvm_string),
1037                  ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1038                  HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1039 #endif
1040
1041         snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1042                  "%s (DRM %i.%i.%i%s%s)",
1043                  r600_get_chip_name(rscreen), rscreen->info.drm_major,
1044                  rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1045                  kernel_version, llvm_string);
1046
1047         rscreen->b.get_name = r600_get_name;
1048         rscreen->b.get_vendor = r600_get_vendor;
1049         rscreen->b.get_device_vendor = r600_get_device_vendor;
1050         rscreen->b.get_compute_param = r600_get_compute_param;
1051         rscreen->b.get_paramf = r600_get_paramf;
1052         rscreen->b.get_timestamp = r600_get_timestamp;
1053         rscreen->b.fence_finish = r600_fence_finish;
1054         rscreen->b.fence_reference = r600_fence_reference;
1055         rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1056         rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1057         rscreen->b.query_memory_info = r600_query_memory_info;
1058
1059         if (rscreen->info.has_uvd) {
1060                 rscreen->b.get_video_param = rvid_get_video_param;
1061                 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1062         } else {
1063                 rscreen->b.get_video_param = r600_get_video_param;
1064                 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1065         }
1066
1067         r600_init_screen_texture_functions(rscreen);
1068         r600_init_screen_query_functions(rscreen);
1069
1070         rscreen->ws = ws;
1071         rscreen->family = rscreen->info.family;
1072         rscreen->chip_class = rscreen->info.chip_class;
1073         rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1074
1075         rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1076         if (rscreen->force_aniso >= 0) {
1077                 printf("radeon: Forcing anisotropy filter to %ix\n",
1078                        /* round down to a power of two */
1079                        1 << util_logbase2(rscreen->force_aniso));
1080         }
1081
1082         util_format_s3tc_init();
1083         pipe_mutex_init(rscreen->aux_context_lock);
1084         pipe_mutex_init(rscreen->gpu_load_mutex);
1085
1086         if (rscreen->debug_flags & DBG_INFO) {
1087                 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1088                 printf("family = %i (%s)\n", rscreen->info.family,
1089                        r600_get_chip_name(rscreen));
1090                 printf("chip_class = %i\n", rscreen->info.chip_class);
1091                 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1092                 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1093                 printf("max_alloc_size = %i MB\n",
1094                        (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1095                 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1096                 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1097                 printf("has_sdma = %i\n", rscreen->info.has_sdma);
1098                 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1099                 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1100                 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1101                 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1102                 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1103                        rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1104                 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1105
1106                 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1107                 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1108                 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1109                 printf("max_se = %i\n", rscreen->info.max_se);
1110                 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1111
1112                 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1113                 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1114                 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1115                 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1116                 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1117                 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1118         }
1119         return true;
1120 }
1121
1122 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1123 {
1124         r600_perfcounters_destroy(rscreen);
1125         r600_gpu_load_kill_thread(rscreen);
1126
1127         pipe_mutex_destroy(rscreen->gpu_load_mutex);
1128         pipe_mutex_destroy(rscreen->aux_context_lock);
1129         rscreen->aux_context->destroy(rscreen->aux_context);
1130
1131         rscreen->ws->destroy(rscreen->ws);
1132         FREE(rscreen);
1133 }
1134
1135 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1136                           unsigned processor)
1137 {
1138         switch (processor) {
1139         case PIPE_SHADER_VERTEX:
1140                 return (rscreen->debug_flags & DBG_VS) != 0;
1141         case PIPE_SHADER_TESS_CTRL:
1142                 return (rscreen->debug_flags & DBG_TCS) != 0;
1143         case PIPE_SHADER_TESS_EVAL:
1144                 return (rscreen->debug_flags & DBG_TES) != 0;
1145         case PIPE_SHADER_GEOMETRY:
1146                 return (rscreen->debug_flags & DBG_GS) != 0;
1147         case PIPE_SHADER_FRAGMENT:
1148                 return (rscreen->debug_flags & DBG_PS) != 0;
1149         case PIPE_SHADER_COMPUTE:
1150                 return (rscreen->debug_flags & DBG_CS) != 0;
1151         default:
1152                 return false;
1153         }
1154 }
1155
1156 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1157                               uint64_t offset, uint64_t size, unsigned value,
1158                               enum r600_coherency coher)
1159 {
1160         struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1161
1162         pipe_mutex_lock(rscreen->aux_context_lock);
1163         rctx->clear_buffer(&rctx->b, dst, offset, size, value, coher);
1164         rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1165         pipe_mutex_unlock(rscreen->aux_context_lock);
1166 }