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r600,compute: Plug few memory leaks
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40
41 #ifndef HAVE_LLVM
42 #define HAVE_LLVM 0
43 #endif
44
45 struct r600_multi_fence {
46 struct pipe_reference reference;
47 struct pipe_fence_handle *gfx;
48 struct pipe_fence_handle *sdma;
49 };
50
51 /*
52 * shader binary helpers.
53 */
54 void radeon_shader_binary_init(struct radeon_shader_binary *b)
55 {
56 memset(b, 0, sizeof(*b));
57 }
58
59 void radeon_shader_binary_clean(struct radeon_shader_binary *b)
60 {
61 if (!b)
62 return;
63 FREE(b->code);
64 FREE(b->config);
65 FREE(b->rodata);
66 FREE(b->global_symbol_offsets);
67 FREE(b->relocs);
68 FREE(b->disasm_string);
69 }
70
71 /*
72 * pipe_context
73 */
74
75 void r600_draw_rectangle(struct blitter_context *blitter,
76 int x1, int y1, int x2, int y2, float depth,
77 enum blitter_attrib_type type,
78 const union pipe_color_union *attrib)
79 {
80 struct r600_common_context *rctx =
81 (struct r600_common_context*)util_blitter_get_pipe(blitter);
82 struct pipe_viewport_state viewport;
83 struct pipe_resource *buf = NULL;
84 unsigned offset = 0;
85 float *vb;
86
87 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
88 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
89 return;
90 }
91
92 /* Some operations (like color resolve on r6xx) don't work
93 * with the conventional primitive types.
94 * One that works is PT_RECTLIST, which we use here. */
95
96 /* setup viewport */
97 viewport.scale[0] = 1.0f;
98 viewport.scale[1] = 1.0f;
99 viewport.scale[2] = 1.0f;
100 viewport.translate[0] = 0.0f;
101 viewport.translate[1] = 0.0f;
102 viewport.translate[2] = 0.0f;
103 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
104
105 /* Upload vertices. The hw rectangle has only 3 vertices,
106 * I guess the 4th one is derived from the first 3.
107 * The vertex specification should match u_blitter's vertex element state. */
108 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, 256, &offset, &buf, (void**)&vb);
109 if (!buf)
110 return;
111
112 vb[0] = x1;
113 vb[1] = y1;
114 vb[2] = depth;
115 vb[3] = 1;
116
117 vb[8] = x1;
118 vb[9] = y2;
119 vb[10] = depth;
120 vb[11] = 1;
121
122 vb[16] = x2;
123 vb[17] = y1;
124 vb[18] = depth;
125 vb[19] = 1;
126
127 if (attrib) {
128 memcpy(vb+4, attrib->f, sizeof(float)*4);
129 memcpy(vb+12, attrib->f, sizeof(float)*4);
130 memcpy(vb+20, attrib->f, sizeof(float)*4);
131 }
132
133 /* draw */
134 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
135 R600_PRIM_RECTANGLE_LIST, 3, 2);
136 pipe_resource_reference(&buf, NULL);
137 }
138
139 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
140 {
141 /* Flush the GFX IB if it's not empty. */
142 if (ctx->gfx.cs->cdw > ctx->initial_gfx_cs_size)
143 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
144
145 /* Flush if there's not enough space. */
146 if ((num_dw + ctx->dma.cs->cdw) > ctx->dma.cs->max_dw) {
147 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
148 assert((num_dw + ctx->dma.cs->cdw) <= ctx->dma.cs->max_dw);
149 }
150 }
151
152 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
153 {
154 }
155
156 void r600_preflush_suspend_features(struct r600_common_context *ctx)
157 {
158 /* suspend queries */
159 if (ctx->num_cs_dw_nontimer_queries_suspend) {
160 /* Since non-timer queries are suspended during blits,
161 * we have to guard against double-suspends. */
162 r600_suspend_nontimer_queries(ctx);
163 ctx->nontimer_queries_suspended_by_flush = true;
164 }
165 if (!LIST_IS_EMPTY(&ctx->active_timer_queries))
166 r600_suspend_timer_queries(ctx);
167
168 ctx->streamout.suspended = false;
169 if (ctx->streamout.begin_emitted) {
170 r600_emit_streamout_end(ctx);
171 ctx->streamout.suspended = true;
172 }
173 }
174
175 void r600_postflush_resume_features(struct r600_common_context *ctx)
176 {
177 if (ctx->streamout.suspended) {
178 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
179 r600_streamout_buffers_dirty(ctx);
180 }
181
182 /* resume queries */
183 if (!LIST_IS_EMPTY(&ctx->active_timer_queries))
184 r600_resume_timer_queries(ctx);
185 if (ctx->nontimer_queries_suspended_by_flush) {
186 ctx->nontimer_queries_suspended_by_flush = false;
187 r600_resume_nontimer_queries(ctx);
188 }
189 }
190
191 static void r600_flush_from_st(struct pipe_context *ctx,
192 struct pipe_fence_handle **fence,
193 unsigned flags)
194 {
195 struct pipe_screen *screen = ctx->screen;
196 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
197 unsigned rflags = 0;
198 struct pipe_fence_handle *gfx_fence = NULL;
199 struct pipe_fence_handle *sdma_fence = NULL;
200
201 if (flags & PIPE_FLUSH_END_OF_FRAME)
202 rflags |= RADEON_FLUSH_END_OF_FRAME;
203
204 if (rctx->dma.cs) {
205 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
206 }
207 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
208
209 /* Both engines can signal out of order, so we need to keep both fences. */
210 if (gfx_fence || sdma_fence) {
211 struct r600_multi_fence *multi_fence =
212 CALLOC_STRUCT(r600_multi_fence);
213 if (!multi_fence)
214 return;
215
216 multi_fence->reference.count = 1;
217 multi_fence->gfx = gfx_fence;
218 multi_fence->sdma = sdma_fence;
219
220 screen->fence_reference(screen, fence, NULL);
221 *fence = (struct pipe_fence_handle*)multi_fence;
222 }
223 }
224
225 static void r600_flush_dma_ring(void *ctx, unsigned flags,
226 struct pipe_fence_handle **fence)
227 {
228 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
229 struct radeon_winsys_cs *cs = rctx->dma.cs;
230
231 if (cs->cdw)
232 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence, 0);
233 if (fence)
234 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
235 }
236
237 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
238 {
239 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
240 unsigned latest = rctx->ws->query_value(rctx->ws,
241 RADEON_GPU_RESET_COUNTER);
242
243 if (rctx->gpu_reset_counter == latest)
244 return PIPE_NO_RESET;
245
246 rctx->gpu_reset_counter = latest;
247 return PIPE_UNKNOWN_CONTEXT_RESET;
248 }
249
250 static void r600_set_debug_callback(struct pipe_context *ctx,
251 const struct pipe_debug_callback *cb)
252 {
253 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
254
255 if (cb)
256 rctx->debug = *cb;
257 else
258 memset(&rctx->debug, 0, sizeof(rctx->debug));
259 }
260
261 bool r600_common_context_init(struct r600_common_context *rctx,
262 struct r600_common_screen *rscreen)
263 {
264 util_slab_create(&rctx->pool_transfers,
265 sizeof(struct r600_transfer), 64,
266 UTIL_SLAB_SINGLETHREADED);
267
268 rctx->screen = rscreen;
269 rctx->ws = rscreen->ws;
270 rctx->family = rscreen->family;
271 rctx->chip_class = rscreen->chip_class;
272
273 if (rscreen->chip_class >= CIK)
274 rctx->max_db = MAX2(8, rscreen->info.r600_num_backends);
275 else if (rscreen->chip_class >= EVERGREEN)
276 rctx->max_db = 8;
277 else
278 rctx->max_db = 4;
279
280 rctx->b.invalidate_resource = r600_invalidate_resource;
281 rctx->b.transfer_map = u_transfer_map_vtbl;
282 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
283 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
284 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
285 rctx->b.memory_barrier = r600_memory_barrier;
286 rctx->b.flush = r600_flush_from_st;
287 rctx->b.set_debug_callback = r600_set_debug_callback;
288
289 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
290 rctx->b.get_device_reset_status = r600_get_reset_status;
291 rctx->gpu_reset_counter =
292 rctx->ws->query_value(rctx->ws,
293 RADEON_GPU_RESET_COUNTER);
294 }
295
296 LIST_INITHEAD(&rctx->texture_buffers);
297
298 r600_init_context_texture_functions(rctx);
299 r600_streamout_init(rctx);
300 r600_query_init(rctx);
301 cayman_init_msaa(&rctx->b);
302
303 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
304 0, PIPE_USAGE_DEFAULT, TRUE);
305 if (!rctx->allocator_so_filled_size)
306 return false;
307
308 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024,
309 PIPE_BIND_INDEX_BUFFER |
310 PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
311 if (!rctx->uploader)
312 return false;
313
314 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
315 if (!rctx->ctx)
316 return false;
317
318 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
319 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
320 r600_flush_dma_ring,
321 rctx, NULL);
322 rctx->dma.flush = r600_flush_dma_ring;
323 }
324
325 return true;
326 }
327
328 void r600_common_context_cleanup(struct r600_common_context *rctx)
329 {
330 if (rctx->gfx.cs)
331 rctx->ws->cs_destroy(rctx->gfx.cs);
332 if (rctx->dma.cs)
333 rctx->ws->cs_destroy(rctx->dma.cs);
334 if (rctx->ctx)
335 rctx->ws->ctx_destroy(rctx->ctx);
336
337 if (rctx->uploader) {
338 u_upload_destroy(rctx->uploader);
339 }
340
341 util_slab_destroy(&rctx->pool_transfers);
342
343 if (rctx->allocator_so_filled_size) {
344 u_suballocator_destroy(rctx->allocator_so_filled_size);
345 }
346 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
347 }
348
349 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
350 {
351 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
352 struct r600_resource *rr = (struct r600_resource *)r;
353
354 if (!r) {
355 return;
356 }
357
358 /*
359 * The idea is to compute a gross estimate of memory requirement of
360 * each draw call. After each draw call, memory will be precisely
361 * accounted. So the uncertainty is only on the current draw call.
362 * In practice this gave very good estimate (+/- 10% of the target
363 * memory limit).
364 */
365 if (rr->domains & RADEON_DOMAIN_GTT) {
366 rctx->gtt += rr->buf->size;
367 }
368 if (rr->domains & RADEON_DOMAIN_VRAM) {
369 rctx->vram += rr->buf->size;
370 }
371 }
372
373 /*
374 * pipe_screen
375 */
376
377 static const struct debug_named_value common_debug_options[] = {
378 /* logging */
379 { "tex", DBG_TEX, "Print texture info" },
380 { "compute", DBG_COMPUTE, "Print compute info" },
381 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
382 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
383 { "info", DBG_INFO, "Print driver information" },
384
385 /* shaders */
386 { "fs", DBG_FS, "Print fetch shaders" },
387 { "vs", DBG_VS, "Print vertex shaders" },
388 { "gs", DBG_GS, "Print geometry shaders" },
389 { "ps", DBG_PS, "Print pixel shaders" },
390 { "cs", DBG_CS, "Print compute shaders" },
391 { "tcs", DBG_TCS, "Print tessellation control shaders" },
392 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
393 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
394 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
395 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
396
397 /* features */
398 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
399 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
400 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
401 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
402 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
403 { "notiling", DBG_NO_TILING, "Disable tiling" },
404 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
405 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
406 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
407 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
408 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
409 { "nodcc", DBG_NO_DCC, "Disable DCC." },
410 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
411 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
412
413 DEBUG_NAMED_VALUE_END /* must be last */
414 };
415
416 static const char* r600_get_vendor(struct pipe_screen* pscreen)
417 {
418 return "X.Org";
419 }
420
421 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
422 {
423 return "AMD";
424 }
425
426 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
427 {
428 switch (rscreen->info.family) {
429 case CHIP_R600: return "AMD R600";
430 case CHIP_RV610: return "AMD RV610";
431 case CHIP_RV630: return "AMD RV630";
432 case CHIP_RV670: return "AMD RV670";
433 case CHIP_RV620: return "AMD RV620";
434 case CHIP_RV635: return "AMD RV635";
435 case CHIP_RS780: return "AMD RS780";
436 case CHIP_RS880: return "AMD RS880";
437 case CHIP_RV770: return "AMD RV770";
438 case CHIP_RV730: return "AMD RV730";
439 case CHIP_RV710: return "AMD RV710";
440 case CHIP_RV740: return "AMD RV740";
441 case CHIP_CEDAR: return "AMD CEDAR";
442 case CHIP_REDWOOD: return "AMD REDWOOD";
443 case CHIP_JUNIPER: return "AMD JUNIPER";
444 case CHIP_CYPRESS: return "AMD CYPRESS";
445 case CHIP_HEMLOCK: return "AMD HEMLOCK";
446 case CHIP_PALM: return "AMD PALM";
447 case CHIP_SUMO: return "AMD SUMO";
448 case CHIP_SUMO2: return "AMD SUMO2";
449 case CHIP_BARTS: return "AMD BARTS";
450 case CHIP_TURKS: return "AMD TURKS";
451 case CHIP_CAICOS: return "AMD CAICOS";
452 case CHIP_CAYMAN: return "AMD CAYMAN";
453 case CHIP_ARUBA: return "AMD ARUBA";
454 case CHIP_TAHITI: return "AMD TAHITI";
455 case CHIP_PITCAIRN: return "AMD PITCAIRN";
456 case CHIP_VERDE: return "AMD CAPE VERDE";
457 case CHIP_OLAND: return "AMD OLAND";
458 case CHIP_HAINAN: return "AMD HAINAN";
459 case CHIP_BONAIRE: return "AMD BONAIRE";
460 case CHIP_KAVERI: return "AMD KAVERI";
461 case CHIP_KABINI: return "AMD KABINI";
462 case CHIP_HAWAII: return "AMD HAWAII";
463 case CHIP_MULLINS: return "AMD MULLINS";
464 case CHIP_TONGA: return "AMD TONGA";
465 case CHIP_ICELAND: return "AMD ICELAND";
466 case CHIP_CARRIZO: return "AMD CARRIZO";
467 case CHIP_FIJI: return "AMD FIJI";
468 case CHIP_STONEY: return "AMD STONEY";
469 default: return "AMD unknown";
470 }
471 }
472
473 static const char* r600_get_name(struct pipe_screen* pscreen)
474 {
475 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
476
477 return rscreen->renderer_string;
478 }
479
480 static float r600_get_paramf(struct pipe_screen* pscreen,
481 enum pipe_capf param)
482 {
483 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
484
485 switch (param) {
486 case PIPE_CAPF_MAX_LINE_WIDTH:
487 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
488 case PIPE_CAPF_MAX_POINT_WIDTH:
489 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
490 if (rscreen->family >= CHIP_CEDAR)
491 return 16384.0f;
492 else
493 return 8192.0f;
494 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
495 return 16.0f;
496 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
497 return 16.0f;
498 case PIPE_CAPF_GUARD_BAND_LEFT:
499 case PIPE_CAPF_GUARD_BAND_TOP:
500 case PIPE_CAPF_GUARD_BAND_RIGHT:
501 case PIPE_CAPF_GUARD_BAND_BOTTOM:
502 return 0.0f;
503 }
504 return 0.0f;
505 }
506
507 static int r600_get_video_param(struct pipe_screen *screen,
508 enum pipe_video_profile profile,
509 enum pipe_video_entrypoint entrypoint,
510 enum pipe_video_cap param)
511 {
512 switch (param) {
513 case PIPE_VIDEO_CAP_SUPPORTED:
514 return vl_profile_supported(screen, profile, entrypoint);
515 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
516 return 1;
517 case PIPE_VIDEO_CAP_MAX_WIDTH:
518 case PIPE_VIDEO_CAP_MAX_HEIGHT:
519 return vl_video_buffer_max_size(screen);
520 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
521 return PIPE_FORMAT_NV12;
522 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
523 return false;
524 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
525 return false;
526 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
527 return true;
528 case PIPE_VIDEO_CAP_MAX_LEVEL:
529 return vl_level_supported(screen, profile);
530 default:
531 return 0;
532 }
533 }
534
535 const char *r600_get_llvm_processor_name(enum radeon_family family)
536 {
537 switch (family) {
538 case CHIP_R600:
539 case CHIP_RV630:
540 case CHIP_RV635:
541 case CHIP_RV670:
542 return "r600";
543 case CHIP_RV610:
544 case CHIP_RV620:
545 case CHIP_RS780:
546 case CHIP_RS880:
547 return "rs880";
548 case CHIP_RV710:
549 return "rv710";
550 case CHIP_RV730:
551 return "rv730";
552 case CHIP_RV740:
553 case CHIP_RV770:
554 return "rv770";
555 case CHIP_PALM:
556 case CHIP_CEDAR:
557 return "cedar";
558 case CHIP_SUMO:
559 case CHIP_SUMO2:
560 return "sumo";
561 case CHIP_REDWOOD:
562 return "redwood";
563 case CHIP_JUNIPER:
564 return "juniper";
565 case CHIP_HEMLOCK:
566 case CHIP_CYPRESS:
567 return "cypress";
568 case CHIP_BARTS:
569 return "barts";
570 case CHIP_TURKS:
571 return "turks";
572 case CHIP_CAICOS:
573 return "caicos";
574 case CHIP_CAYMAN:
575 case CHIP_ARUBA:
576 return "cayman";
577
578 case CHIP_TAHITI: return "tahiti";
579 case CHIP_PITCAIRN: return "pitcairn";
580 case CHIP_VERDE: return "verde";
581 case CHIP_OLAND: return "oland";
582 case CHIP_HAINAN: return "hainan";
583 case CHIP_BONAIRE: return "bonaire";
584 case CHIP_KABINI: return "kabini";
585 case CHIP_KAVERI: return "kaveri";
586 case CHIP_HAWAII: return "hawaii";
587 case CHIP_MULLINS:
588 return "mullins";
589 case CHIP_TONGA: return "tonga";
590 case CHIP_ICELAND: return "iceland";
591 case CHIP_CARRIZO: return "carrizo";
592 #if HAVE_LLVM <= 0x0307
593 case CHIP_FIJI: return "tonga";
594 case CHIP_STONEY: return "carrizo";
595 #else
596 case CHIP_FIJI: return "fiji";
597 case CHIP_STONEY: return "stoney";
598 #endif
599 default: return "";
600 }
601 }
602
603 static int r600_get_compute_param(struct pipe_screen *screen,
604 enum pipe_compute_cap param,
605 void *ret)
606 {
607 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
608
609 //TODO: select these params by asic
610 switch (param) {
611 case PIPE_COMPUTE_CAP_IR_TARGET: {
612 const char *gpu;
613 const char *triple;
614 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
615 triple = "r600--";
616 } else {
617 triple = "amdgcn--";
618 }
619 switch(rscreen->family) {
620 /* Clang < 3.6 is missing Hainan in its list of
621 * GPUs, so we need to use the name of a similar GPU.
622 */
623 #if HAVE_LLVM < 0x0306
624 case CHIP_HAINAN:
625 gpu = "oland";
626 break;
627 #endif
628 default:
629 gpu = r600_get_llvm_processor_name(rscreen->family);
630 break;
631 }
632 if (ret) {
633 sprintf(ret, "%s-%s", gpu, triple);
634 }
635 /* +2 for dash and terminating NIL byte */
636 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
637 }
638 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
639 if (ret) {
640 uint64_t *grid_dimension = ret;
641 grid_dimension[0] = 3;
642 }
643 return 1 * sizeof(uint64_t);
644
645 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
646 if (ret) {
647 uint64_t *grid_size = ret;
648 grid_size[0] = 65535;
649 grid_size[1] = 65535;
650 grid_size[2] = 1;
651 }
652 return 3 * sizeof(uint64_t) ;
653
654 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
655 if (ret) {
656 uint64_t *block_size = ret;
657 block_size[0] = 256;
658 block_size[1] = 256;
659 block_size[2] = 256;
660 }
661 return 3 * sizeof(uint64_t);
662
663 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
664 if (ret) {
665 uint64_t *max_threads_per_block = ret;
666 *max_threads_per_block = 256;
667 }
668 return sizeof(uint64_t);
669
670 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
671 if (ret) {
672 uint64_t *max_global_size = ret;
673 uint64_t max_mem_alloc_size;
674
675 r600_get_compute_param(screen,
676 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
677 &max_mem_alloc_size);
678
679 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
680 * 1/4 of the MAX_GLOBAL_SIZE. Since the
681 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
682 * make sure we never report more than
683 * 4 * MAX_MEM_ALLOC_SIZE.
684 */
685 *max_global_size = MIN2(4 * max_mem_alloc_size,
686 rscreen->info.gart_size +
687 rscreen->info.vram_size);
688 }
689 return sizeof(uint64_t);
690
691 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
692 if (ret) {
693 uint64_t *max_local_size = ret;
694 /* Value reported by the closed source driver. */
695 *max_local_size = 32768;
696 }
697 return sizeof(uint64_t);
698
699 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
700 if (ret) {
701 uint64_t *max_input_size = ret;
702 /* Value reported by the closed source driver. */
703 *max_input_size = 1024;
704 }
705 return sizeof(uint64_t);
706
707 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
708 if (ret) {
709 uint64_t *max_mem_alloc_size = ret;
710
711 /* XXX: The limit in older kernels is 256 MB. We
712 * should add a query here for newer kernels.
713 */
714 *max_mem_alloc_size = 256 * 1024 * 1024;
715 }
716 return sizeof(uint64_t);
717
718 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
719 if (ret) {
720 uint32_t *max_clock_frequency = ret;
721 *max_clock_frequency = rscreen->info.max_sclk;
722 }
723 return sizeof(uint32_t);
724
725 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
726 if (ret) {
727 uint32_t *max_compute_units = ret;
728 *max_compute_units = rscreen->info.num_good_compute_units;
729 }
730 return sizeof(uint32_t);
731
732 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
733 if (ret) {
734 uint32_t *images_supported = ret;
735 *images_supported = 0;
736 }
737 return sizeof(uint32_t);
738 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
739 break; /* unused */
740 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
741 if (ret) {
742 uint32_t *subgroup_size = ret;
743 *subgroup_size = r600_wavefront_size(rscreen->family);
744 }
745 return sizeof(uint32_t);
746 }
747
748 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
749 return 0;
750 }
751
752 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
753 {
754 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
755
756 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
757 rscreen->info.r600_clock_crystal_freq;
758 }
759
760 static void r600_fence_reference(struct pipe_screen *screen,
761 struct pipe_fence_handle **dst,
762 struct pipe_fence_handle *src)
763 {
764 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
765 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
766 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
767
768 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
769 ws->fence_reference(&(*rdst)->gfx, NULL);
770 ws->fence_reference(&(*rdst)->sdma, NULL);
771 FREE(*rdst);
772 }
773 *rdst = rsrc;
774 }
775
776 static boolean r600_fence_finish(struct pipe_screen *screen,
777 struct pipe_fence_handle *fence,
778 uint64_t timeout)
779 {
780 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
781 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
782 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
783
784 if (rfence->sdma) {
785 if (!rws->fence_wait(rws, rfence->sdma, timeout))
786 return false;
787
788 /* Recompute the timeout after waiting. */
789 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
790 int64_t time = os_time_get_nano();
791 timeout = abs_timeout > time ? abs_timeout - time : 0;
792 }
793 }
794
795 if (!rfence->gfx)
796 return true;
797
798 return rws->fence_wait(rws, rfence->gfx, timeout);
799 }
800
801 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
802 uint32_t tiling_config)
803 {
804 switch ((tiling_config & 0xe) >> 1) {
805 case 0:
806 rscreen->tiling_info.num_channels = 1;
807 break;
808 case 1:
809 rscreen->tiling_info.num_channels = 2;
810 break;
811 case 2:
812 rscreen->tiling_info.num_channels = 4;
813 break;
814 case 3:
815 rscreen->tiling_info.num_channels = 8;
816 break;
817 default:
818 return false;
819 }
820
821 switch ((tiling_config & 0x30) >> 4) {
822 case 0:
823 rscreen->tiling_info.num_banks = 4;
824 break;
825 case 1:
826 rscreen->tiling_info.num_banks = 8;
827 break;
828 default:
829 return false;
830
831 }
832 switch ((tiling_config & 0xc0) >> 6) {
833 case 0:
834 rscreen->tiling_info.group_bytes = 256;
835 break;
836 case 1:
837 rscreen->tiling_info.group_bytes = 512;
838 break;
839 default:
840 return false;
841 }
842 return true;
843 }
844
845 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
846 uint32_t tiling_config)
847 {
848 switch (tiling_config & 0xf) {
849 case 0:
850 rscreen->tiling_info.num_channels = 1;
851 break;
852 case 1:
853 rscreen->tiling_info.num_channels = 2;
854 break;
855 case 2:
856 rscreen->tiling_info.num_channels = 4;
857 break;
858 case 3:
859 rscreen->tiling_info.num_channels = 8;
860 break;
861 default:
862 return false;
863 }
864
865 switch ((tiling_config & 0xf0) >> 4) {
866 case 0:
867 rscreen->tiling_info.num_banks = 4;
868 break;
869 case 1:
870 rscreen->tiling_info.num_banks = 8;
871 break;
872 case 2:
873 rscreen->tiling_info.num_banks = 16;
874 break;
875 default:
876 return false;
877 }
878
879 switch ((tiling_config & 0xf00) >> 8) {
880 case 0:
881 rscreen->tiling_info.group_bytes = 256;
882 break;
883 case 1:
884 rscreen->tiling_info.group_bytes = 512;
885 break;
886 default:
887 return false;
888 }
889 return true;
890 }
891
892 static bool r600_init_tiling(struct r600_common_screen *rscreen)
893 {
894 uint32_t tiling_config = rscreen->info.r600_tiling_config;
895
896 /* set default group bytes, overridden by tiling info ioctl */
897 if (rscreen->chip_class <= R700) {
898 rscreen->tiling_info.group_bytes = 256;
899 } else {
900 rscreen->tiling_info.group_bytes = 512;
901 }
902
903 if (!tiling_config)
904 return true;
905
906 if (rscreen->chip_class <= R700) {
907 return r600_interpret_tiling(rscreen, tiling_config);
908 } else {
909 return evergreen_interpret_tiling(rscreen, tiling_config);
910 }
911 }
912
913 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
914 const struct pipe_resource *templ)
915 {
916 if (templ->target == PIPE_BUFFER) {
917 return r600_buffer_create(screen, templ, 4096);
918 } else {
919 return r600_texture_create(screen, templ);
920 }
921 }
922
923 bool r600_common_screen_init(struct r600_common_screen *rscreen,
924 struct radeon_winsys *ws)
925 {
926 char llvm_string[32] = {};
927
928 ws->query_info(ws, &rscreen->info);
929
930 #if HAVE_LLVM
931 snprintf(llvm_string, sizeof(llvm_string),
932 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
933 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
934 #endif
935
936 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
937 "%s (DRM %i.%i.%i%s)",
938 r600_get_chip_name(rscreen), rscreen->info.drm_major,
939 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
940 llvm_string);
941
942 rscreen->b.get_name = r600_get_name;
943 rscreen->b.get_vendor = r600_get_vendor;
944 rscreen->b.get_device_vendor = r600_get_device_vendor;
945 rscreen->b.get_compute_param = r600_get_compute_param;
946 rscreen->b.get_paramf = r600_get_paramf;
947 rscreen->b.get_timestamp = r600_get_timestamp;
948 rscreen->b.fence_finish = r600_fence_finish;
949 rscreen->b.fence_reference = r600_fence_reference;
950 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
951 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
952
953 if (rscreen->info.has_uvd) {
954 rscreen->b.get_video_param = rvid_get_video_param;
955 rscreen->b.is_video_format_supported = rvid_is_format_supported;
956 } else {
957 rscreen->b.get_video_param = r600_get_video_param;
958 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
959 }
960
961 r600_init_screen_texture_functions(rscreen);
962 r600_init_screen_query_functions(rscreen);
963
964 rscreen->ws = ws;
965 rscreen->family = rscreen->info.family;
966 rscreen->chip_class = rscreen->info.chip_class;
967 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
968
969 if (!r600_init_tiling(rscreen)) {
970 return false;
971 }
972 util_format_s3tc_init();
973 pipe_mutex_init(rscreen->aux_context_lock);
974 pipe_mutex_init(rscreen->gpu_load_mutex);
975
976 if (((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 28) ||
977 rscreen->info.drm_major == 3) &&
978 (rscreen->debug_flags & DBG_TRACE_CS)) {
979 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
980 PIPE_BIND_CUSTOM,
981 PIPE_USAGE_STAGING,
982 4096);
983 if (rscreen->trace_bo) {
984 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->buf, NULL,
985 PIPE_TRANSFER_UNSYNCHRONIZED);
986 }
987 }
988
989 if (rscreen->debug_flags & DBG_INFO) {
990 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
991 printf("family = %i\n", rscreen->info.family);
992 printf("chip_class = %i\n", rscreen->info.chip_class);
993 printf("gart_size = %i MB\n", (int)(rscreen->info.gart_size >> 20));
994 printf("vram_size = %i MB\n", (int)(rscreen->info.vram_size >> 20));
995 printf("max_sclk = %i\n", rscreen->info.max_sclk);
996 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
997 printf("max_se = %i\n", rscreen->info.max_se);
998 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
999 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1000 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1001 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1002 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1003 printf("r600_num_backends = %i\n", rscreen->info.r600_num_backends);
1004 printf("r600_clock_crystal_freq = %i\n", rscreen->info.r600_clock_crystal_freq);
1005 printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
1006 printf("r600_num_tile_pipes = %i\n", rscreen->info.r600_num_tile_pipes);
1007 printf("r600_max_pipes = %i\n", rscreen->info.r600_max_pipes);
1008 printf("r600_virtual_address = %i\n", rscreen->info.r600_virtual_address);
1009 printf("r600_has_dma = %i\n", rscreen->info.r600_has_dma);
1010 printf("r600_backend_map = %i\n", rscreen->info.r600_backend_map);
1011 printf("r600_backend_map_valid = %i\n", rscreen->info.r600_backend_map_valid);
1012 printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
1013 printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
1014 }
1015 return true;
1016 }
1017
1018 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1019 {
1020 r600_perfcounters_destroy(rscreen);
1021 r600_gpu_load_kill_thread(rscreen);
1022
1023 pipe_mutex_destroy(rscreen->gpu_load_mutex);
1024 pipe_mutex_destroy(rscreen->aux_context_lock);
1025 rscreen->aux_context->destroy(rscreen->aux_context);
1026
1027 if (rscreen->trace_bo)
1028 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
1029
1030 rscreen->ws->destroy(rscreen->ws);
1031 FREE(rscreen);
1032 }
1033
1034 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1035 unsigned processor)
1036 {
1037 switch (processor) {
1038 case TGSI_PROCESSOR_VERTEX:
1039 return (rscreen->debug_flags & DBG_VS) != 0;
1040 case TGSI_PROCESSOR_TESS_CTRL:
1041 return (rscreen->debug_flags & DBG_TCS) != 0;
1042 case TGSI_PROCESSOR_TESS_EVAL:
1043 return (rscreen->debug_flags & DBG_TES) != 0;
1044 case TGSI_PROCESSOR_GEOMETRY:
1045 return (rscreen->debug_flags & DBG_GS) != 0;
1046 case TGSI_PROCESSOR_FRAGMENT:
1047 return (rscreen->debug_flags & DBG_PS) != 0;
1048 case TGSI_PROCESSOR_COMPUTE:
1049 return (rscreen->debug_flags & DBG_CS) != 0;
1050 default:
1051 return false;
1052 }
1053 }
1054
1055 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1056 unsigned offset, unsigned size, unsigned value,
1057 bool is_framebuffer)
1058 {
1059 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1060
1061 pipe_mutex_lock(rscreen->aux_context_lock);
1062 rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
1063 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1064 pipe_mutex_unlock(rscreen->aux_context_lock);
1065 }