2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
27 #include "r600_pipe_common.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
40 #include <sys/utsname.h>
42 #include <llvm-c/TargetMachine.h>
45 struct r600_multi_fence
{
46 struct pipe_reference reference
;
47 struct pipe_fence_handle
*gfx
;
48 struct pipe_fence_handle
*sdma
;
50 /* If the context wasn't flushed at fence creation, this is non-NULL. */
52 struct r600_common_context
*ctx
;
58 * shader binary helpers.
60 void si_radeon_shader_binary_init(struct ac_shader_binary
*b
)
62 memset(b
, 0, sizeof(*b
));
65 void si_radeon_shader_binary_clean(struct ac_shader_binary
*b
)
72 FREE(b
->global_symbol_offsets
);
74 FREE(b
->disasm_string
);
75 FREE(b
->llvm_ir_string
);
85 * \param event EVENT_TYPE_*
86 * \param event_flags Optional cache flush flags (TC)
87 * \param data_sel 1 = fence, 3 = timestamp
89 * \param va GPU address
90 * \param old_value Previous fence value (for a bug workaround)
91 * \param new_value Fence value to write for this event.
93 void si_gfx_write_event_eop(struct r600_common_context
*ctx
,
94 unsigned event
, unsigned event_flags
,
96 struct r600_resource
*buf
, uint64_t va
,
97 uint32_t new_fence
, unsigned query_type
)
99 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
100 unsigned op
= EVENT_TYPE(event
) |
103 unsigned sel
= EOP_DATA_SEL(data_sel
);
105 /* Wait for write confirmation before writing data, but don't send
107 if (ctx
->chip_class
>= SI
&& data_sel
!= EOP_DATA_SEL_DISCARD
)
108 sel
|= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM
);
110 if (ctx
->chip_class
>= GFX9
) {
111 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
112 * counters) must immediately precede every timestamp event to
113 * prevent a GPU hang on GFX9.
115 * Occlusion queries don't need to do it here, because they
116 * always do ZPASS_DONE before the timestamp.
118 if (ctx
->chip_class
== GFX9
&&
119 query_type
!= PIPE_QUERY_OCCLUSION_COUNTER
&&
120 query_type
!= PIPE_QUERY_OCCLUSION_PREDICATE
&&
121 query_type
!= PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
) {
122 struct r600_resource
*scratch
= ctx
->eop_bug_scratch
;
124 assert(16 * ctx
->screen
->info
.num_render_backends
<=
125 scratch
->b
.b
.width0
);
126 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
127 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE
) | EVENT_INDEX(1));
128 radeon_emit(cs
, scratch
->gpu_address
);
129 radeon_emit(cs
, scratch
->gpu_address
>> 32);
131 radeon_add_to_buffer_list(ctx
, &ctx
->gfx
, scratch
,
132 RADEON_USAGE_WRITE
, RADEON_PRIO_QUERY
);
135 radeon_emit(cs
, PKT3(PKT3_RELEASE_MEM
, 6, 0));
137 radeon_emit(cs
, sel
);
138 radeon_emit(cs
, va
); /* address lo */
139 radeon_emit(cs
, va
>> 32); /* address hi */
140 radeon_emit(cs
, new_fence
); /* immediate data lo */
141 radeon_emit(cs
, 0); /* immediate data hi */
142 radeon_emit(cs
, 0); /* unused */
144 if (ctx
->chip_class
== CIK
||
145 ctx
->chip_class
== VI
) {
146 struct r600_resource
*scratch
= ctx
->eop_bug_scratch
;
147 uint64_t va
= scratch
->gpu_address
;
149 /* Two EOP events are required to make all engines go idle
150 * (and optional cache flushes executed) before the timestamp
153 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0));
156 radeon_emit(cs
, ((va
>> 32) & 0xffff) | sel
);
157 radeon_emit(cs
, 0); /* immediate data */
158 radeon_emit(cs
, 0); /* unused */
160 radeon_add_to_buffer_list(ctx
, &ctx
->gfx
, scratch
,
161 RADEON_USAGE_WRITE
, RADEON_PRIO_QUERY
);
164 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0));
167 radeon_emit(cs
, ((va
>> 32) & 0xffff) | sel
);
168 radeon_emit(cs
, new_fence
); /* immediate data */
169 radeon_emit(cs
, 0); /* unused */
173 r600_emit_reloc(ctx
, &ctx
->gfx
, buf
, RADEON_USAGE_WRITE
,
177 unsigned si_gfx_write_fence_dwords(struct r600_common_screen
*screen
)
181 if (screen
->chip_class
== CIK
||
182 screen
->chip_class
== VI
)
185 if (!screen
->info
.has_virtual_memory
)
191 void si_gfx_wait_fence(struct r600_common_context
*ctx
,
192 uint64_t va
, uint32_t ref
, uint32_t mask
)
194 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
196 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
197 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
| WAIT_REG_MEM_MEM_SPACE(1));
199 radeon_emit(cs
, va
>> 32);
200 radeon_emit(cs
, ref
); /* reference value */
201 radeon_emit(cs
, mask
); /* mask */
202 radeon_emit(cs
, 4); /* poll interval */
205 void si_draw_rectangle(struct blitter_context
*blitter
,
206 int x1
, int y1
, int x2
, int y2
,
207 float depth
, unsigned num_instances
,
208 enum blitter_attrib_type type
,
209 const union blitter_attrib
*attrib
)
211 struct r600_common_context
*rctx
=
212 (struct r600_common_context
*)util_blitter_get_pipe(blitter
);
213 struct pipe_viewport_state viewport
;
214 struct pipe_resource
*buf
= NULL
;
218 /* Some operations (like color resolve on r6xx) don't work
219 * with the conventional primitive types.
220 * One that works is PT_RECTLIST, which we use here. */
223 viewport
.scale
[0] = 1.0f
;
224 viewport
.scale
[1] = 1.0f
;
225 viewport
.scale
[2] = 1.0f
;
226 viewport
.translate
[0] = 0.0f
;
227 viewport
.translate
[1] = 0.0f
;
228 viewport
.translate
[2] = 0.0f
;
229 rctx
->b
.set_viewport_states(&rctx
->b
, 0, 1, &viewport
);
231 /* Upload vertices. The hw rectangle has only 3 vertices,
232 * The 4th one is derived from the first 3.
233 * The vertex specification should match u_blitter's vertex element state. */
234 u_upload_alloc(rctx
->b
.stream_uploader
, 0, sizeof(float) * 24,
235 rctx
->screen
->info
.tcc_cache_line_size
,
236 &offset
, &buf
, (void**)&vb
);
256 case UTIL_BLITTER_ATTRIB_COLOR
:
257 memcpy(vb
+4, attrib
->color
, sizeof(float)*4);
258 memcpy(vb
+12, attrib
->color
, sizeof(float)*4);
259 memcpy(vb
+20, attrib
->color
, sizeof(float)*4);
261 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW
:
262 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY
:
263 vb
[6] = vb
[14] = vb
[22] = attrib
->texcoord
.z
;
264 vb
[7] = vb
[15] = vb
[23] = attrib
->texcoord
.w
;
266 vb
[4] = attrib
->texcoord
.x1
;
267 vb
[5] = attrib
->texcoord
.y1
;
268 vb
[12] = attrib
->texcoord
.x1
;
269 vb
[13] = attrib
->texcoord
.y2
;
270 vb
[20] = attrib
->texcoord
.x2
;
271 vb
[21] = attrib
->texcoord
.y1
;
273 default:; /* Nothing to do. */
277 struct pipe_vertex_buffer vbuffer
= {};
278 vbuffer
.buffer
.resource
= buf
;
279 vbuffer
.stride
= 2 * 4 * sizeof(float); /* vertex size */
280 vbuffer
.buffer_offset
= offset
;
282 rctx
->b
.set_vertex_buffers(&rctx
->b
, blitter
->vb_slot
, 1, &vbuffer
);
283 util_draw_arrays_instanced(&rctx
->b
, R600_PRIM_RECTANGLE_LIST
, 0, 3,
285 pipe_resource_reference(&buf
, NULL
);
288 static void r600_dma_emit_wait_idle(struct r600_common_context
*rctx
)
290 struct radeon_winsys_cs
*cs
= rctx
->dma
.cs
;
292 /* NOP waits for idle on Evergreen and later. */
293 if (rctx
->chip_class
>= CIK
)
294 radeon_emit(cs
, 0x00000000); /* NOP */
295 else if (rctx
->chip_class
>= EVERGREEN
)
296 radeon_emit(cs
, 0xf0000000); /* NOP */
298 /* TODO: R600-R700 should use the FENCE packet.
299 * CS checker support is required. */
303 void si_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
,
304 struct r600_resource
*dst
, struct r600_resource
*src
)
306 uint64_t vram
= ctx
->dma
.cs
->used_vram
;
307 uint64_t gtt
= ctx
->dma
.cs
->used_gart
;
310 vram
+= dst
->vram_usage
;
311 gtt
+= dst
->gart_usage
;
314 vram
+= src
->vram_usage
;
315 gtt
+= src
->gart_usage
;
318 /* Flush the GFX IB if DMA depends on it. */
319 if (radeon_emitted(ctx
->gfx
.cs
, ctx
->initial_gfx_cs_size
) &&
321 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
, dst
->buf
,
322 RADEON_USAGE_READWRITE
)) ||
324 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
, src
->buf
,
325 RADEON_USAGE_WRITE
))))
326 ctx
->gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
328 /* Flush if there's not enough space, or if the memory usage per IB
331 * IBs using too little memory are limited by the IB submission overhead.
332 * IBs using too much memory are limited by the kernel/TTM overhead.
333 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
335 * This heuristic makes sure that DMA requests are executed
336 * very soon after the call is made and lowers memory usage.
337 * It improves texture upload performance by keeping the DMA
338 * engine busy while uploads are being submitted.
340 num_dw
++; /* for emit_wait_idle below */
341 if (!ctx
->ws
->cs_check_space(ctx
->dma
.cs
, num_dw
) ||
342 ctx
->dma
.cs
->used_vram
+ ctx
->dma
.cs
->used_gart
> 64 * 1024 * 1024 ||
343 !radeon_cs_memory_below_limit(ctx
->screen
, ctx
->dma
.cs
, vram
, gtt
)) {
344 ctx
->dma
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
345 assert((num_dw
+ ctx
->dma
.cs
->current
.cdw
) <= ctx
->dma
.cs
->current
.max_dw
);
348 /* Wait for idle if either buffer has been used in the IB before to
349 * prevent read-after-write hazards.
352 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma
.cs
, dst
->buf
,
353 RADEON_USAGE_READWRITE
)) ||
355 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma
.cs
, src
->buf
,
356 RADEON_USAGE_WRITE
)))
357 r600_dma_emit_wait_idle(ctx
);
359 /* If GPUVM is not supported, the CS checker needs 2 entries
360 * in the buffer list per packet, which has to be done manually.
362 if (ctx
->screen
->info
.has_virtual_memory
) {
364 radeon_add_to_buffer_list(ctx
, &ctx
->dma
, dst
,
366 RADEON_PRIO_SDMA_BUFFER
);
368 radeon_add_to_buffer_list(ctx
, &ctx
->dma
, src
,
370 RADEON_PRIO_SDMA_BUFFER
);
373 /* this function is called before all DMA calls, so increment this. */
374 ctx
->num_dma_calls
++;
377 static void r600_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
381 void si_preflush_suspend_features(struct r600_common_context
*ctx
)
383 /* suspend queries */
384 if (!LIST_IS_EMPTY(&ctx
->active_queries
))
385 si_suspend_queries(ctx
);
387 ctx
->streamout
.suspended
= false;
388 if (ctx
->streamout
.begin_emitted
) {
389 si_emit_streamout_end(ctx
);
390 ctx
->streamout
.suspended
= true;
394 void si_postflush_resume_features(struct r600_common_context
*ctx
)
396 if (ctx
->streamout
.suspended
) {
397 ctx
->streamout
.append_bitmask
= ctx
->streamout
.enabled_mask
;
398 si_streamout_buffers_dirty(ctx
);
402 if (!LIST_IS_EMPTY(&ctx
->active_queries
))
403 si_resume_queries(ctx
);
406 static void r600_add_fence_dependency(struct r600_common_context
*rctx
,
407 struct pipe_fence_handle
*fence
)
409 struct radeon_winsys
*ws
= rctx
->ws
;
412 ws
->cs_add_fence_dependency(rctx
->dma
.cs
, fence
);
413 ws
->cs_add_fence_dependency(rctx
->gfx
.cs
, fence
);
416 static void r600_fence_server_sync(struct pipe_context
*ctx
,
417 struct pipe_fence_handle
*fence
)
419 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
420 struct r600_multi_fence
*rfence
= (struct r600_multi_fence
*)fence
;
422 /* Only amdgpu needs to handle fence dependencies (for fence imports).
423 * radeon synchronizes all rings by default and will not implement
426 if (rctx
->screen
->info
.drm_major
== 2)
429 /* Only imported fences need to be handled by fence_server_sync,
430 * because the winsys handles synchronizations automatically for BOs
431 * within the process.
433 * Simply skip unflushed fences here, and the winsys will drop no-op
434 * dependencies (i.e. dependencies within the same ring).
436 if (rfence
->gfx_unflushed
.ctx
)
439 /* All unflushed commands will not start execution before
440 * this fence dependency is signalled.
442 * Should we flush the context to allow more GPU parallelism?
445 r600_add_fence_dependency(rctx
, rfence
->sdma
);
447 r600_add_fence_dependency(rctx
, rfence
->gfx
);
450 static void r600_flush_from_st(struct pipe_context
*ctx
,
451 struct pipe_fence_handle
**fence
,
454 struct pipe_screen
*screen
= ctx
->screen
;
455 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
456 struct radeon_winsys
*ws
= rctx
->ws
;
457 struct pipe_fence_handle
*gfx_fence
= NULL
;
458 struct pipe_fence_handle
*sdma_fence
= NULL
;
459 bool deferred_fence
= false;
460 unsigned rflags
= RADEON_FLUSH_ASYNC
;
462 if (flags
& PIPE_FLUSH_END_OF_FRAME
)
463 rflags
|= RADEON_FLUSH_END_OF_FRAME
;
465 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
467 rctx
->dma
.flush(rctx
, rflags
, fence
? &sdma_fence
: NULL
);
469 if (!radeon_emitted(rctx
->gfx
.cs
, rctx
->initial_gfx_cs_size
)) {
471 ws
->fence_reference(&gfx_fence
, rctx
->last_gfx_fence
);
472 if (!(flags
& PIPE_FLUSH_DEFERRED
))
473 ws
->cs_sync_flush(rctx
->gfx
.cs
);
475 /* Instead of flushing, create a deferred fence. Constraints:
476 * - The state tracker must allow a deferred flush.
477 * - The state tracker must request a fence.
478 * Thread safety in fence_finish must be ensured by the state tracker.
480 if (flags
& PIPE_FLUSH_DEFERRED
&& fence
) {
481 gfx_fence
= rctx
->ws
->cs_get_next_fence(rctx
->gfx
.cs
);
482 deferred_fence
= true;
484 rctx
->gfx
.flush(rctx
, rflags
, fence
? &gfx_fence
: NULL
);
488 /* Both engines can signal out of order, so we need to keep both fences. */
490 struct r600_multi_fence
*multi_fence
=
491 CALLOC_STRUCT(r600_multi_fence
);
493 ws
->fence_reference(&sdma_fence
, NULL
);
494 ws
->fence_reference(&gfx_fence
, NULL
);
498 multi_fence
->reference
.count
= 1;
499 /* If both fences are NULL, fence_finish will always return true. */
500 multi_fence
->gfx
= gfx_fence
;
501 multi_fence
->sdma
= sdma_fence
;
503 if (deferred_fence
) {
504 multi_fence
->gfx_unflushed
.ctx
= rctx
;
505 multi_fence
->gfx_unflushed
.ib_index
= rctx
->num_gfx_cs_flushes
;
508 screen
->fence_reference(screen
, fence
, NULL
);
509 *fence
= (struct pipe_fence_handle
*)multi_fence
;
512 if (!(flags
& PIPE_FLUSH_DEFERRED
)) {
514 ws
->cs_sync_flush(rctx
->dma
.cs
);
515 ws
->cs_sync_flush(rctx
->gfx
.cs
);
519 static void r600_flush_dma_ring(void *ctx
, unsigned flags
,
520 struct pipe_fence_handle
**fence
)
522 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
523 struct radeon_winsys_cs
*cs
= rctx
->dma
.cs
;
524 struct radeon_saved_cs saved
;
526 (rctx
->screen
->debug_flags
& DBG_CHECK_VM
) &&
527 rctx
->check_vm_faults
;
529 if (!radeon_emitted(cs
, 0)) {
531 rctx
->ws
->fence_reference(fence
, rctx
->last_sdma_fence
);
536 si_save_cs(rctx
->ws
, cs
, &saved
, true);
538 rctx
->ws
->cs_flush(cs
, flags
, &rctx
->last_sdma_fence
);
540 rctx
->ws
->fence_reference(fence
, rctx
->last_sdma_fence
);
543 /* Use conservative timeout 800ms, after which we won't wait any
544 * longer and assume the GPU is hung.
546 rctx
->ws
->fence_wait(rctx
->ws
, rctx
->last_sdma_fence
, 800*1000*1000);
548 rctx
->check_vm_faults(rctx
, &saved
, RING_DMA
);
549 si_clear_saved_cs(&saved
);
554 * Store a linearized copy of all chunks of \p cs together with the buffer
557 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_winsys_cs
*cs
,
558 struct radeon_saved_cs
*saved
, bool get_buffer_list
)
563 /* Save the IB chunks. */
564 saved
->num_dw
= cs
->prev_dw
+ cs
->current
.cdw
;
565 saved
->ib
= MALLOC(4 * saved
->num_dw
);
570 for (i
= 0; i
< cs
->num_prev
; ++i
) {
571 memcpy(buf
, cs
->prev
[i
].buf
, cs
->prev
[i
].cdw
* 4);
572 buf
+= cs
->prev
[i
].cdw
;
574 memcpy(buf
, cs
->current
.buf
, cs
->current
.cdw
* 4);
576 if (!get_buffer_list
)
579 /* Save the buffer list. */
580 saved
->bo_count
= ws
->cs_get_buffer_list(cs
, NULL
);
581 saved
->bo_list
= CALLOC(saved
->bo_count
,
582 sizeof(saved
->bo_list
[0]));
583 if (!saved
->bo_list
) {
587 ws
->cs_get_buffer_list(cs
, saved
->bo_list
);
592 fprintf(stderr
, "%s: out of memory\n", __func__
);
593 memset(saved
, 0, sizeof(*saved
));
596 void si_clear_saved_cs(struct radeon_saved_cs
*saved
)
599 FREE(saved
->bo_list
);
601 memset(saved
, 0, sizeof(*saved
));
604 static enum pipe_reset_status
r600_get_reset_status(struct pipe_context
*ctx
)
606 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
607 unsigned latest
= rctx
->ws
->query_value(rctx
->ws
,
608 RADEON_GPU_RESET_COUNTER
);
610 if (rctx
->gpu_reset_counter
== latest
)
611 return PIPE_NO_RESET
;
613 rctx
->gpu_reset_counter
= latest
;
614 return PIPE_UNKNOWN_CONTEXT_RESET
;
617 static void r600_set_debug_callback(struct pipe_context
*ctx
,
618 const struct pipe_debug_callback
*cb
)
620 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
625 memset(&rctx
->debug
, 0, sizeof(rctx
->debug
));
628 static void r600_set_device_reset_callback(struct pipe_context
*ctx
,
629 const struct pipe_device_reset_callback
*cb
)
631 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
634 rctx
->device_reset_callback
= *cb
;
636 memset(&rctx
->device_reset_callback
, 0,
637 sizeof(rctx
->device_reset_callback
));
640 bool si_check_device_reset(struct r600_common_context
*rctx
)
642 enum pipe_reset_status status
;
644 if (!rctx
->device_reset_callback
.reset
)
647 if (!rctx
->b
.get_device_reset_status
)
650 status
= rctx
->b
.get_device_reset_status(&rctx
->b
);
651 if (status
== PIPE_NO_RESET
)
654 rctx
->device_reset_callback
.reset(rctx
->device_reset_callback
.data
, status
);
658 static void r600_dma_clear_buffer_fallback(struct pipe_context
*ctx
,
659 struct pipe_resource
*dst
,
660 uint64_t offset
, uint64_t size
,
663 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
665 rctx
->clear_buffer(ctx
, dst
, offset
, size
, value
, R600_COHERENCY_NONE
);
668 static bool r600_resource_commit(struct pipe_context
*pctx
,
669 struct pipe_resource
*resource
,
670 unsigned level
, struct pipe_box
*box
,
673 struct r600_common_context
*ctx
= (struct r600_common_context
*)pctx
;
674 struct r600_resource
*res
= r600_resource(resource
);
677 * Since buffer commitment changes cannot be pipelined, we need to
678 * (a) flush any pending commands that refer to the buffer we're about
680 * (b) wait for threaded submit to finish, including those that were
681 * triggered by some other, earlier operation.
683 if (radeon_emitted(ctx
->gfx
.cs
, ctx
->initial_gfx_cs_size
) &&
684 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
,
685 res
->buf
, RADEON_USAGE_READWRITE
)) {
686 ctx
->gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
688 if (radeon_emitted(ctx
->dma
.cs
, 0) &&
689 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma
.cs
,
690 res
->buf
, RADEON_USAGE_READWRITE
)) {
691 ctx
->dma
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
694 ctx
->ws
->cs_sync_flush(ctx
->dma
.cs
);
695 ctx
->ws
->cs_sync_flush(ctx
->gfx
.cs
);
697 assert(resource
->target
== PIPE_BUFFER
);
699 return ctx
->ws
->buffer_commit(res
->buf
, box
->x
, box
->width
, commit
);
702 bool si_common_context_init(struct r600_common_context
*rctx
,
703 struct r600_common_screen
*rscreen
,
704 unsigned context_flags
)
706 slab_create_child(&rctx
->pool_transfers
, &rscreen
->pool_transfers
);
707 slab_create_child(&rctx
->pool_transfers_unsync
, &rscreen
->pool_transfers
);
709 rctx
->screen
= rscreen
;
710 rctx
->ws
= rscreen
->ws
;
711 rctx
->family
= rscreen
->family
;
712 rctx
->chip_class
= rscreen
->chip_class
;
714 rctx
->b
.invalidate_resource
= si_invalidate_resource
;
715 rctx
->b
.resource_commit
= r600_resource_commit
;
716 rctx
->b
.transfer_map
= u_transfer_map_vtbl
;
717 rctx
->b
.transfer_flush_region
= u_transfer_flush_region_vtbl
;
718 rctx
->b
.transfer_unmap
= u_transfer_unmap_vtbl
;
719 rctx
->b
.texture_subdata
= u_default_texture_subdata
;
720 rctx
->b
.memory_barrier
= r600_memory_barrier
;
721 rctx
->b
.flush
= r600_flush_from_st
;
722 rctx
->b
.set_debug_callback
= r600_set_debug_callback
;
723 rctx
->b
.fence_server_sync
= r600_fence_server_sync
;
724 rctx
->dma_clear_buffer
= r600_dma_clear_buffer_fallback
;
725 rctx
->b
.buffer_subdata
= si_buffer_subdata
;
727 /* Set a reasonable default to avoid a performance regression in r600
728 * on stable branches. */
729 rctx
->current_rast_prim
= PIPE_PRIM_TRIANGLES
;
731 if (rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
>= 43) {
732 rctx
->b
.get_device_reset_status
= r600_get_reset_status
;
733 rctx
->gpu_reset_counter
=
734 rctx
->ws
->query_value(rctx
->ws
,
735 RADEON_GPU_RESET_COUNTER
);
738 rctx
->b
.set_device_reset_callback
= r600_set_device_reset_callback
;
740 si_init_context_texture_functions(rctx
);
741 si_init_viewport_functions(rctx
);
742 si_streamout_init(rctx
);
743 si_init_query_functions(rctx
);
744 si_init_msaa(&rctx
->b
);
746 if (rctx
->chip_class
== CIK
||
747 rctx
->chip_class
== VI
||
748 rctx
->chip_class
== GFX9
) {
749 rctx
->eop_bug_scratch
= (struct r600_resource
*)
750 pipe_buffer_create(&rscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
751 16 * rscreen
->info
.num_render_backends
);
752 if (!rctx
->eop_bug_scratch
)
756 rctx
->allocator_zeroed_memory
=
757 u_suballocator_create(&rctx
->b
, rscreen
->info
.gart_page_size
,
758 0, PIPE_USAGE_DEFAULT
, 0, true);
759 if (!rctx
->allocator_zeroed_memory
)
762 rctx
->b
.stream_uploader
= u_upload_create(&rctx
->b
, 1024 * 1024,
763 0, PIPE_USAGE_STREAM
);
764 if (!rctx
->b
.stream_uploader
)
767 rctx
->b
.const_uploader
= u_upload_create(&rctx
->b
, 128 * 1024,
768 0, PIPE_USAGE_DEFAULT
);
769 if (!rctx
->b
.const_uploader
)
772 rctx
->ctx
= rctx
->ws
->ctx_create(rctx
->ws
);
776 if (rscreen
->info
.num_sdma_rings
&& !(rscreen
->debug_flags
& DBG_NO_ASYNC_DMA
)) {
777 rctx
->dma
.cs
= rctx
->ws
->cs_create(rctx
->ctx
, RING_DMA
,
780 rctx
->dma
.flush
= r600_flush_dma_ring
;
786 void si_common_context_cleanup(struct r600_common_context
*rctx
)
790 /* Release DCC stats. */
791 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
792 assert(!rctx
->dcc_stats
[i
].query_active
);
794 for (j
= 0; j
< ARRAY_SIZE(rctx
->dcc_stats
[i
].ps_stats
); j
++)
795 if (rctx
->dcc_stats
[i
].ps_stats
[j
])
796 rctx
->b
.destroy_query(&rctx
->b
,
797 rctx
->dcc_stats
[i
].ps_stats
[j
]);
799 r600_texture_reference(&rctx
->dcc_stats
[i
].tex
, NULL
);
802 if (rctx
->query_result_shader
)
803 rctx
->b
.delete_compute_state(&rctx
->b
, rctx
->query_result_shader
);
806 rctx
->ws
->cs_destroy(rctx
->gfx
.cs
);
808 rctx
->ws
->cs_destroy(rctx
->dma
.cs
);
810 rctx
->ws
->ctx_destroy(rctx
->ctx
);
812 if (rctx
->b
.stream_uploader
)
813 u_upload_destroy(rctx
->b
.stream_uploader
);
814 if (rctx
->b
.const_uploader
)
815 u_upload_destroy(rctx
->b
.const_uploader
);
817 slab_destroy_child(&rctx
->pool_transfers
);
818 slab_destroy_child(&rctx
->pool_transfers_unsync
);
820 if (rctx
->allocator_zeroed_memory
) {
821 u_suballocator_destroy(rctx
->allocator_zeroed_memory
);
823 rctx
->ws
->fence_reference(&rctx
->last_gfx_fence
, NULL
);
824 rctx
->ws
->fence_reference(&rctx
->last_sdma_fence
, NULL
);
825 r600_resource_reference(&rctx
->eop_bug_scratch
, NULL
);
832 static const struct debug_named_value common_debug_options
[] = {
834 { "tex", DBG_TEX
, "Print texture info" },
835 { "nir", DBG_NIR
, "Enable experimental NIR shaders" },
836 { "compute", DBG_COMPUTE
, "Print compute info" },
837 { "vm", DBG_VM
, "Print virtual addresses when creating resources" },
838 { "info", DBG_INFO
, "Print driver information" },
841 { "fs", DBG_FS
, "Print fetch shaders" },
842 { "vs", DBG_VS
, "Print vertex shaders" },
843 { "gs", DBG_GS
, "Print geometry shaders" },
844 { "ps", DBG_PS
, "Print pixel shaders" },
845 { "cs", DBG_CS
, "Print compute shaders" },
846 { "tcs", DBG_TCS
, "Print tessellation control shaders" },
847 { "tes", DBG_TES
, "Print tessellation evaluation shaders" },
848 { "noir", DBG_NO_IR
, "Don't print the LLVM IR"},
849 { "notgsi", DBG_NO_TGSI
, "Don't print the TGSI"},
850 { "noasm", DBG_NO_ASM
, "Don't print disassembled shaders"},
851 { "preoptir", DBG_PREOPT_IR
, "Print the LLVM IR before initial optimizations" },
852 { "checkir", DBG_CHECK_IR
, "Enable additional sanity checks on shader IR" },
853 { "nooptvariant", DBG_NO_OPT_VARIANT
, "Disable compiling optimized shader variants." },
855 { "testdma", DBG_TEST_DMA
, "Invoke SDMA tests and exit." },
856 { "testvmfaultcp", DBG_TEST_VMFAULT_CP
, "Invoke a CP VM fault test and exit." },
857 { "testvmfaultsdma", DBG_TEST_VMFAULT_SDMA
, "Invoke a SDMA VM fault test and exit." },
858 { "testvmfaultshader", DBG_TEST_VMFAULT_SHADER
, "Invoke a shader VM fault test and exit." },
861 { "nodma", DBG_NO_ASYNC_DMA
, "Disable asynchronous DMA" },
862 { "nohyperz", DBG_NO_HYPERZ
, "Disable Hyper-Z" },
863 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
864 { "noinvalrange", DBG_NO_DISCARD_RANGE
, "Disable handling of INVALIDATE_RANGE map flags" },
865 { "no2d", DBG_NO_2D_TILING
, "Disable 2D tiling" },
866 { "notiling", DBG_NO_TILING
, "Disable tiling" },
867 { "switch_on_eop", DBG_SWITCH_ON_EOP
, "Program WD/IA to switch on end-of-packet." },
868 { "forcedma", DBG_FORCE_DMA
, "Use asynchronous DMA for all operations when possible." },
869 { "precompile", DBG_PRECOMPILE
, "Compile one shader variant at shader creation." },
870 { "nowc", DBG_NO_WC
, "Disable GTT write combining" },
871 { "check_vm", DBG_CHECK_VM
, "Check VM faults and dump debug info." },
872 { "nodcc", DBG_NO_DCC
, "Disable DCC." },
873 { "nodccclear", DBG_NO_DCC_CLEAR
, "Disable DCC fast clear." },
874 { "norbplus", DBG_NO_RB_PLUS
, "Disable RB+." },
875 { "sisched", DBG_SI_SCHED
, "Enable LLVM SI Machine Instruction Scheduler." },
876 { "mono", DBG_MONOLITHIC_SHADERS
, "Use old-style monolithic shaders compiled on demand" },
877 { "unsafemath", DBG_UNSAFE_MATH
, "Enable unsafe math shader optimizations" },
878 { "nodccfb", DBG_NO_DCC_FB
, "Disable separate DCC on the main framebuffer" },
879 { "nodpbb", DBG_NO_DPBB
, "Disable DPBB." },
880 { "nodfsm", DBG_NO_DFSM
, "Disable DFSM." },
881 { "nooutoforder", DBG_NO_OUT_OF_ORDER
, "Disable out-of-order rasterization" },
883 DEBUG_NAMED_VALUE_END
/* must be last */
886 static const char* r600_get_vendor(struct pipe_screen
* pscreen
)
891 static const char* r600_get_device_vendor(struct pipe_screen
* pscreen
)
896 static const char *r600_get_marketing_name(struct radeon_winsys
*ws
)
898 if (!ws
->get_chip_name
)
900 return ws
->get_chip_name(ws
);
903 static const char *r600_get_family_name(const struct r600_common_screen
*rscreen
)
905 switch (rscreen
->info
.family
) {
906 case CHIP_R600
: return "AMD R600";
907 case CHIP_RV610
: return "AMD RV610";
908 case CHIP_RV630
: return "AMD RV630";
909 case CHIP_RV670
: return "AMD RV670";
910 case CHIP_RV620
: return "AMD RV620";
911 case CHIP_RV635
: return "AMD RV635";
912 case CHIP_RS780
: return "AMD RS780";
913 case CHIP_RS880
: return "AMD RS880";
914 case CHIP_RV770
: return "AMD RV770";
915 case CHIP_RV730
: return "AMD RV730";
916 case CHIP_RV710
: return "AMD RV710";
917 case CHIP_RV740
: return "AMD RV740";
918 case CHIP_CEDAR
: return "AMD CEDAR";
919 case CHIP_REDWOOD
: return "AMD REDWOOD";
920 case CHIP_JUNIPER
: return "AMD JUNIPER";
921 case CHIP_CYPRESS
: return "AMD CYPRESS";
922 case CHIP_HEMLOCK
: return "AMD HEMLOCK";
923 case CHIP_PALM
: return "AMD PALM";
924 case CHIP_SUMO
: return "AMD SUMO";
925 case CHIP_SUMO2
: return "AMD SUMO2";
926 case CHIP_BARTS
: return "AMD BARTS";
927 case CHIP_TURKS
: return "AMD TURKS";
928 case CHIP_CAICOS
: return "AMD CAICOS";
929 case CHIP_CAYMAN
: return "AMD CAYMAN";
930 case CHIP_ARUBA
: return "AMD ARUBA";
931 case CHIP_TAHITI
: return "AMD TAHITI";
932 case CHIP_PITCAIRN
: return "AMD PITCAIRN";
933 case CHIP_VERDE
: return "AMD CAPE VERDE";
934 case CHIP_OLAND
: return "AMD OLAND";
935 case CHIP_HAINAN
: return "AMD HAINAN";
936 case CHIP_BONAIRE
: return "AMD BONAIRE";
937 case CHIP_KAVERI
: return "AMD KAVERI";
938 case CHIP_KABINI
: return "AMD KABINI";
939 case CHIP_HAWAII
: return "AMD HAWAII";
940 case CHIP_MULLINS
: return "AMD MULLINS";
941 case CHIP_TONGA
: return "AMD TONGA";
942 case CHIP_ICELAND
: return "AMD ICELAND";
943 case CHIP_CARRIZO
: return "AMD CARRIZO";
944 case CHIP_FIJI
: return "AMD FIJI";
945 case CHIP_POLARIS10
: return "AMD POLARIS10";
946 case CHIP_POLARIS11
: return "AMD POLARIS11";
947 case CHIP_POLARIS12
: return "AMD POLARIS12";
948 case CHIP_STONEY
: return "AMD STONEY";
949 case CHIP_VEGA10
: return "AMD VEGA10";
950 case CHIP_RAVEN
: return "AMD RAVEN";
951 default: return "AMD unknown";
955 static void r600_disk_cache_create(struct r600_common_screen
*rscreen
)
957 /* Don't use the cache if shader dumping is enabled. */
958 if (rscreen
->debug_flags
& DBG_ALL_SHADERS
)
961 uint32_t mesa_timestamp
;
962 if (disk_cache_get_function_timestamp(r600_disk_cache_create
,
966 uint32_t llvm_timestamp
;
968 if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo
,
970 res
= asprintf(×tamp_str
, "%u_%u",
971 mesa_timestamp
, llvm_timestamp
);
975 /* These flags affect shader compilation. */
976 uint64_t shader_debug_flags
=
977 rscreen
->debug_flags
&
978 (DBG_FS_CORRECT_DERIVS_AFTER_KILL
|
982 rscreen
->disk_shader_cache
=
983 disk_cache_create(r600_get_family_name(rscreen
),
991 static struct disk_cache
*r600_get_disk_shader_cache(struct pipe_screen
*pscreen
)
993 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
994 return rscreen
->disk_shader_cache
;
997 static const char* r600_get_name(struct pipe_screen
* pscreen
)
999 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
1001 return rscreen
->renderer_string
;
1004 static float r600_get_paramf(struct pipe_screen
* pscreen
,
1005 enum pipe_capf param
)
1007 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
1010 case PIPE_CAPF_MAX_LINE_WIDTH
:
1011 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
1012 case PIPE_CAPF_MAX_POINT_WIDTH
:
1013 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
1014 if (rscreen
->family
>= CHIP_CEDAR
)
1018 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
1020 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
1022 case PIPE_CAPF_GUARD_BAND_LEFT
:
1023 case PIPE_CAPF_GUARD_BAND_TOP
:
1024 case PIPE_CAPF_GUARD_BAND_RIGHT
:
1025 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
1031 static int r600_get_video_param(struct pipe_screen
*screen
,
1032 enum pipe_video_profile profile
,
1033 enum pipe_video_entrypoint entrypoint
,
1034 enum pipe_video_cap param
)
1037 case PIPE_VIDEO_CAP_SUPPORTED
:
1038 return vl_profile_supported(screen
, profile
, entrypoint
);
1039 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
1041 case PIPE_VIDEO_CAP_MAX_WIDTH
:
1042 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
1043 return vl_video_buffer_max_size(screen
);
1044 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
1045 return PIPE_FORMAT_NV12
;
1046 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
1048 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
1050 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
1052 case PIPE_VIDEO_CAP_MAX_LEVEL
:
1053 return vl_level_supported(screen
, profile
);
1059 const char *si_get_llvm_processor_name(enum radeon_family family
)
1102 case CHIP_TAHITI
: return "tahiti";
1103 case CHIP_PITCAIRN
: return "pitcairn";
1104 case CHIP_VERDE
: return "verde";
1105 case CHIP_OLAND
: return "oland";
1106 case CHIP_HAINAN
: return "hainan";
1107 case CHIP_BONAIRE
: return "bonaire";
1108 case CHIP_KABINI
: return "kabini";
1109 case CHIP_KAVERI
: return "kaveri";
1110 case CHIP_HAWAII
: return "hawaii";
1113 case CHIP_TONGA
: return "tonga";
1114 case CHIP_ICELAND
: return "iceland";
1115 case CHIP_CARRIZO
: return "carrizo";
1120 case CHIP_POLARIS10
:
1122 case CHIP_POLARIS11
:
1123 case CHIP_POLARIS12
: /* same as polaris11 */
1133 static unsigned get_max_threads_per_block(struct r600_common_screen
*screen
,
1134 enum pipe_shader_ir ir_type
)
1136 if (ir_type
!= PIPE_SHADER_IR_TGSI
)
1139 /* Only 16 waves per thread-group on gfx9. */
1140 if (screen
->chip_class
>= GFX9
)
1143 /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
1149 static int r600_get_compute_param(struct pipe_screen
*screen
,
1150 enum pipe_shader_ir ir_type
,
1151 enum pipe_compute_cap param
,
1154 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1156 //TODO: select these params by asic
1158 case PIPE_COMPUTE_CAP_IR_TARGET
: {
1161 if (rscreen
->family
<= CHIP_ARUBA
) {
1164 if (HAVE_LLVM
< 0x0400) {
1165 triple
= "amdgcn--";
1167 triple
= "amdgcn-mesa-mesa3d";
1170 switch(rscreen
->family
) {
1171 /* Clang < 3.6 is missing Hainan in its list of
1172 * GPUs, so we need to use the name of a similar GPU.
1175 gpu
= si_get_llvm_processor_name(rscreen
->family
);
1179 sprintf(ret
, "%s-%s", gpu
, triple
);
1181 /* +2 for dash and terminating NIL byte */
1182 return (strlen(triple
) + strlen(gpu
) + 2) * sizeof(char);
1184 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
1186 uint64_t *grid_dimension
= ret
;
1187 grid_dimension
[0] = 3;
1189 return 1 * sizeof(uint64_t);
1191 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
1193 uint64_t *grid_size
= ret
;
1194 grid_size
[0] = 65535;
1195 grid_size
[1] = 65535;
1196 grid_size
[2] = 65535;
1198 return 3 * sizeof(uint64_t) ;
1200 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
1202 uint64_t *block_size
= ret
;
1203 unsigned threads_per_block
= get_max_threads_per_block(rscreen
, ir_type
);
1204 block_size
[0] = threads_per_block
;
1205 block_size
[1] = threads_per_block
;
1206 block_size
[2] = threads_per_block
;
1208 return 3 * sizeof(uint64_t);
1210 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
1212 uint64_t *max_threads_per_block
= ret
;
1213 *max_threads_per_block
= get_max_threads_per_block(rscreen
, ir_type
);
1215 return sizeof(uint64_t);
1216 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
1218 uint32_t *address_bits
= ret
;
1219 address_bits
[0] = 64;
1221 return 1 * sizeof(uint32_t);
1223 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
1225 uint64_t *max_global_size
= ret
;
1226 uint64_t max_mem_alloc_size
;
1228 r600_get_compute_param(screen
, ir_type
,
1229 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
1230 &max_mem_alloc_size
);
1232 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1233 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1234 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1235 * make sure we never report more than
1236 * 4 * MAX_MEM_ALLOC_SIZE.
1238 *max_global_size
= MIN2(4 * max_mem_alloc_size
,
1239 MAX2(rscreen
->info
.gart_size
,
1240 rscreen
->info
.vram_size
));
1242 return sizeof(uint64_t);
1244 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
1246 uint64_t *max_local_size
= ret
;
1247 /* Value reported by the closed source driver. */
1248 *max_local_size
= 32768;
1250 return sizeof(uint64_t);
1252 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
1254 uint64_t *max_input_size
= ret
;
1255 /* Value reported by the closed source driver. */
1256 *max_input_size
= 1024;
1258 return sizeof(uint64_t);
1260 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
1262 uint64_t *max_mem_alloc_size
= ret
;
1264 *max_mem_alloc_size
= rscreen
->info
.max_alloc_size
;
1266 return sizeof(uint64_t);
1268 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
1270 uint32_t *max_clock_frequency
= ret
;
1271 *max_clock_frequency
= rscreen
->info
.max_shader_clock
;
1273 return sizeof(uint32_t);
1275 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
1277 uint32_t *max_compute_units
= ret
;
1278 *max_compute_units
= rscreen
->info
.num_good_compute_units
;
1280 return sizeof(uint32_t);
1282 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
1284 uint32_t *images_supported
= ret
;
1285 *images_supported
= 0;
1287 return sizeof(uint32_t);
1288 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
1290 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
1292 uint32_t *subgroup_size
= ret
;
1293 *subgroup_size
= r600_wavefront_size(rscreen
->family
);
1295 return sizeof(uint32_t);
1296 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
1298 uint64_t *max_variable_threads_per_block
= ret
;
1299 if (ir_type
== PIPE_SHADER_IR_TGSI
)
1300 *max_variable_threads_per_block
= SI_MAX_VARIABLE_THREADS_PER_BLOCK
;
1302 *max_variable_threads_per_block
= 0;
1304 return sizeof(uint64_t);
1307 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
1311 static uint64_t r600_get_timestamp(struct pipe_screen
*screen
)
1313 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1315 return 1000000 * rscreen
->ws
->query_value(rscreen
->ws
, RADEON_TIMESTAMP
) /
1316 rscreen
->info
.clock_crystal_freq
;
1319 static void r600_fence_reference(struct pipe_screen
*screen
,
1320 struct pipe_fence_handle
**dst
,
1321 struct pipe_fence_handle
*src
)
1323 struct radeon_winsys
*ws
= ((struct r600_common_screen
*)screen
)->ws
;
1324 struct r600_multi_fence
**rdst
= (struct r600_multi_fence
**)dst
;
1325 struct r600_multi_fence
*rsrc
= (struct r600_multi_fence
*)src
;
1327 if (pipe_reference(&(*rdst
)->reference
, &rsrc
->reference
)) {
1328 ws
->fence_reference(&(*rdst
)->gfx
, NULL
);
1329 ws
->fence_reference(&(*rdst
)->sdma
, NULL
);
1335 static boolean
r600_fence_finish(struct pipe_screen
*screen
,
1336 struct pipe_context
*ctx
,
1337 struct pipe_fence_handle
*fence
,
1340 struct radeon_winsys
*rws
= ((struct r600_common_screen
*)screen
)->ws
;
1341 struct r600_multi_fence
*rfence
= (struct r600_multi_fence
*)fence
;
1342 struct r600_common_context
*rctx
;
1343 int64_t abs_timeout
= os_time_get_absolute_timeout(timeout
);
1345 ctx
= threaded_context_unwrap_sync(ctx
);
1346 rctx
= ctx
? (struct r600_common_context
*)ctx
: NULL
;
1349 if (!rws
->fence_wait(rws
, rfence
->sdma
, timeout
))
1352 /* Recompute the timeout after waiting. */
1353 if (timeout
&& timeout
!= PIPE_TIMEOUT_INFINITE
) {
1354 int64_t time
= os_time_get_nano();
1355 timeout
= abs_timeout
> time
? abs_timeout
- time
: 0;
1362 /* Flush the gfx IB if it hasn't been flushed yet. */
1364 rfence
->gfx_unflushed
.ctx
== rctx
&&
1365 rfence
->gfx_unflushed
.ib_index
== rctx
->num_gfx_cs_flushes
) {
1366 rctx
->gfx
.flush(rctx
, timeout
? 0 : RADEON_FLUSH_ASYNC
, NULL
);
1367 rfence
->gfx_unflushed
.ctx
= NULL
;
1372 /* Recompute the timeout after all that. */
1373 if (timeout
&& timeout
!= PIPE_TIMEOUT_INFINITE
) {
1374 int64_t time
= os_time_get_nano();
1375 timeout
= abs_timeout
> time
? abs_timeout
- time
: 0;
1379 return rws
->fence_wait(rws
, rfence
->gfx
, timeout
);
1382 static void r600_query_memory_info(struct pipe_screen
*screen
,
1383 struct pipe_memory_info
*info
)
1385 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1386 struct radeon_winsys
*ws
= rscreen
->ws
;
1387 unsigned vram_usage
, gtt_usage
;
1389 info
->total_device_memory
= rscreen
->info
.vram_size
/ 1024;
1390 info
->total_staging_memory
= rscreen
->info
.gart_size
/ 1024;
1392 /* The real TTM memory usage is somewhat random, because:
1394 * 1) TTM delays freeing memory, because it can only free it after
1397 * 2) The memory usage can be really low if big VRAM evictions are
1398 * taking place, but the real usage is well above the size of VRAM.
1400 * Instead, return statistics of this process.
1402 vram_usage
= ws
->query_value(ws
, RADEON_REQUESTED_VRAM_MEMORY
) / 1024;
1403 gtt_usage
= ws
->query_value(ws
, RADEON_REQUESTED_GTT_MEMORY
) / 1024;
1405 info
->avail_device_memory
=
1406 vram_usage
<= info
->total_device_memory
?
1407 info
->total_device_memory
- vram_usage
: 0;
1408 info
->avail_staging_memory
=
1409 gtt_usage
<= info
->total_staging_memory
?
1410 info
->total_staging_memory
- gtt_usage
: 0;
1412 info
->device_memory_evicted
=
1413 ws
->query_value(ws
, RADEON_NUM_BYTES_MOVED
) / 1024;
1415 if (rscreen
->info
.drm_major
== 3 && rscreen
->info
.drm_minor
>= 4)
1416 info
->nr_device_memory_evictions
=
1417 ws
->query_value(ws
, RADEON_NUM_EVICTIONS
);
1419 /* Just return the number of evicted 64KB pages. */
1420 info
->nr_device_memory_evictions
= info
->device_memory_evicted
/ 64;
1423 struct pipe_resource
*si_resource_create_common(struct pipe_screen
*screen
,
1424 const struct pipe_resource
*templ
)
1426 if (templ
->target
== PIPE_BUFFER
) {
1427 return si_buffer_create(screen
, templ
, 256);
1429 return si_texture_create(screen
, templ
);
1433 bool si_common_screen_init(struct r600_common_screen
*rscreen
,
1434 struct radeon_winsys
*ws
)
1436 char family_name
[32] = {}, llvm_string
[32] = {}, kernel_version
[128] = {};
1437 struct utsname uname_data
;
1438 const char *chip_name
;
1440 ws
->query_info(ws
, &rscreen
->info
);
1443 if ((chip_name
= r600_get_marketing_name(ws
)))
1444 snprintf(family_name
, sizeof(family_name
), "%s / ",
1445 r600_get_family_name(rscreen
) + 4);
1447 chip_name
= r600_get_family_name(rscreen
);
1449 if (uname(&uname_data
) == 0)
1450 snprintf(kernel_version
, sizeof(kernel_version
),
1451 " / %s", uname_data
.release
);
1453 if (HAVE_LLVM
> 0) {
1454 snprintf(llvm_string
, sizeof(llvm_string
),
1455 ", LLVM %i.%i.%i", (HAVE_LLVM
>> 8) & 0xff,
1456 HAVE_LLVM
& 0xff, MESA_LLVM_VERSION_PATCH
);
1459 snprintf(rscreen
->renderer_string
, sizeof(rscreen
->renderer_string
),
1460 "%s (%sDRM %i.%i.%i%s%s)",
1461 chip_name
, family_name
, rscreen
->info
.drm_major
,
1462 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
,
1463 kernel_version
, llvm_string
);
1465 rscreen
->b
.get_name
= r600_get_name
;
1466 rscreen
->b
.get_vendor
= r600_get_vendor
;
1467 rscreen
->b
.get_device_vendor
= r600_get_device_vendor
;
1468 rscreen
->b
.get_disk_shader_cache
= r600_get_disk_shader_cache
;
1469 rscreen
->b
.get_compute_param
= r600_get_compute_param
;
1470 rscreen
->b
.get_paramf
= r600_get_paramf
;
1471 rscreen
->b
.get_timestamp
= r600_get_timestamp
;
1472 rscreen
->b
.fence_finish
= r600_fence_finish
;
1473 rscreen
->b
.fence_reference
= r600_fence_reference
;
1474 rscreen
->b
.resource_destroy
= u_resource_destroy_vtbl
;
1475 rscreen
->b
.resource_from_user_memory
= si_buffer_from_user_memory
;
1476 rscreen
->b
.query_memory_info
= r600_query_memory_info
;
1478 if (rscreen
->info
.has_hw_decode
) {
1479 rscreen
->b
.get_video_param
= si_vid_get_video_param
;
1480 rscreen
->b
.is_video_format_supported
= si_vid_is_format_supported
;
1482 rscreen
->b
.get_video_param
= r600_get_video_param
;
1483 rscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
1486 si_init_screen_texture_functions(rscreen
);
1487 si_init_screen_query_functions(rscreen
);
1489 rscreen
->family
= rscreen
->info
.family
;
1490 rscreen
->chip_class
= rscreen
->info
.chip_class
;
1491 rscreen
->debug_flags
|= debug_get_flags_option("R600_DEBUG", common_debug_options
, 0);
1492 rscreen
->has_rbplus
= false;
1493 rscreen
->rbplus_allowed
= false;
1495 r600_disk_cache_create(rscreen
);
1497 slab_create_parent(&rscreen
->pool_transfers
, sizeof(struct r600_transfer
), 64);
1499 rscreen
->force_aniso
= MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1500 if (rscreen
->force_aniso
>= 0) {
1501 printf("radeon: Forcing anisotropy filter to %ix\n",
1502 /* round down to a power of two */
1503 1 << util_logbase2(rscreen
->force_aniso
));
1506 util_format_s3tc_init();
1507 (void) mtx_init(&rscreen
->aux_context_lock
, mtx_plain
);
1508 (void) mtx_init(&rscreen
->gpu_load_mutex
, mtx_plain
);
1510 if (rscreen
->debug_flags
& DBG_INFO
) {
1511 printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
1512 rscreen
->info
.pci_domain
, rscreen
->info
.pci_bus
,
1513 rscreen
->info
.pci_dev
, rscreen
->info
.pci_func
);
1514 printf("pci_id = 0x%x\n", rscreen
->info
.pci_id
);
1515 printf("family = %i (%s)\n", rscreen
->info
.family
,
1516 r600_get_family_name(rscreen
));
1517 printf("chip_class = %i\n", rscreen
->info
.chip_class
);
1518 printf("pte_fragment_size = %u\n", rscreen
->info
.pte_fragment_size
);
1519 printf("gart_page_size = %u\n", rscreen
->info
.gart_page_size
);
1520 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen
->info
.gart_size
, 1024*1024));
1521 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen
->info
.vram_size
, 1024*1024));
1522 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen
->info
.vram_vis_size
, 1024*1024));
1523 printf("max_alloc_size = %i MB\n",
1524 (int)DIV_ROUND_UP(rscreen
->info
.max_alloc_size
, 1024*1024));
1525 printf("min_alloc_size = %u\n", rscreen
->info
.min_alloc_size
);
1526 printf("has_dedicated_vram = %u\n", rscreen
->info
.has_dedicated_vram
);
1527 printf("has_virtual_memory = %i\n", rscreen
->info
.has_virtual_memory
);
1528 printf("gfx_ib_pad_with_type2 = %i\n", rscreen
->info
.gfx_ib_pad_with_type2
);
1529 printf("has_hw_decode = %u\n", rscreen
->info
.has_hw_decode
);
1530 printf("num_sdma_rings = %i\n", rscreen
->info
.num_sdma_rings
);
1531 printf("num_compute_rings = %u\n", rscreen
->info
.num_compute_rings
);
1532 printf("uvd_fw_version = %u\n", rscreen
->info
.uvd_fw_version
);
1533 printf("vce_fw_version = %u\n", rscreen
->info
.vce_fw_version
);
1534 printf("me_fw_version = %i\n", rscreen
->info
.me_fw_version
);
1535 printf("me_fw_feature = %i\n", rscreen
->info
.me_fw_feature
);
1536 printf("pfp_fw_version = %i\n", rscreen
->info
.pfp_fw_version
);
1537 printf("pfp_fw_feature = %i\n", rscreen
->info
.pfp_fw_feature
);
1538 printf("ce_fw_version = %i\n", rscreen
->info
.ce_fw_version
);
1539 printf("ce_fw_feature = %i\n", rscreen
->info
.ce_fw_feature
);
1540 printf("vce_harvest_config = %i\n", rscreen
->info
.vce_harvest_config
);
1541 printf("clock_crystal_freq = %i\n", rscreen
->info
.clock_crystal_freq
);
1542 printf("tcc_cache_line_size = %u\n", rscreen
->info
.tcc_cache_line_size
);
1543 printf("drm = %i.%i.%i\n", rscreen
->info
.drm_major
,
1544 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
);
1545 printf("has_userptr = %i\n", rscreen
->info
.has_userptr
);
1546 printf("has_syncobj = %u\n", rscreen
->info
.has_syncobj
);
1548 printf("r600_max_quad_pipes = %i\n", rscreen
->info
.r600_max_quad_pipes
);
1549 printf("max_shader_clock = %i\n", rscreen
->info
.max_shader_clock
);
1550 printf("num_good_compute_units = %i\n", rscreen
->info
.num_good_compute_units
);
1551 printf("max_se = %i\n", rscreen
->info
.max_se
);
1552 printf("max_sh_per_se = %i\n", rscreen
->info
.max_sh_per_se
);
1554 printf("r600_gb_backend_map = %i\n", rscreen
->info
.r600_gb_backend_map
);
1555 printf("r600_gb_backend_map_valid = %i\n", rscreen
->info
.r600_gb_backend_map_valid
);
1556 printf("r600_num_banks = %i\n", rscreen
->info
.r600_num_banks
);
1557 printf("num_render_backends = %i\n", rscreen
->info
.num_render_backends
);
1558 printf("num_tile_pipes = %i\n", rscreen
->info
.num_tile_pipes
);
1559 printf("pipe_interleave_bytes = %i\n", rscreen
->info
.pipe_interleave_bytes
);
1560 printf("enabled_rb_mask = 0x%x\n", rscreen
->info
.enabled_rb_mask
);
1561 printf("max_alignment = %u\n", (unsigned)rscreen
->info
.max_alignment
);
1566 void si_destroy_common_screen(struct r600_common_screen
*rscreen
)
1568 si_perfcounters_destroy(rscreen
);
1569 si_gpu_load_kill_thread(rscreen
);
1571 mtx_destroy(&rscreen
->gpu_load_mutex
);
1572 mtx_destroy(&rscreen
->aux_context_lock
);
1573 rscreen
->aux_context
->destroy(rscreen
->aux_context
);
1575 slab_destroy_parent(&rscreen
->pool_transfers
);
1577 disk_cache_destroy(rscreen
->disk_shader_cache
);
1578 rscreen
->ws
->destroy(rscreen
->ws
);
1582 bool si_can_dump_shader(struct r600_common_screen
*rscreen
,
1585 return rscreen
->debug_flags
& (1 << processor
);
1588 bool si_extra_shader_checks(struct r600_common_screen
*rscreen
, unsigned processor
)
1590 return (rscreen
->debug_flags
& DBG_CHECK_IR
) ||
1591 si_can_dump_shader(rscreen
, processor
);
1594 void si_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
1595 uint64_t offset
, uint64_t size
, unsigned value
)
1597 struct r600_common_context
*rctx
= (struct r600_common_context
*)rscreen
->aux_context
;
1599 mtx_lock(&rscreen
->aux_context_lock
);
1600 rctx
->dma_clear_buffer(&rctx
->b
, dst
, offset
, size
, value
);
1601 rscreen
->aux_context
->flush(rscreen
->aux_context
, NULL
, 0);
1602 mtx_unlock(&rscreen
->aux_context_lock
);