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radeonsi: consolidate radeon_add_to_buffer_list calls for DMA
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40
41 #ifndef HAVE_LLVM
42 #define HAVE_LLVM 0
43 #endif
44
45 struct r600_multi_fence {
46 struct pipe_reference reference;
47 struct pipe_fence_handle *gfx;
48 struct pipe_fence_handle *sdma;
49 };
50
51 /*
52 * shader binary helpers.
53 */
54 void radeon_shader_binary_init(struct radeon_shader_binary *b)
55 {
56 memset(b, 0, sizeof(*b));
57 }
58
59 void radeon_shader_binary_clean(struct radeon_shader_binary *b)
60 {
61 if (!b)
62 return;
63 FREE(b->code);
64 FREE(b->config);
65 FREE(b->rodata);
66 FREE(b->global_symbol_offsets);
67 FREE(b->relocs);
68 FREE(b->disasm_string);
69 }
70
71 /*
72 * pipe_context
73 */
74
75 void r600_draw_rectangle(struct blitter_context *blitter,
76 int x1, int y1, int x2, int y2, float depth,
77 enum blitter_attrib_type type,
78 const union pipe_color_union *attrib)
79 {
80 struct r600_common_context *rctx =
81 (struct r600_common_context*)util_blitter_get_pipe(blitter);
82 struct pipe_viewport_state viewport;
83 struct pipe_resource *buf = NULL;
84 unsigned offset = 0;
85 float *vb;
86
87 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
88 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
89 return;
90 }
91
92 /* Some operations (like color resolve on r6xx) don't work
93 * with the conventional primitive types.
94 * One that works is PT_RECTLIST, which we use here. */
95
96 /* setup viewport */
97 viewport.scale[0] = 1.0f;
98 viewport.scale[1] = 1.0f;
99 viewport.scale[2] = 1.0f;
100 viewport.translate[0] = 0.0f;
101 viewport.translate[1] = 0.0f;
102 viewport.translate[2] = 0.0f;
103 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
104
105 /* Upload vertices. The hw rectangle has only 3 vertices,
106 * I guess the 4th one is derived from the first 3.
107 * The vertex specification should match u_blitter's vertex element state. */
108 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, 256, &offset, &buf, (void**)&vb);
109 if (!buf)
110 return;
111
112 vb[0] = x1;
113 vb[1] = y1;
114 vb[2] = depth;
115 vb[3] = 1;
116
117 vb[8] = x1;
118 vb[9] = y2;
119 vb[10] = depth;
120 vb[11] = 1;
121
122 vb[16] = x2;
123 vb[17] = y1;
124 vb[18] = depth;
125 vb[19] = 1;
126
127 if (attrib) {
128 memcpy(vb+4, attrib->f, sizeof(float)*4);
129 memcpy(vb+12, attrib->f, sizeof(float)*4);
130 memcpy(vb+20, attrib->f, sizeof(float)*4);
131 }
132
133 /* draw */
134 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
135 R600_PRIM_RECTANGLE_LIST, 3, 2);
136 pipe_resource_reference(&buf, NULL);
137 }
138
139 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
140 struct r600_resource *dst, struct r600_resource *src)
141 {
142 uint64_t vram = 0, gtt = 0;
143
144 if (dst) {
145 if (dst->domains & RADEON_DOMAIN_VRAM)
146 vram += dst->buf->size;
147 else if (dst->domains & RADEON_DOMAIN_GTT)
148 gtt += dst->buf->size;
149 }
150 if (src) {
151 if (src->domains & RADEON_DOMAIN_VRAM)
152 vram += src->buf->size;
153 else if (src->domains & RADEON_DOMAIN_GTT)
154 gtt += src->buf->size;
155 }
156
157 /* Flush the GFX IB if it's not empty. */
158 if (ctx->gfx.cs->cdw > ctx->initial_gfx_cs_size)
159 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
160
161 /* Flush if there's not enough space, or if the memory usage per IB
162 * is too large.
163 */
164 if ((num_dw + ctx->dma.cs->cdw) > ctx->dma.cs->max_dw ||
165 !ctx->ws->cs_memory_below_limit(ctx->dma.cs, vram, gtt)) {
166 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
167 assert((num_dw + ctx->dma.cs->cdw) <= ctx->dma.cs->max_dw);
168 }
169
170 /* If GPUVM is not supported, the CS checker needs 2 entries
171 * in the buffer list per packet, which has to be done manually.
172 */
173 if (ctx->screen->info.has_virtual_memory) {
174 if (dst)
175 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
176 RADEON_USAGE_WRITE,
177 RADEON_PRIO_SDMA_BUFFER);
178 if (src)
179 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
180 RADEON_USAGE_READ,
181 RADEON_PRIO_SDMA_BUFFER);
182 }
183 }
184
185 /* This is required to prevent read-after-write hazards. */
186 void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
187 {
188 struct radeon_winsys_cs *cs = rctx->dma.cs;
189
190 /* done at the end of DMA calls, so increment this. */
191 rctx->num_dma_calls++;
192
193 /* IBs using too little memory are limited by the IB submission overhead.
194 * IBs using too much memory are limited by the kernel/TTM overhead.
195 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
196 *
197 * This heuristic makes sure that DMA requests are executed
198 * very soon after the call is made and lowers memory usage.
199 * It improves texture upload performance by keeping the DMA
200 * engine busy while uploads are being submitted.
201 */
202 if (rctx->ws->cs_query_memory_usage(rctx->dma.cs) > 64 * 1024 * 1024) {
203 rctx->dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
204 return;
205 }
206
207 r600_need_dma_space(rctx, 1, NULL, NULL);
208
209 if (cs->cdw == 0) /* empty queue */
210 return;
211
212 /* NOP waits for idle on Evergreen and later. */
213 if (rctx->chip_class >= CIK)
214 radeon_emit(cs, 0x00000000); /* NOP */
215 else if (rctx->chip_class >= EVERGREEN)
216 radeon_emit(cs, 0xf0000000); /* NOP */
217 else {
218 /* TODO: R600-R700 should use the FENCE packet.
219 * CS checker support is required. */
220 }
221 }
222
223 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
224 {
225 }
226
227 void r600_preflush_suspend_features(struct r600_common_context *ctx)
228 {
229 /* suspend queries */
230 if (!LIST_IS_EMPTY(&ctx->active_queries))
231 r600_suspend_queries(ctx);
232
233 ctx->streamout.suspended = false;
234 if (ctx->streamout.begin_emitted) {
235 r600_emit_streamout_end(ctx);
236 ctx->streamout.suspended = true;
237 }
238 }
239
240 void r600_postflush_resume_features(struct r600_common_context *ctx)
241 {
242 if (ctx->streamout.suspended) {
243 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
244 r600_streamout_buffers_dirty(ctx);
245 }
246
247 /* resume queries */
248 if (!LIST_IS_EMPTY(&ctx->active_queries))
249 r600_resume_queries(ctx);
250 }
251
252 static void r600_flush_from_st(struct pipe_context *ctx,
253 struct pipe_fence_handle **fence,
254 unsigned flags)
255 {
256 struct pipe_screen *screen = ctx->screen;
257 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
258 unsigned rflags = 0;
259 struct pipe_fence_handle *gfx_fence = NULL;
260 struct pipe_fence_handle *sdma_fence = NULL;
261
262 if (flags & PIPE_FLUSH_END_OF_FRAME)
263 rflags |= RADEON_FLUSH_END_OF_FRAME;
264
265 if (rctx->dma.cs) {
266 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
267 }
268 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
269
270 /* Both engines can signal out of order, so we need to keep both fences. */
271 if (gfx_fence || sdma_fence) {
272 struct r600_multi_fence *multi_fence =
273 CALLOC_STRUCT(r600_multi_fence);
274 if (!multi_fence)
275 return;
276
277 multi_fence->reference.count = 1;
278 multi_fence->gfx = gfx_fence;
279 multi_fence->sdma = sdma_fence;
280
281 screen->fence_reference(screen, fence, NULL);
282 *fence = (struct pipe_fence_handle*)multi_fence;
283 }
284 }
285
286 static void r600_flush_dma_ring(void *ctx, unsigned flags,
287 struct pipe_fence_handle **fence)
288 {
289 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
290 struct radeon_winsys_cs *cs = rctx->dma.cs;
291
292 if (cs->cdw)
293 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
294 if (fence)
295 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
296 }
297
298 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
299 {
300 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
301 unsigned latest = rctx->ws->query_value(rctx->ws,
302 RADEON_GPU_RESET_COUNTER);
303
304 if (rctx->gpu_reset_counter == latest)
305 return PIPE_NO_RESET;
306
307 rctx->gpu_reset_counter = latest;
308 return PIPE_UNKNOWN_CONTEXT_RESET;
309 }
310
311 static void r600_set_debug_callback(struct pipe_context *ctx,
312 const struct pipe_debug_callback *cb)
313 {
314 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
315
316 if (cb)
317 rctx->debug = *cb;
318 else
319 memset(&rctx->debug, 0, sizeof(rctx->debug));
320 }
321
322 bool r600_common_context_init(struct r600_common_context *rctx,
323 struct r600_common_screen *rscreen)
324 {
325 util_slab_create(&rctx->pool_transfers,
326 sizeof(struct r600_transfer), 64,
327 UTIL_SLAB_SINGLETHREADED);
328
329 rctx->screen = rscreen;
330 rctx->ws = rscreen->ws;
331 rctx->family = rscreen->family;
332 rctx->chip_class = rscreen->chip_class;
333
334 if (rscreen->chip_class >= CIK)
335 rctx->max_db = MAX2(8, rscreen->info.num_render_backends);
336 else if (rscreen->chip_class >= EVERGREEN)
337 rctx->max_db = 8;
338 else
339 rctx->max_db = 4;
340
341 rctx->b.invalidate_resource = r600_invalidate_resource;
342 rctx->b.transfer_map = u_transfer_map_vtbl;
343 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
344 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
345 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
346 rctx->b.memory_barrier = r600_memory_barrier;
347 rctx->b.flush = r600_flush_from_st;
348 rctx->b.set_debug_callback = r600_set_debug_callback;
349
350 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
351 rctx->b.get_device_reset_status = r600_get_reset_status;
352 rctx->gpu_reset_counter =
353 rctx->ws->query_value(rctx->ws,
354 RADEON_GPU_RESET_COUNTER);
355 }
356
357 LIST_INITHEAD(&rctx->texture_buffers);
358
359 r600_init_context_texture_functions(rctx);
360 r600_init_viewport_functions(rctx);
361 r600_streamout_init(rctx);
362 r600_query_init(rctx);
363 cayman_init_msaa(&rctx->b);
364
365 rctx->allocator_so_filled_size =
366 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
367 4, 0, PIPE_USAGE_DEFAULT, TRUE);
368 if (!rctx->allocator_so_filled_size)
369 return false;
370
371 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024,
372 PIPE_BIND_INDEX_BUFFER |
373 PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
374 if (!rctx->uploader)
375 return false;
376
377 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
378 if (!rctx->ctx)
379 return false;
380
381 if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
382 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
383 r600_flush_dma_ring,
384 rctx);
385 rctx->dma.flush = r600_flush_dma_ring;
386 }
387
388 return true;
389 }
390
391 void r600_common_context_cleanup(struct r600_common_context *rctx)
392 {
393 if (rctx->gfx.cs)
394 rctx->ws->cs_destroy(rctx->gfx.cs);
395 if (rctx->dma.cs)
396 rctx->ws->cs_destroy(rctx->dma.cs);
397 if (rctx->ctx)
398 rctx->ws->ctx_destroy(rctx->ctx);
399
400 if (rctx->uploader) {
401 u_upload_destroy(rctx->uploader);
402 }
403
404 util_slab_destroy(&rctx->pool_transfers);
405
406 if (rctx->allocator_so_filled_size) {
407 u_suballocator_destroy(rctx->allocator_so_filled_size);
408 }
409 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
410 }
411
412 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
413 {
414 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
415 struct r600_resource *rr = (struct r600_resource *)r;
416
417 if (!r) {
418 return;
419 }
420
421 /*
422 * The idea is to compute a gross estimate of memory requirement of
423 * each draw call. After each draw call, memory will be precisely
424 * accounted. So the uncertainty is only on the current draw call.
425 * In practice this gave very good estimate (+/- 10% of the target
426 * memory limit).
427 */
428 if (rr->domains & RADEON_DOMAIN_VRAM)
429 rctx->vram += rr->buf->size;
430 else if (rr->domains & RADEON_DOMAIN_GTT)
431 rctx->gtt += rr->buf->size;
432 }
433
434 /*
435 * pipe_screen
436 */
437
438 static const struct debug_named_value common_debug_options[] = {
439 /* logging */
440 { "tex", DBG_TEX, "Print texture info" },
441 { "compute", DBG_COMPUTE, "Print compute info" },
442 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
443 { "info", DBG_INFO, "Print driver information" },
444
445 /* shaders */
446 { "fs", DBG_FS, "Print fetch shaders" },
447 { "vs", DBG_VS, "Print vertex shaders" },
448 { "gs", DBG_GS, "Print geometry shaders" },
449 { "ps", DBG_PS, "Print pixel shaders" },
450 { "cs", DBG_CS, "Print compute shaders" },
451 { "tcs", DBG_TCS, "Print tessellation control shaders" },
452 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
453 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
454 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
455 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
456 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
457
458 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
459
460 /* features */
461 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
462 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
463 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
464 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
465 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
466 { "notiling", DBG_NO_TILING, "Disable tiling" },
467 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
468 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
469 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
470 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
471 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
472 { "nodcc", DBG_NO_DCC, "Disable DCC." },
473 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
474 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
475 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
476 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
477 { "noce", DBG_NO_CE, "Disable the constant engine"},
478
479 DEBUG_NAMED_VALUE_END /* must be last */
480 };
481
482 static const char* r600_get_vendor(struct pipe_screen* pscreen)
483 {
484 return "X.Org";
485 }
486
487 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
488 {
489 return "AMD";
490 }
491
492 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
493 {
494 switch (rscreen->info.family) {
495 case CHIP_R600: return "AMD R600";
496 case CHIP_RV610: return "AMD RV610";
497 case CHIP_RV630: return "AMD RV630";
498 case CHIP_RV670: return "AMD RV670";
499 case CHIP_RV620: return "AMD RV620";
500 case CHIP_RV635: return "AMD RV635";
501 case CHIP_RS780: return "AMD RS780";
502 case CHIP_RS880: return "AMD RS880";
503 case CHIP_RV770: return "AMD RV770";
504 case CHIP_RV730: return "AMD RV730";
505 case CHIP_RV710: return "AMD RV710";
506 case CHIP_RV740: return "AMD RV740";
507 case CHIP_CEDAR: return "AMD CEDAR";
508 case CHIP_REDWOOD: return "AMD REDWOOD";
509 case CHIP_JUNIPER: return "AMD JUNIPER";
510 case CHIP_CYPRESS: return "AMD CYPRESS";
511 case CHIP_HEMLOCK: return "AMD HEMLOCK";
512 case CHIP_PALM: return "AMD PALM";
513 case CHIP_SUMO: return "AMD SUMO";
514 case CHIP_SUMO2: return "AMD SUMO2";
515 case CHIP_BARTS: return "AMD BARTS";
516 case CHIP_TURKS: return "AMD TURKS";
517 case CHIP_CAICOS: return "AMD CAICOS";
518 case CHIP_CAYMAN: return "AMD CAYMAN";
519 case CHIP_ARUBA: return "AMD ARUBA";
520 case CHIP_TAHITI: return "AMD TAHITI";
521 case CHIP_PITCAIRN: return "AMD PITCAIRN";
522 case CHIP_VERDE: return "AMD CAPE VERDE";
523 case CHIP_OLAND: return "AMD OLAND";
524 case CHIP_HAINAN: return "AMD HAINAN";
525 case CHIP_BONAIRE: return "AMD BONAIRE";
526 case CHIP_KAVERI: return "AMD KAVERI";
527 case CHIP_KABINI: return "AMD KABINI";
528 case CHIP_HAWAII: return "AMD HAWAII";
529 case CHIP_MULLINS: return "AMD MULLINS";
530 case CHIP_TONGA: return "AMD TONGA";
531 case CHIP_ICELAND: return "AMD ICELAND";
532 case CHIP_CARRIZO: return "AMD CARRIZO";
533 case CHIP_FIJI: return "AMD FIJI";
534 case CHIP_POLARIS10: return "AMD POLARIS10";
535 case CHIP_POLARIS11: return "AMD POLARIS11";
536 case CHIP_STONEY: return "AMD STONEY";
537 default: return "AMD unknown";
538 }
539 }
540
541 static const char* r600_get_name(struct pipe_screen* pscreen)
542 {
543 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
544
545 return rscreen->renderer_string;
546 }
547
548 static float r600_get_paramf(struct pipe_screen* pscreen,
549 enum pipe_capf param)
550 {
551 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
552
553 switch (param) {
554 case PIPE_CAPF_MAX_LINE_WIDTH:
555 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
556 case PIPE_CAPF_MAX_POINT_WIDTH:
557 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
558 if (rscreen->family >= CHIP_CEDAR)
559 return 16384.0f;
560 else
561 return 8192.0f;
562 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
563 return 16.0f;
564 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
565 return 16.0f;
566 case PIPE_CAPF_GUARD_BAND_LEFT:
567 case PIPE_CAPF_GUARD_BAND_TOP:
568 case PIPE_CAPF_GUARD_BAND_RIGHT:
569 case PIPE_CAPF_GUARD_BAND_BOTTOM:
570 return 0.0f;
571 }
572 return 0.0f;
573 }
574
575 static int r600_get_video_param(struct pipe_screen *screen,
576 enum pipe_video_profile profile,
577 enum pipe_video_entrypoint entrypoint,
578 enum pipe_video_cap param)
579 {
580 switch (param) {
581 case PIPE_VIDEO_CAP_SUPPORTED:
582 return vl_profile_supported(screen, profile, entrypoint);
583 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
584 return 1;
585 case PIPE_VIDEO_CAP_MAX_WIDTH:
586 case PIPE_VIDEO_CAP_MAX_HEIGHT:
587 return vl_video_buffer_max_size(screen);
588 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
589 return PIPE_FORMAT_NV12;
590 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
591 return false;
592 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
593 return false;
594 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
595 return true;
596 case PIPE_VIDEO_CAP_MAX_LEVEL:
597 return vl_level_supported(screen, profile);
598 default:
599 return 0;
600 }
601 }
602
603 const char *r600_get_llvm_processor_name(enum radeon_family family)
604 {
605 switch (family) {
606 case CHIP_R600:
607 case CHIP_RV630:
608 case CHIP_RV635:
609 case CHIP_RV670:
610 return "r600";
611 case CHIP_RV610:
612 case CHIP_RV620:
613 case CHIP_RS780:
614 case CHIP_RS880:
615 return "rs880";
616 case CHIP_RV710:
617 return "rv710";
618 case CHIP_RV730:
619 return "rv730";
620 case CHIP_RV740:
621 case CHIP_RV770:
622 return "rv770";
623 case CHIP_PALM:
624 case CHIP_CEDAR:
625 return "cedar";
626 case CHIP_SUMO:
627 case CHIP_SUMO2:
628 return "sumo";
629 case CHIP_REDWOOD:
630 return "redwood";
631 case CHIP_JUNIPER:
632 return "juniper";
633 case CHIP_HEMLOCK:
634 case CHIP_CYPRESS:
635 return "cypress";
636 case CHIP_BARTS:
637 return "barts";
638 case CHIP_TURKS:
639 return "turks";
640 case CHIP_CAICOS:
641 return "caicos";
642 case CHIP_CAYMAN:
643 case CHIP_ARUBA:
644 return "cayman";
645
646 case CHIP_TAHITI: return "tahiti";
647 case CHIP_PITCAIRN: return "pitcairn";
648 case CHIP_VERDE: return "verde";
649 case CHIP_OLAND: return "oland";
650 case CHIP_HAINAN: return "hainan";
651 case CHIP_BONAIRE: return "bonaire";
652 case CHIP_KABINI: return "kabini";
653 case CHIP_KAVERI: return "kaveri";
654 case CHIP_HAWAII: return "hawaii";
655 case CHIP_MULLINS:
656 return "mullins";
657 case CHIP_TONGA: return "tonga";
658 case CHIP_ICELAND: return "iceland";
659 case CHIP_CARRIZO: return "carrizo";
660 #if HAVE_LLVM <= 0x0307
661 case CHIP_FIJI: return "tonga";
662 case CHIP_STONEY: return "carrizo";
663 #else
664 case CHIP_FIJI: return "fiji";
665 case CHIP_STONEY: return "stoney";
666 #endif
667 #if HAVE_LLVM <= 0x0308
668 case CHIP_POLARIS10: return "tonga";
669 case CHIP_POLARIS11: return "tonga";
670 #else
671 case CHIP_POLARIS10: return "polaris10";
672 case CHIP_POLARIS11: return "polaris11";
673 #endif
674 default: return "";
675 }
676 }
677
678 static int r600_get_compute_param(struct pipe_screen *screen,
679 enum pipe_shader_ir ir_type,
680 enum pipe_compute_cap param,
681 void *ret)
682 {
683 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
684
685 //TODO: select these params by asic
686 switch (param) {
687 case PIPE_COMPUTE_CAP_IR_TARGET: {
688 const char *gpu;
689 const char *triple;
690 if (rscreen->family <= CHIP_ARUBA) {
691 triple = "r600--";
692 } else {
693 triple = "amdgcn--";
694 }
695 switch(rscreen->family) {
696 /* Clang < 3.6 is missing Hainan in its list of
697 * GPUs, so we need to use the name of a similar GPU.
698 */
699 default:
700 gpu = r600_get_llvm_processor_name(rscreen->family);
701 break;
702 }
703 if (ret) {
704 sprintf(ret, "%s-%s", gpu, triple);
705 }
706 /* +2 for dash and terminating NIL byte */
707 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
708 }
709 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
710 if (ret) {
711 uint64_t *grid_dimension = ret;
712 grid_dimension[0] = 3;
713 }
714 return 1 * sizeof(uint64_t);
715
716 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
717 if (ret) {
718 uint64_t *grid_size = ret;
719 grid_size[0] = 65535;
720 grid_size[1] = 65535;
721 grid_size[2] = 65535;
722 }
723 return 3 * sizeof(uint64_t) ;
724
725 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
726 if (ret) {
727 uint64_t *block_size = ret;
728 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
729 ir_type == PIPE_SHADER_IR_TGSI) {
730 block_size[0] = 2048;
731 block_size[1] = 2048;
732 block_size[2] = 2048;
733 } else {
734 block_size[0] = 256;
735 block_size[1] = 256;
736 block_size[2] = 256;
737 }
738 }
739 return 3 * sizeof(uint64_t);
740
741 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
742 if (ret) {
743 uint64_t *max_threads_per_block = ret;
744 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
745 ir_type == PIPE_SHADER_IR_TGSI)
746 *max_threads_per_block = 2048;
747 else
748 *max_threads_per_block = 256;
749 }
750 return sizeof(uint64_t);
751
752 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
753 if (ret) {
754 uint64_t *max_global_size = ret;
755 uint64_t max_mem_alloc_size;
756
757 r600_get_compute_param(screen, ir_type,
758 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
759 &max_mem_alloc_size);
760
761 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
762 * 1/4 of the MAX_GLOBAL_SIZE. Since the
763 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
764 * make sure we never report more than
765 * 4 * MAX_MEM_ALLOC_SIZE.
766 */
767 *max_global_size = MIN2(4 * max_mem_alloc_size,
768 rscreen->info.gart_size +
769 rscreen->info.vram_size);
770 }
771 return sizeof(uint64_t);
772
773 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
774 if (ret) {
775 uint64_t *max_local_size = ret;
776 /* Value reported by the closed source driver. */
777 *max_local_size = 32768;
778 }
779 return sizeof(uint64_t);
780
781 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
782 if (ret) {
783 uint64_t *max_input_size = ret;
784 /* Value reported by the closed source driver. */
785 *max_input_size = 1024;
786 }
787 return sizeof(uint64_t);
788
789 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
790 if (ret) {
791 uint64_t *max_mem_alloc_size = ret;
792
793 /* XXX: The limit in older kernels is 256 MB. We
794 * should add a query here for newer kernels.
795 */
796 *max_mem_alloc_size = 256 * 1024 * 1024;
797 }
798 return sizeof(uint64_t);
799
800 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
801 if (ret) {
802 uint32_t *max_clock_frequency = ret;
803 *max_clock_frequency = rscreen->info.max_shader_clock;
804 }
805 return sizeof(uint32_t);
806
807 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
808 if (ret) {
809 uint32_t *max_compute_units = ret;
810 *max_compute_units = rscreen->info.num_good_compute_units;
811 }
812 return sizeof(uint32_t);
813
814 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
815 if (ret) {
816 uint32_t *images_supported = ret;
817 *images_supported = 0;
818 }
819 return sizeof(uint32_t);
820 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
821 break; /* unused */
822 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
823 if (ret) {
824 uint32_t *subgroup_size = ret;
825 *subgroup_size = r600_wavefront_size(rscreen->family);
826 }
827 return sizeof(uint32_t);
828 }
829
830 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
831 return 0;
832 }
833
834 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
835 {
836 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
837
838 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
839 rscreen->info.clock_crystal_freq;
840 }
841
842 static void r600_fence_reference(struct pipe_screen *screen,
843 struct pipe_fence_handle **dst,
844 struct pipe_fence_handle *src)
845 {
846 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
847 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
848 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
849
850 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
851 ws->fence_reference(&(*rdst)->gfx, NULL);
852 ws->fence_reference(&(*rdst)->sdma, NULL);
853 FREE(*rdst);
854 }
855 *rdst = rsrc;
856 }
857
858 static boolean r600_fence_finish(struct pipe_screen *screen,
859 struct pipe_fence_handle *fence,
860 uint64_t timeout)
861 {
862 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
863 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
864 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
865
866 if (rfence->sdma) {
867 if (!rws->fence_wait(rws, rfence->sdma, timeout))
868 return false;
869
870 /* Recompute the timeout after waiting. */
871 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
872 int64_t time = os_time_get_nano();
873 timeout = abs_timeout > time ? abs_timeout - time : 0;
874 }
875 }
876
877 if (!rfence->gfx)
878 return true;
879
880 return rws->fence_wait(rws, rfence->gfx, timeout);
881 }
882
883 static void r600_query_memory_info(struct pipe_screen *screen,
884 struct pipe_memory_info *info)
885 {
886 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
887 struct radeon_winsys *ws = rscreen->ws;
888 unsigned vram_usage, gtt_usage;
889
890 info->total_device_memory = rscreen->info.vram_size / 1024;
891 info->total_staging_memory = rscreen->info.gart_size / 1024;
892
893 /* The real TTM memory usage is somewhat random, because:
894 *
895 * 1) TTM delays freeing memory, because it can only free it after
896 * fences expire.
897 *
898 * 2) The memory usage can be really low if big VRAM evictions are
899 * taking place, but the real usage is well above the size of VRAM.
900 *
901 * Instead, return statistics of this process.
902 */
903 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
904 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
905
906 info->avail_device_memory =
907 vram_usage <= info->total_device_memory ?
908 info->total_device_memory - vram_usage : 0;
909 info->avail_staging_memory =
910 gtt_usage <= info->total_staging_memory ?
911 info->total_staging_memory - gtt_usage : 0;
912
913 info->device_memory_evicted =
914 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
915 /* Just return the number of evicted 64KB pages. */
916 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
917 }
918
919 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
920 const struct pipe_resource *templ)
921 {
922 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
923
924 if (templ->target == PIPE_BUFFER) {
925 return r600_buffer_create(screen, templ,
926 rscreen->info.gart_page_size);
927 } else {
928 return r600_texture_create(screen, templ);
929 }
930 }
931
932 bool r600_common_screen_init(struct r600_common_screen *rscreen,
933 struct radeon_winsys *ws)
934 {
935 char llvm_string[32] = {};
936
937 ws->query_info(ws, &rscreen->info);
938
939 #if HAVE_LLVM
940 snprintf(llvm_string, sizeof(llvm_string),
941 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
942 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
943 #endif
944
945 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
946 "%s (DRM %i.%i.%i%s)",
947 r600_get_chip_name(rscreen), rscreen->info.drm_major,
948 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
949 llvm_string);
950
951 rscreen->b.get_name = r600_get_name;
952 rscreen->b.get_vendor = r600_get_vendor;
953 rscreen->b.get_device_vendor = r600_get_device_vendor;
954 rscreen->b.get_compute_param = r600_get_compute_param;
955 rscreen->b.get_paramf = r600_get_paramf;
956 rscreen->b.get_timestamp = r600_get_timestamp;
957 rscreen->b.fence_finish = r600_fence_finish;
958 rscreen->b.fence_reference = r600_fence_reference;
959 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
960 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
961 rscreen->b.query_memory_info = r600_query_memory_info;
962
963 if (rscreen->info.has_uvd) {
964 rscreen->b.get_video_param = rvid_get_video_param;
965 rscreen->b.is_video_format_supported = rvid_is_format_supported;
966 } else {
967 rscreen->b.get_video_param = r600_get_video_param;
968 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
969 }
970
971 r600_init_screen_texture_functions(rscreen);
972 r600_init_screen_query_functions(rscreen);
973
974 rscreen->ws = ws;
975 rscreen->family = rscreen->info.family;
976 rscreen->chip_class = rscreen->info.chip_class;
977 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
978
979 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
980 if (rscreen->force_aniso >= 0) {
981 printf("radeon: Forcing anisotropy filter to %ix\n",
982 /* round down to a power of two */
983 1 << util_logbase2(rscreen->force_aniso));
984 }
985
986 util_format_s3tc_init();
987 pipe_mutex_init(rscreen->aux_context_lock);
988 pipe_mutex_init(rscreen->gpu_load_mutex);
989
990 if (rscreen->debug_flags & DBG_INFO) {
991 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
992 printf("family = %i (%s)\n", rscreen->info.family,
993 r600_get_chip_name(rscreen));
994 printf("chip_class = %i\n", rscreen->info.chip_class);
995 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
996 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
997 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
998 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
999 printf("has_sdma = %i\n", rscreen->info.has_sdma);
1000 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1001 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1002 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1003 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1004 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1005 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1006 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1007
1008 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1009 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1010 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1011 printf("max_se = %i\n", rscreen->info.max_se);
1012 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1013
1014 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1015 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1016 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1017 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1018 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1019 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1020 }
1021 return true;
1022 }
1023
1024 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1025 {
1026 r600_perfcounters_destroy(rscreen);
1027 r600_gpu_load_kill_thread(rscreen);
1028
1029 pipe_mutex_destroy(rscreen->gpu_load_mutex);
1030 pipe_mutex_destroy(rscreen->aux_context_lock);
1031 rscreen->aux_context->destroy(rscreen->aux_context);
1032
1033 rscreen->ws->destroy(rscreen->ws);
1034 FREE(rscreen);
1035 }
1036
1037 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1038 unsigned processor)
1039 {
1040 switch (processor) {
1041 case PIPE_SHADER_VERTEX:
1042 return (rscreen->debug_flags & DBG_VS) != 0;
1043 case PIPE_SHADER_TESS_CTRL:
1044 return (rscreen->debug_flags & DBG_TCS) != 0;
1045 case PIPE_SHADER_TESS_EVAL:
1046 return (rscreen->debug_flags & DBG_TES) != 0;
1047 case PIPE_SHADER_GEOMETRY:
1048 return (rscreen->debug_flags & DBG_GS) != 0;
1049 case PIPE_SHADER_FRAGMENT:
1050 return (rscreen->debug_flags & DBG_PS) != 0;
1051 case PIPE_SHADER_COMPUTE:
1052 return (rscreen->debug_flags & DBG_CS) != 0;
1053 default:
1054 return false;
1055 }
1056 }
1057
1058 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1059 uint64_t offset, uint64_t size, unsigned value,
1060 enum r600_coherency coher)
1061 {
1062 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1063
1064 pipe_mutex_lock(rscreen->aux_context_lock);
1065 rctx->clear_buffer(&rctx->b, dst, offset, size, value, coher);
1066 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1067 pipe_mutex_unlock(rscreen->aux_context_lock);
1068 }