src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "../../winsys/radeon/drm/radeon_winsys.h"
  38
  39 #include "util/u_double_list.h"
  40 #include "util/u_range.h"
  41 #include "util/u_slab.h"
  42 #include "util/u_suballoc.h"
  43 #include "util/u_transfer.h"
  44
  45 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  46 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  47 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  48
  49 #define R600_QUERY_DRAW_CALLS           (PIPE_QUERY_DRIVER_SPECIFIC + 0)
  50 #define R600_QUERY_REQUESTED_VRAM       (PIPE_QUERY_DRIVER_SPECIFIC + 1)
  51 #define R600_QUERY_REQUESTED_GTT        (PIPE_QUERY_DRIVER_SPECIFIC + 2)
  52 #define R600_QUERY_BUFFER_WAIT_TIME     (PIPE_QUERY_DRIVER_SPECIFIC + 3)
  53
  54 /* read caches */
  55 #define R600_CONTEXT_INV_VERTEX_CACHE           (1 << 0)
  56 #define R600_CONTEXT_INV_TEX_CACHE              (1 << 1)
  57 #define R600_CONTEXT_INV_CONST_CACHE            (1 << 2)
  58 #define R600_CONTEXT_INV_SHADER_CACHE           (1 << 3)
  59 /* read-write caches */
  60 #define R600_CONTEXT_STREAMOUT_FLUSH            (1 << 8)
  61 #define R600_CONTEXT_FLUSH_AND_INV              (1 << 9)
  62 #define R600_CONTEXT_FLUSH_AND_INV_CB_META      (1 << 10)
  63 #define R600_CONTEXT_FLUSH_AND_INV_DB_META      (1 << 11)
  64 #define R600_CONTEXT_FLUSH_AND_INV_DB           (1 << 12)
  65 #define R600_CONTEXT_FLUSH_AND_INV_CB           (1 << 13)
  66 /* engine synchronization */
  67 #define R600_CONTEXT_PS_PARTIAL_FLUSH           (1 << 16)
  68 #define R600_CONTEXT_WAIT_3D_IDLE               (1 << 17)
  69 #define R600_CONTEXT_WAIT_CP_DMA_IDLE           (1 << 18)
  70
  71 /* Debug flags. */
  72 /* logging */
  73 #define DBG_TEX                 (1 << 0)
  74 #define DBG_TEXMIP              (1 << 1)
  75 #define DBG_COMPUTE             (1 << 2)
  76 #define DBG_VM                  (1 << 3)
  77 #define DBG_TRACE_CS            (1 << 4)
  78 /* shaders */
  79 #define DBG_FS                  (1 << 8)
  80 #define DBG_VS                  (1 << 9)
  81 #define DBG_GS                  (1 << 10)
  82 #define DBG_PS                  (1 << 11)
  83 #define DBG_CS                  (1 << 12)
  84 /* features */
  85 #define DBG_NO_HYPERZ           (1 << 13)
  86 #define DBG_NO_DISCARD_RANGE    (1 << 14)
  87 /* The maximum allowed bit is 15. */
  88
  89 #define R600_MAP_BUFFER_ALIGNMENT 64
  90
  91 struct r600_common_context;
  92
  93 struct r600_resource {
  94         struct u_resource               b;
  95
  96         /* Winsys objects. */
  97         struct pb_buffer                *buf;
  98         struct radeon_winsys_cs_handle  *cs_buf;
  99
 100         /* Resource state. */
 101         enum radeon_bo_domain           domains;
 102
 103         /* The buffer range which is initialized (with a write transfer,
 104          * streamout, DMA, or as a random access target). The rest of
 105          * the buffer is considered invalid and can be mapped unsynchronized.
 106          *
 107          * This allows unsychronized mapping of a buffer range which hasn't
 108          * been used yet. It's for applications which forget to use
 109          * the unsynchronized map flag and expect the driver to figure it out.
 110          */
 111         struct util_range               valid_buffer_range;
 112 };
 113
 114 struct r600_transfer {
 115         struct pipe_transfer            transfer;
 116         struct r600_resource            *staging;
 117         unsigned                        offset;
 118 };
 119
 120 struct r600_fmask_info {
 121         unsigned offset;
 122         unsigned size;
 123         unsigned alignment;
 124         unsigned pitch;
 125         unsigned bank_height;
 126         unsigned slice_tile_max;
 127         unsigned tile_mode_index;
 128 };
 129
 130 struct r600_cmask_info {
 131         unsigned offset;
 132         unsigned size;
 133         unsigned alignment;
 134         unsigned slice_tile_max;
 135 };
 136
 137 struct r600_texture {
 138         struct r600_resource            resource;
 139
 140         unsigned                        size;
 141         unsigned                        pitch_override;
 142         bool                            is_depth;
 143         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 144         struct r600_texture             *flushed_depth_texture;
 145         boolean                         is_flushing_texture;
 146         struct radeon_surface           surface;
 147
 148         /* Colorbuffer compression and fast clear. */
 149         struct r600_fmask_info          fmask;
 150         struct r600_cmask_info          cmask;
 151         struct r600_resource            *cmask_buffer;
 152         unsigned                        color_clear_value[2];
 153
 154         /* Depth buffer compression and fast clear. */
 155         struct r600_resource            *htile_buffer;
 156         float                           depth_clear_value;
 157
 158         bool                            non_disp_tiling; /* R600-Cayman only */
 159         unsigned                        mipmap_shift;
 160 };
 161
 162 struct r600_tiling_info {
 163         unsigned num_channels;
 164         unsigned num_banks;
 165         unsigned group_bytes;
 166 };
 167
 168 struct r600_common_screen {
 169         struct pipe_screen              b;
 170         struct radeon_winsys            *ws;
 171         enum radeon_family              family;
 172         enum chip_class                 chip_class;
 173         struct radeon_info              info;
 174         struct r600_tiling_info         tiling_info;
 175         unsigned                        debug_flags;
 176         bool                            has_cp_dma;
 177         bool                            has_streamout;
 178
 179         /* Auxiliary context. Mainly used to initialize resources.
 180          * It must be locked prior to using and flushed before unlocking. */
 181         struct pipe_context             *aux_context;
 182         pipe_mutex                      aux_context_lock;
 183
 184         struct r600_resource            *trace_bo;
 185         uint32_t                        *trace_ptr;
 186         unsigned                        cs_count;
 187 };
 188
 189 /* This encapsulates a state or an operation which can emitted into the GPU
 190  * command stream. */
 191 struct r600_atom {
 192         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 193         unsigned                num_dw;
 194         bool                    dirty;
 195 };
 196
 197 struct r600_so_target {
 198         struct pipe_stream_output_target b;
 199
 200         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 201         struct r600_resource    *buf_filled_size;
 202         unsigned                buf_filled_size_offset;
 203
 204         unsigned                stride_in_dw;
 205 };
 206
 207 struct r600_streamout {
 208         struct r600_atom                begin_atom;
 209         bool                            begin_emitted;
 210         unsigned                        num_dw_for_end;
 211
 212         unsigned                        enabled_mask;
 213         unsigned                        num_targets;
 214         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 215
 216         unsigned                        append_bitmask;
 217         bool                            suspended;
 218
 219         /* External state which comes from the vertex shader,
 220          * it must be set explicitly when binding a shader. */
 221         unsigned                        *stride_in_dw;
 222 };
 223
 224 struct r600_ring {
 225         struct radeon_winsys_cs         *cs;
 226         bool                            flushing;
 227         void (*flush)(void *ctx, unsigned flags);
 228 };
 229
 230 struct r600_rings {
 231         struct r600_ring                gfx;
 232         struct r600_ring                dma;
 233 };
 234
 235 struct r600_common_context {
 236         struct pipe_context b; /* base class */
 237
 238         struct r600_common_screen       *screen;
 239         struct radeon_winsys            *ws;
 240         enum radeon_family              family;
 241         enum chip_class                 chip_class;
 242         struct r600_rings               rings;
 243
 244         struct u_upload_mgr             *uploader;
 245         struct u_suballocator           *allocator_so_filled_size;
 246         struct util_slab_mempool        pool_transfers;
 247
 248         /* Current unaccounted memory usage. */
 249         uint64_t                        vram;
 250         uint64_t                        gtt;
 251
 252         /* States. */
 253         struct r600_streamout           streamout;
 254
 255         /* Additional context states. */
 256         unsigned flags; /* flush flags */
 257
 258         /* Queries. */
 259         /* The list of active queries. Only one query of each type can be active. */
 260         int                             num_occlusion_queries;
 261         int                             num_pipelinestat_queries;
 262         /* Keep track of non-timer queries, because they should be suspended
 263          * during context flushing.
 264          * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
 265         struct list_head                active_nontimer_queries;
 266         unsigned                        num_cs_dw_nontimer_queries_suspend;
 267         /* If queries have been suspended. */
 268         bool                            nontimer_queries_suspended;
 269         /* Additional hardware info. */
 270         unsigned                        backend_mask;
 271         unsigned                        max_db; /* for OQ */
 272         /* Misc stats. */
 273         unsigned                        num_draw_calls;
 274
 275         /* Render condition. */
 276         struct pipe_query               *current_render_cond;
 277         unsigned                        current_render_cond_mode;
 278         boolean                         current_render_cond_cond;
 279         boolean                         predicate_drawing;
 280
 281         /* Copy one resource to another using async DMA.
 282          * False is returned if the copy couldn't be done. */
 283         boolean (*dma_copy)(struct pipe_context *ctx,
 284                             struct pipe_resource *dst,
 285                             unsigned dst_level,
 286                             unsigned dst_x, unsigned dst_y, unsigned dst_z,
 287                             struct pipe_resource *src,
 288                             unsigned src_level,
 289                             const struct pipe_box *src_box);
 290
 291         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 292                              unsigned offset, unsigned size, unsigned value);
 293
 294         void (*blit_decompress_depth)(struct pipe_context *ctx,
 295                                       struct r600_texture *texture,
 296                                       struct r600_texture *staging,
 297                                       unsigned first_level, unsigned last_level,
 298                                       unsigned first_layer, unsigned last_layer,
 299                                       unsigned first_sample, unsigned last_sample);
 300
 301         /* Reallocate the buffer and update all resource bindings where
 302          * the buffer is bound, including all resource descriptors. */
 303         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 304
 305         /* Enable or disable occlusion queries. */
 306         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 307
 308         /* This ensures there is enough space in the command stream. */
 309         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 310                                   bool include_draw_vbo);
 311 };
 312
 313 /* r600_buffer.c */
 314 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 315                                         struct radeon_winsys_cs_handle *buf,
 316                                         enum radeon_bo_usage usage);
 317 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 318                                       struct r600_resource *resource,
 319                                       unsigned usage);
 320 bool r600_init_resource(struct r600_common_screen *rscreen,
 321                         struct r600_resource *res,
 322                         unsigned size, unsigned alignment,
 323                         bool use_reusable_pool, unsigned usage);
 324 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 325                                          const struct pipe_resource *templ,
 326                                          unsigned alignment);
 327
 328 /* r600_common_pipe.c */
 329 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 330                              struct radeon_winsys *ws);
 331 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 332 bool r600_common_context_init(struct r600_common_context *rctx,
 333                               struct r600_common_screen *rscreen);
 334 void r600_common_context_cleanup(struct r600_common_context *rctx);
 335 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 336 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 337                           const struct tgsi_token *tokens);
 338 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 339                               unsigned offset, unsigned size, unsigned value);
 340 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 341                                                   const struct pipe_resource *templ);
 342 const char *r600_get_llvm_processor_name(enum radeon_family family);
 343
 344 /* r600_query.c */
 345 void r600_query_init(struct r600_common_context *rctx);
 346 void r600_suspend_nontimer_queries(struct r600_common_context *ctx);
 347 void r600_resume_nontimer_queries(struct r600_common_context *ctx);
 348 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 349
 350 /* r600_streamout.c */
 351 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 352 void r600_set_streamout_targets(struct pipe_context *ctx,
 353                                 unsigned num_targets,
 354                                 struct pipe_stream_output_target **targets,
 355                                 unsigned append_bitmask);
 356 void r600_emit_streamout_end(struct r600_common_context *rctx);
 357 void r600_streamout_init(struct r600_common_context *rctx);
 358
 359 /* r600_texture.c */
 360 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 361                                  struct r600_texture *rtex,
 362                                  unsigned nr_samples,
 363                                  struct r600_fmask_info *out);
 364 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 365                                  struct r600_texture *rtex,
 366                                  struct r600_cmask_info *out);
 367 void r600_texture_init_cmask(struct r600_common_screen *rscreen,
 368                              struct r600_texture *rtex);
 369 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 370                                      struct pipe_resource *texture,
 371                                      struct r600_texture **staging);
 372 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 373                                         const struct pipe_resource *templ);
 374 void r600_init_texture_functions(struct r600_common_screen *rscreen);
 375
 376
 377 /* Inline helpers. */
 378
 379 static INLINE struct r600_resource *r600_resource(struct pipe_resource *r)
 380 {
 381         return (struct r600_resource*)r;
 382 }
 383
 384 static INLINE void
 385 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 386 {
 387         pipe_resource_reference((struct pipe_resource **)ptr,
 388                                 (struct pipe_resource *)res);
 389 }
 390
 391 #define R600_ERR(fmt, args...) \
 392         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
 393
 394 #endif