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[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.h
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 /**
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
30 */
31
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
34
35 #include <stdio.h>
36
37 #include "radeon/radeon_winsys.h"
38
39 #include "util/u_blitter.h"
40 #include "util/list.h"
41 #include "util/u_range.h"
42 #include "util/u_slab.h"
43 #include "util/u_suballoc.h"
44 #include "util/u_transfer.h"
45
46 #define ATI_VENDOR_ID 0x1002
47
48 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
49 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
50 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
51 #define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
52
53 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
54 /* Pipeline & streamout query controls. */
55 #define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
56 #define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
57 #define R600_CONTEXT_PRIVATE_FLAG (1u << 3)
58
59 /* special primitive types */
60 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
61
62 /* Debug flags. */
63 /* logging */
64 #define DBG_TEX (1 << 0)
65 /* gap - reuse */
66 #define DBG_COMPUTE (1 << 2)
67 #define DBG_VM (1 << 3)
68 /* gap - reuse */
69 /* shader logging */
70 #define DBG_FS (1 << 5)
71 #define DBG_VS (1 << 6)
72 #define DBG_GS (1 << 7)
73 #define DBG_PS (1 << 8)
74 #define DBG_CS (1 << 9)
75 #define DBG_TCS (1 << 10)
76 #define DBG_TES (1 << 11)
77 #define DBG_NO_IR (1 << 12)
78 #define DBG_NO_TGSI (1 << 13)
79 #define DBG_NO_ASM (1 << 14)
80 #define DBG_PREOPT_IR (1 << 15)
81 /* gaps */
82 #define DBG_TEST_DMA (1 << 20)
83 /* Bits 21-31 are reserved for the r600g driver. */
84 /* features */
85 #define DBG_NO_ASYNC_DMA (1llu << 32)
86 #define DBG_NO_HYPERZ (1llu << 33)
87 #define DBG_NO_DISCARD_RANGE (1llu << 34)
88 #define DBG_NO_2D_TILING (1llu << 35)
89 #define DBG_NO_TILING (1llu << 36)
90 #define DBG_SWITCH_ON_EOP (1llu << 37)
91 #define DBG_FORCE_DMA (1llu << 38)
92 #define DBG_PRECOMPILE (1llu << 39)
93 #define DBG_INFO (1llu << 40)
94 #define DBG_NO_WC (1llu << 41)
95 #define DBG_CHECK_VM (1llu << 42)
96 #define DBG_NO_DCC (1llu << 43)
97 #define DBG_NO_DCC_CLEAR (1llu << 44)
98 #define DBG_NO_RB_PLUS (1llu << 45)
99 #define DBG_SI_SCHED (1llu << 46)
100 #define DBG_MONOLITHIC_SHADERS (1llu << 47)
101 #define DBG_NO_CE (1llu << 48)
102 #define DBG_UNSAFE_MATH (1llu << 49)
103 #define DBG_NO_DCC_FB (1llu << 50)
104
105 #define R600_MAP_BUFFER_ALIGNMENT 64
106 #define R600_MAX_VIEWPORTS 16
107
108 enum r600_coherency {
109 R600_COHERENCY_NONE, /* no cache flushes needed */
110 R600_COHERENCY_SHADER,
111 R600_COHERENCY_CB_META,
112 };
113
114 #ifdef PIPE_ARCH_BIG_ENDIAN
115 #define R600_BIG_ENDIAN 1
116 #else
117 #define R600_BIG_ENDIAN 0
118 #endif
119
120 struct r600_common_context;
121 struct r600_perfcounters;
122 struct tgsi_shader_info;
123
124 struct radeon_shader_reloc {
125 char name[32];
126 uint64_t offset;
127 };
128
129 struct radeon_shader_binary {
130 /** Shader code */
131 unsigned char *code;
132 unsigned code_size;
133
134 /** Config/Context register state that accompanies this shader.
135 * This is a stream of dword pairs. First dword contains the
136 * register address, the second dword contains the value.*/
137 unsigned char *config;
138 unsigned config_size;
139
140 /** The number of bytes of config information for each global symbol.
141 */
142 unsigned config_size_per_symbol;
143
144 /** Constant data accessed by the shader. This will be uploaded
145 * into a constant buffer. */
146 unsigned char *rodata;
147 unsigned rodata_size;
148
149 /** List of symbol offsets for the shader */
150 uint64_t *global_symbol_offsets;
151 unsigned global_symbol_count;
152
153 struct radeon_shader_reloc *relocs;
154 unsigned reloc_count;
155
156 /** Disassembled shader in a string. */
157 char *disasm_string;
158 char *llvm_ir_string;
159 };
160
161 void radeon_shader_binary_init(struct radeon_shader_binary *b);
162 void radeon_shader_binary_clean(struct radeon_shader_binary *b);
163
164 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
165 * at the moment.
166 */
167 struct r600_resource {
168 struct u_resource b;
169
170 /* Winsys objects. */
171 struct pb_buffer *buf;
172 uint64_t gpu_address;
173
174 /* Resource state. */
175 enum radeon_bo_domain domains;
176
177 /* The buffer range which is initialized (with a write transfer,
178 * streamout, DMA, or as a random access target). The rest of
179 * the buffer is considered invalid and can be mapped unsynchronized.
180 *
181 * This allows unsychronized mapping of a buffer range which hasn't
182 * been used yet. It's for applications which forget to use
183 * the unsynchronized map flag and expect the driver to figure it out.
184 */
185 struct util_range valid_buffer_range;
186
187 /* For buffers only. This indicates that a write operation has been
188 * performed by TC L2, but the cache hasn't been flushed.
189 * Any hw block which doesn't use or bypasses TC L2 should check this
190 * flag and flush the cache before using the buffer.
191 *
192 * For example, TC L2 must be flushed if a buffer which has been
193 * modified by a shader store instruction is about to be used as
194 * an index buffer. The reason is that VGT DMA index fetching doesn't
195 * use TC L2.
196 */
197 bool TC_L2_dirty;
198
199 /* Whether the resource has been exported via resource_get_handle. */
200 bool is_shared;
201 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
202 };
203
204 struct r600_transfer {
205 struct pipe_transfer transfer;
206 struct r600_resource *staging;
207 unsigned offset;
208 };
209
210 struct r600_fmask_info {
211 uint64_t offset;
212 uint64_t size;
213 unsigned alignment;
214 unsigned pitch_in_pixels;
215 unsigned bank_height;
216 unsigned slice_tile_max;
217 unsigned tile_mode_index;
218 };
219
220 struct r600_cmask_info {
221 uint64_t offset;
222 uint64_t size;
223 unsigned alignment;
224 unsigned pitch;
225 unsigned height;
226 unsigned xalign;
227 unsigned yalign;
228 unsigned slice_tile_max;
229 unsigned base_address_reg;
230 };
231
232 struct r600_htile_info {
233 unsigned pitch;
234 unsigned height;
235 unsigned xalign;
236 unsigned yalign;
237 };
238
239 struct r600_texture {
240 struct r600_resource resource;
241
242 uint64_t size;
243 unsigned num_level0_transfers;
244 bool is_depth;
245 bool can_sample_z;
246 bool can_sample_s;
247 unsigned dirty_level_mask; /* each bit says if that mipmap is compressed */
248 unsigned stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
249 struct r600_texture *flushed_depth_texture;
250 bool is_flushing_texture;
251 struct radeon_surf surface;
252
253 /* Colorbuffer compression and fast clear. */
254 struct r600_fmask_info fmask;
255 struct r600_cmask_info cmask;
256 struct r600_resource *cmask_buffer;
257 uint64_t dcc_offset; /* 0 = disabled */
258 unsigned cb_color_info; /* fast clear enable bit */
259 unsigned color_clear_value[2];
260 unsigned last_msaa_resolve_target_micro_mode;
261
262 /* Depth buffer compression and fast clear. */
263 struct r600_htile_info htile;
264 struct r600_resource *htile_buffer;
265 bool depth_cleared; /* if it was cleared at least once */
266 float depth_clear_value;
267 bool stencil_cleared; /* if it was cleared at least once */
268 uint8_t stencil_clear_value;
269
270 bool non_disp_tiling; /* R600-Cayman only */
271
272 /* Whether the texture is a displayable back buffer and needs DCC
273 * decompression, which is expensive. Therefore, it's enabled only
274 * if statistics suggest that it will pay off and it's allocated
275 * separately. It can't be bound as a sampler by apps. Limited to
276 * target == 2D and last_level == 0. If enabled, dcc_offset contains
277 * the absolute GPUVM address, not the relative one.
278 */
279 struct r600_resource *dcc_separate_buffer;
280 /* When DCC is temporarily disabled, the separate buffer is here. */
281 struct r600_resource *last_dcc_separate_buffer;
282 /* We need to track DCC dirtiness, because st/dri usually calls
283 * flush_resource twice per frame (not a bug) and we don't wanna
284 * decompress DCC twice. Also, the dirty tracking must be done even
285 * if DCC isn't used, because it's required by the DCC usage analysis
286 * for a possible future enablement.
287 */
288 bool separate_dcc_dirty;
289 /* Statistics gathering for the DCC enablement heuristic. */
290 bool dcc_gather_statistics;
291 /* Estimate of how much this color buffer is written to in units of
292 * full-screen draws: ps_invocations / (width * height)
293 * Shader kills, late Z, and blending with trivial discards make it
294 * inaccurate (we need to count CB updates, not PS invocations).
295 */
296 unsigned ps_draw_ratio;
297 /* The number of clears since the last DCC usage analysis. */
298 unsigned num_slow_clears;
299
300 /* Counter that should be non-zero if the texture is bound to a
301 * framebuffer. Implemented in radeonsi only.
302 */
303 uint32_t framebuffers_bound;
304 };
305
306 struct r600_surface {
307 struct pipe_surface base;
308 const struct radeon_surf_level *level_info;
309
310 bool color_initialized;
311 bool depth_initialized;
312
313 /* Misc. color flags. */
314 bool alphatest_bypass;
315 bool export_16bpc;
316 bool color_is_int8;
317
318 /* Color registers. */
319 unsigned cb_color_info;
320 unsigned cb_color_base;
321 unsigned cb_color_view;
322 unsigned cb_color_size; /* R600 only */
323 unsigned cb_color_dim; /* EG only */
324 unsigned cb_color_pitch; /* EG and later */
325 unsigned cb_color_slice; /* EG and later */
326 unsigned cb_color_attrib; /* EG and later */
327 unsigned cb_dcc_control; /* VI and later */
328 unsigned cb_color_fmask; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
329 unsigned cb_color_fmask_slice; /* EG and later */
330 unsigned cb_color_cmask; /* CB_COLORn_TILE (r600 only) */
331 unsigned cb_color_mask; /* R600 only */
332 unsigned spi_shader_col_format; /* SI+, no blending, no alpha-to-coverage. */
333 unsigned spi_shader_col_format_alpha; /* SI+, alpha-to-coverage */
334 unsigned spi_shader_col_format_blend; /* SI+, blending without alpha. */
335 unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
336 struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
337 struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
338
339 /* DB registers. */
340 unsigned db_depth_info; /* R600 only, then SI and later */
341 unsigned db_z_info; /* EG and later */
342 unsigned db_depth_base; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
343 unsigned db_depth_view;
344 unsigned db_depth_size;
345 unsigned db_depth_slice; /* EG and later */
346 unsigned db_stencil_base; /* EG and later */
347 unsigned db_stencil_info; /* EG and later */
348 unsigned db_prefetch_limit; /* R600 only */
349 unsigned db_htile_surface;
350 unsigned db_htile_data_base;
351 unsigned db_preload_control; /* EG and later */
352 };
353
354 struct r600_common_screen {
355 struct pipe_screen b;
356 struct radeon_winsys *ws;
357 enum radeon_family family;
358 enum chip_class chip_class;
359 struct radeon_info info;
360 uint64_t debug_flags;
361 bool has_cp_dma;
362 bool has_streamout;
363
364 /* Texture filter settings. */
365 int force_aniso; /* -1 = disabled */
366
367 /* Auxiliary context. Mainly used to initialize resources.
368 * It must be locked prior to using and flushed before unlocking. */
369 struct pipe_context *aux_context;
370 pipe_mutex aux_context_lock;
371
372 /* This must be in the screen, because UE4 uses one context for
373 * compilation and another one for rendering.
374 */
375 unsigned num_compilations;
376 /* Along with ST_DEBUG=precompile, this should show if applications
377 * are loading shaders on demand. This is a monotonic counter.
378 */
379 unsigned num_shaders_created;
380
381 /* GPU load thread. */
382 pipe_mutex gpu_load_mutex;
383 pipe_thread gpu_load_thread;
384 unsigned gpu_load_counter_busy;
385 unsigned gpu_load_counter_idle;
386 volatile unsigned gpu_load_stop_thread; /* bool */
387
388 char renderer_string[64];
389
390 /* Performance counters. */
391 struct r600_perfcounters *perfcounters;
392
393 /* If pipe_screen wants to re-emit the framebuffer state of all
394 * contexts, it should atomically increment this. Each context will
395 * compare this with its own last known value of the counter before
396 * drawing and re-emit the framebuffer state accordingly.
397 */
398 unsigned dirty_fb_counter;
399
400 /* Atomically increment this counter when an existing texture's
401 * metadata is enabled or disabled in a way that requires changing
402 * contexts' compressed texture binding masks.
403 */
404 unsigned compressed_colortex_counter;
405
406 /* Atomically increment this counter when an existing texture's
407 * backing buffer or tile mode parameters have changed that requires
408 * recomputation of shader descriptors.
409 */
410 unsigned dirty_tex_descriptor_counter;
411
412 void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
413 struct r600_texture *rtex,
414 struct radeon_bo_metadata *md);
415
416 void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
417 struct r600_texture *rtex,
418 struct radeon_bo_metadata *md);
419 };
420
421 /* This encapsulates a state or an operation which can emitted into the GPU
422 * command stream. */
423 struct r600_atom {
424 void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
425 unsigned num_dw;
426 unsigned short id;
427 };
428
429 struct r600_so_target {
430 struct pipe_stream_output_target b;
431
432 /* The buffer where BUFFER_FILLED_SIZE is stored. */
433 struct r600_resource *buf_filled_size;
434 unsigned buf_filled_size_offset;
435 bool buf_filled_size_valid;
436
437 unsigned stride_in_dw;
438 };
439
440 struct r600_streamout {
441 struct r600_atom begin_atom;
442 bool begin_emitted;
443 unsigned num_dw_for_end;
444
445 unsigned enabled_mask;
446 unsigned num_targets;
447 struct r600_so_target *targets[PIPE_MAX_SO_BUFFERS];
448
449 unsigned append_bitmask;
450 bool suspended;
451
452 /* External state which comes from the vertex shader,
453 * it must be set explicitly when binding a shader. */
454 unsigned *stride_in_dw;
455 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
456
457 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
458 unsigned hw_enabled_mask;
459
460 /* The state of VGT_STRMOUT_(CONFIG|EN). */
461 struct r600_atom enable_atom;
462 bool streamout_enabled;
463 bool prims_gen_query_enabled;
464 int num_prims_gen_queries;
465 };
466
467 struct r600_signed_scissor {
468 int minx;
469 int miny;
470 int maxx;
471 int maxy;
472 };
473
474 struct r600_scissors {
475 struct r600_atom atom;
476 unsigned dirty_mask;
477 struct pipe_scissor_state states[R600_MAX_VIEWPORTS];
478 };
479
480 struct r600_viewports {
481 struct r600_atom atom;
482 unsigned dirty_mask;
483 struct pipe_viewport_state states[R600_MAX_VIEWPORTS];
484 struct r600_signed_scissor as_scissor[R600_MAX_VIEWPORTS];
485 };
486
487 struct r600_ring {
488 struct radeon_winsys_cs *cs;
489 void (*flush)(void *ctx, unsigned flags,
490 struct pipe_fence_handle **fence);
491 };
492
493 /* Saved CS data for debugging features. */
494 struct radeon_saved_cs {
495 uint32_t *ib;
496 unsigned num_dw;
497
498 struct radeon_bo_list_item *bo_list;
499 unsigned bo_count;
500 };
501
502 struct r600_common_context {
503 struct pipe_context b; /* base class */
504
505 struct r600_common_screen *screen;
506 struct radeon_winsys *ws;
507 struct radeon_winsys_ctx *ctx;
508 enum radeon_family family;
509 enum chip_class chip_class;
510 struct r600_ring gfx;
511 struct r600_ring dma;
512 struct pipe_fence_handle *last_sdma_fence;
513 unsigned initial_gfx_cs_size;
514 unsigned gpu_reset_counter;
515 unsigned last_dirty_fb_counter;
516 unsigned last_compressed_colortex_counter;
517 unsigned last_dirty_tex_descriptor_counter;
518
519 struct u_upload_mgr *uploader;
520 struct u_suballocator *allocator_zeroed_memory;
521 struct util_slab_mempool pool_transfers;
522
523 /* Current unaccounted memory usage. */
524 uint64_t vram;
525 uint64_t gtt;
526
527 /* States. */
528 struct r600_streamout streamout;
529 struct r600_scissors scissors;
530 struct r600_viewports viewports;
531 bool scissor_enabled;
532 bool vs_writes_viewport_index;
533 bool vs_disables_clipping_viewport;
534
535 /* Additional context states. */
536 unsigned flags; /* flush flags */
537
538 /* Queries. */
539 /* Maintain the list of active queries for pausing between IBs. */
540 int num_occlusion_queries;
541 int num_perfect_occlusion_queries;
542 struct list_head active_queries;
543 unsigned num_cs_dw_queries_suspend;
544 /* Additional hardware info. */
545 unsigned backend_mask;
546 unsigned max_db; /* for OQ */
547 /* Misc stats. */
548 unsigned num_draw_calls;
549 unsigned num_spill_draw_calls;
550 unsigned num_compute_calls;
551 unsigned num_spill_compute_calls;
552 unsigned num_dma_calls;
553 uint64_t num_alloc_tex_transfer_bytes;
554 unsigned last_tex_ps_draw_ratio; /* for query */
555
556 /* Render condition. */
557 struct r600_atom render_cond_atom;
558 struct pipe_query *render_cond;
559 unsigned render_cond_mode;
560 bool render_cond_invert;
561 bool render_cond_force_off; /* for u_blitter */
562
563 /* MSAA sample locations.
564 * The first index is the sample index.
565 * The second index is the coordinate: X, Y. */
566 float sample_locations_1x[1][2];
567 float sample_locations_2x[2][2];
568 float sample_locations_4x[4][2];
569 float sample_locations_8x[8][2];
570 float sample_locations_16x[16][2];
571
572 /* Statistics gathering for the DCC enablement heuristic. It can't be
573 * in r600_texture because r600_texture can be shared by multiple
574 * contexts. This is for back buffers only. We shouldn't get too many
575 * of those.
576 *
577 * X11 DRI3 rotates among a finite set of back buffers. They should
578 * all fit in this array. If they don't, separate DCC might never be
579 * enabled by DCC stat gathering.
580 */
581 struct {
582 struct r600_texture *tex;
583 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
584 struct pipe_query *ps_stats[3];
585 /* If all slots are used and another slot is needed,
586 * the least recently used slot is evicted based on this. */
587 int64_t last_use_timestamp;
588 bool query_active;
589 } dcc_stats[5];
590
591 /* The list of all texture buffer objects in this context.
592 * This list is walked when a buffer is invalidated/reallocated and
593 * the GPU addresses are updated. */
594 struct list_head texture_buffers;
595
596 struct pipe_debug_callback debug;
597
598 /* Copy one resource to another using async DMA. */
599 void (*dma_copy)(struct pipe_context *ctx,
600 struct pipe_resource *dst,
601 unsigned dst_level,
602 unsigned dst_x, unsigned dst_y, unsigned dst_z,
603 struct pipe_resource *src,
604 unsigned src_level,
605 const struct pipe_box *src_box);
606
607 void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
608 uint64_t offset, uint64_t size, unsigned value,
609 enum r600_coherency coher);
610
611 void (*blit_decompress_depth)(struct pipe_context *ctx,
612 struct r600_texture *texture,
613 struct r600_texture *staging,
614 unsigned first_level, unsigned last_level,
615 unsigned first_layer, unsigned last_layer,
616 unsigned first_sample, unsigned last_sample);
617
618 void (*decompress_dcc)(struct pipe_context *ctx,
619 struct r600_texture *rtex);
620
621 /* Reallocate the buffer and update all resource bindings where
622 * the buffer is bound, including all resource descriptors. */
623 void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
624
625 /* Enable or disable occlusion queries. */
626 void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
627
628 /* This ensures there is enough space in the command stream. */
629 void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
630 bool include_draw_vbo);
631
632 void (*set_atom_dirty)(struct r600_common_context *ctx,
633 struct r600_atom *atom, bool dirty);
634
635 void (*check_vm_faults)(struct r600_common_context *ctx,
636 struct radeon_saved_cs *saved,
637 enum ring_type ring);
638 };
639
640 /* r600_buffer.c */
641 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
642 struct pb_buffer *buf,
643 enum radeon_bo_usage usage);
644 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
645 struct r600_resource *resource,
646 unsigned usage);
647 bool r600_init_resource(struct r600_common_screen *rscreen,
648 struct r600_resource *res,
649 uint64_t size, unsigned alignment);
650 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
651 const struct pipe_resource *templ,
652 unsigned alignment);
653 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
654 unsigned bind,
655 unsigned usage,
656 unsigned size,
657 unsigned alignment);
658 struct pipe_resource *
659 r600_buffer_from_user_memory(struct pipe_screen *screen,
660 const struct pipe_resource *templ,
661 void *user_memory);
662 void
663 r600_invalidate_resource(struct pipe_context *ctx,
664 struct pipe_resource *resource);
665
666 /* r600_common_pipe.c */
667 void r600_draw_rectangle(struct blitter_context *blitter,
668 int x1, int y1, int x2, int y2, float depth,
669 enum blitter_attrib_type type,
670 const union pipe_color_union *attrib);
671 bool r600_common_screen_init(struct r600_common_screen *rscreen,
672 struct radeon_winsys *ws);
673 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
674 void r600_preflush_suspend_features(struct r600_common_context *ctx);
675 void r600_postflush_resume_features(struct r600_common_context *ctx);
676 bool r600_common_context_init(struct r600_common_context *rctx,
677 struct r600_common_screen *rscreen);
678 void r600_common_context_cleanup(struct r600_common_context *rctx);
679 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
680 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
681 unsigned processor);
682 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
683 uint64_t offset, uint64_t size, unsigned value,
684 enum r600_coherency coher);
685 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
686 const struct pipe_resource *templ);
687 const char *r600_get_llvm_processor_name(enum radeon_family family);
688 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
689 struct r600_resource *dst, struct r600_resource *src);
690 void r600_dma_emit_wait_idle(struct r600_common_context *rctx);
691 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
692 struct radeon_saved_cs *saved);
693 void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
694
695 /* r600_gpu_load.c */
696 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
697 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
698 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
699
700 /* r600_perfcounters.c */
701 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
702
703 /* r600_query.c */
704 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
705 void r600_query_init(struct r600_common_context *rctx);
706 void r600_suspend_queries(struct r600_common_context *ctx);
707 void r600_resume_queries(struct r600_common_context *ctx);
708 void r600_query_init_backend_mask(struct r600_common_context *ctx);
709
710 /* r600_streamout.c */
711 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
712 void r600_set_streamout_targets(struct pipe_context *ctx,
713 unsigned num_targets,
714 struct pipe_stream_output_target **targets,
715 const unsigned *offset);
716 void r600_emit_streamout_end(struct r600_common_context *rctx);
717 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
718 unsigned type, int diff);
719 void r600_streamout_init(struct r600_common_context *rctx);
720
721 /* r600_test_dma.c */
722 void r600_test_dma(struct r600_common_screen *rscreen);
723
724 /* r600_texture.c */
725 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
726 struct r600_texture *rdst,
727 unsigned dst_level, unsigned dstx,
728 unsigned dsty, unsigned dstz,
729 struct r600_texture *rsrc,
730 unsigned src_level,
731 const struct pipe_box *src_box);
732 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
733 struct r600_texture *rtex,
734 unsigned nr_samples,
735 struct r600_fmask_info *out);
736 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
737 struct r600_texture *rtex,
738 struct r600_cmask_info *out);
739 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
740 struct pipe_resource *texture,
741 struct r600_texture **staging);
742 void r600_print_texture_info(struct r600_texture *rtex, FILE *f);
743 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
744 const struct pipe_resource *templ);
745 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
746 struct pipe_resource *texture,
747 const struct pipe_surface *templ,
748 unsigned width, unsigned height);
749 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
750 void vi_separate_dcc_start_query(struct pipe_context *ctx,
751 struct r600_texture *tex);
752 void vi_separate_dcc_stop_query(struct pipe_context *ctx,
753 struct r600_texture *tex);
754 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
755 struct r600_texture *tex);
756 void vi_dcc_clear_level(struct r600_common_context *rctx,
757 struct r600_texture *rtex,
758 unsigned level, unsigned clear_value);
759 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
760 struct pipe_framebuffer_state *fb,
761 struct r600_atom *fb_state,
762 unsigned *buffers, unsigned *dirty_cbufs,
763 const union pipe_color_union *color);
764 bool r600_texture_disable_dcc(struct r600_common_screen *rscreen,
765 struct r600_texture *rtex);
766 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
767 void r600_init_context_texture_functions(struct r600_common_context *rctx);
768
769 /* r600_viewport.c */
770 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
771 struct pipe_scissor_state *scissor);
772 void r600_set_scissor_enable(struct r600_common_context *rctx, bool enable);
773 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
774 struct tgsi_shader_info *info);
775 void r600_init_viewport_functions(struct r600_common_context *rctx);
776
777 /* cayman_msaa.c */
778 extern const uint32_t eg_sample_locs_2x[4];
779 extern const unsigned eg_max_dist_2x;
780 extern const uint32_t eg_sample_locs_4x[4];
781 extern const unsigned eg_max_dist_4x;
782 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
783 unsigned sample_index, float *out_value);
784 void cayman_init_msaa(struct pipe_context *ctx);
785 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
786 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
787 int ps_iter_samples, int overrast_samples,
788 unsigned sc_mode_cntl_1);
789
790
791 /* Inline helpers. */
792
793 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
794 {
795 return (struct r600_resource*)r;
796 }
797
798 static inline void
799 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
800 {
801 pipe_resource_reference((struct pipe_resource **)ptr,
802 (struct pipe_resource *)res);
803 }
804
805 static inline void
806 r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
807 {
808 pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
809 }
810
811 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
812 {
813 return rctx->streamout.streamout_enabled ||
814 rctx->streamout.prims_gen_query_enabled;
815 }
816
817 #define SQ_TEX_XY_FILTER_POINT 0x00
818 #define SQ_TEX_XY_FILTER_BILINEAR 0x01
819 #define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
820 #define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03
821
822 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
823 {
824 if (filter == PIPE_TEX_FILTER_LINEAR)
825 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
826 : SQ_TEX_XY_FILTER_BILINEAR;
827 else
828 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
829 : SQ_TEX_XY_FILTER_POINT;
830 }
831
832 static inline unsigned r600_tex_aniso_filter(unsigned filter)
833 {
834 if (filter < 2)
835 return 0;
836 if (filter < 4)
837 return 1;
838 if (filter < 8)
839 return 2;
840 if (filter < 16)
841 return 3;
842 return 4;
843 }
844
845 static inline unsigned r600_wavefront_size(enum radeon_family family)
846 {
847 switch (family) {
848 case CHIP_RV610:
849 case CHIP_RS780:
850 case CHIP_RV620:
851 case CHIP_RS880:
852 return 16;
853 case CHIP_RV630:
854 case CHIP_RV635:
855 case CHIP_RV730:
856 case CHIP_RV710:
857 case CHIP_PALM:
858 case CHIP_CEDAR:
859 return 32;
860 default:
861 return 64;
862 }
863 }
864
865 static inline enum radeon_bo_priority
866 r600_get_sampler_view_priority(struct r600_resource *res)
867 {
868 if (res->b.b.target == PIPE_BUFFER)
869 return RADEON_PRIO_SAMPLER_BUFFER;
870
871 if (res->b.b.nr_samples > 1)
872 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
873
874 return RADEON_PRIO_SAMPLER_TEXTURE;
875 }
876
877 static inline bool
878 r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
879 {
880 return (stencil_sampler && tex->can_sample_s) ||
881 (!stencil_sampler && tex->can_sample_z);
882 }
883
884 #define COMPUTE_DBG(rscreen, fmt, args...) \
885 do { \
886 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
887 } while (0);
888
889 #define R600_ERR(fmt, args...) \
890 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
891
892 /* For MSAA sample positions. */
893 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
894 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
895 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
896 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
897 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
898
899 #endif