2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
37 #include "radeon/radeon_winsys.h"
39 #include "util/u_blitter.h"
40 #include "util/list.h"
41 #include "util/u_range.h"
42 #include "util/u_slab.h"
43 #include "util/u_suballoc.h"
44 #include "util/u_transfer.h"
46 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
47 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
48 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
50 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
51 #define R600_CONTEXT_PRIVATE_FLAG (1u << 1)
53 /* special primitive types */
54 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
58 #define DBG_TEX (1 << 0)
59 #define DBG_TEXMIP (1 << 1)
60 #define DBG_COMPUTE (1 << 2)
61 #define DBG_VM (1 << 3)
62 #define DBG_TRACE_CS (1 << 4)
64 #define DBG_FS (1 << 5)
65 #define DBG_VS (1 << 6)
66 #define DBG_GS (1 << 7)
67 #define DBG_PS (1 << 8)
68 #define DBG_CS (1 << 9)
69 #define DBG_TCS (1 << 10)
70 #define DBG_TES (1 << 11)
71 #define DBG_NO_IR (1 << 12)
72 #define DBG_NO_TGSI (1 << 13)
73 #define DBG_NO_ASM (1 << 14)
74 /* Bits 21-31 are reserved for the r600g driver. */
76 #define DBG_NO_ASYNC_DMA (1llu << 32)
77 #define DBG_NO_HYPERZ (1llu << 33)
78 #define DBG_NO_DISCARD_RANGE (1llu << 34)
79 #define DBG_NO_2D_TILING (1llu << 35)
80 #define DBG_NO_TILING (1llu << 36)
81 #define DBG_SWITCH_ON_EOP (1llu << 37)
82 #define DBG_FORCE_DMA (1llu << 38)
83 #define DBG_PRECOMPILE (1llu << 39)
84 #define DBG_INFO (1llu << 40)
85 #define DBG_NO_WC (1llu << 41)
86 #define DBG_CHECK_VM (1llu << 42)
87 #define DBG_NO_DCC (1llu << 43)
88 #define DBG_NO_DCC_CLEAR (1llu << 44)
90 #define R600_MAP_BUFFER_ALIGNMENT 64
92 struct r600_common_context
;
93 struct r600_perfcounters
;
95 struct radeon_shader_reloc
{
100 struct radeon_shader_binary
{
105 /** Config/Context register state that accompanies this shader.
106 * This is a stream of dword pairs. First dword contains the
107 * register address, the second dword contains the value.*/
108 unsigned char *config
;
109 unsigned config_size
;
111 /** The number of bytes of config information for each global symbol.
113 unsigned config_size_per_symbol
;
115 /** Constant data accessed by the shader. This will be uploaded
116 * into a constant buffer. */
117 unsigned char *rodata
;
118 unsigned rodata_size
;
120 /** List of symbol offsets for the shader */
121 uint64_t *global_symbol_offsets
;
122 unsigned global_symbol_count
;
124 struct radeon_shader_reloc
*relocs
;
125 unsigned reloc_count
;
127 /** Disassembled shader in a string. */
131 struct r600_resource
{
134 /* Winsys objects. */
135 struct pb_buffer
*buf
;
136 struct radeon_winsys_cs_handle
*cs_buf
;
137 uint64_t gpu_address
;
139 /* Resource state. */
140 enum radeon_bo_domain domains
;
142 /* The buffer range which is initialized (with a write transfer,
143 * streamout, DMA, or as a random access target). The rest of
144 * the buffer is considered invalid and can be mapped unsynchronized.
146 * This allows unsychronized mapping of a buffer range which hasn't
147 * been used yet. It's for applications which forget to use
148 * the unsynchronized map flag and expect the driver to figure it out.
150 struct util_range valid_buffer_range
;
152 /* For buffers only. This indicates that a write operation has been
153 * performed by TC L2, but the cache hasn't been flushed.
154 * Any hw block which doesn't use or bypasses TC L2 should check this
155 * flag and flush the cache before using the buffer.
157 * For example, TC L2 must be flushed if a buffer which has been
158 * modified by a shader store instruction is about to be used as
159 * an index buffer. The reason is that VGT DMA index fetching doesn't
165 struct r600_transfer
{
166 struct pipe_transfer transfer
;
167 struct r600_resource
*staging
;
171 struct r600_fmask_info
{
176 unsigned bank_height
;
177 unsigned slice_tile_max
;
178 unsigned tile_mode_index
;
181 struct r600_cmask_info
{
185 unsigned slice_tile_max
;
186 unsigned base_address_reg
;
189 struct r600_texture
{
190 struct r600_resource resource
;
193 unsigned pitch_override
;
195 unsigned dirty_level_mask
; /* each bit says if that mipmap is compressed */
196 unsigned stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
197 struct r600_texture
*flushed_depth_texture
;
198 boolean is_flushing_texture
;
199 struct radeon_surf surface
;
201 /* Colorbuffer compression and fast clear. */
202 struct r600_fmask_info fmask
;
203 struct r600_cmask_info cmask
;
204 struct r600_resource
*cmask_buffer
;
205 struct r600_resource
*dcc_buffer
;
206 unsigned cb_color_info
; /* fast clear enable bit */
207 unsigned color_clear_value
[2];
209 /* Depth buffer compression and fast clear. */
210 struct r600_resource
*htile_buffer
;
211 bool depth_cleared
; /* if it was cleared at least once */
212 float depth_clear_value
;
214 bool non_disp_tiling
; /* R600-Cayman only */
217 struct r600_surface
{
218 struct pipe_surface base
;
220 bool color_initialized
;
221 bool depth_initialized
;
223 /* Misc. color flags. */
224 bool alphatest_bypass
;
227 /* Color registers. */
228 unsigned cb_color_info
;
229 unsigned cb_color_base
;
230 unsigned cb_color_view
;
231 unsigned cb_color_size
; /* R600 only */
232 unsigned cb_color_dim
; /* EG only */
233 unsigned cb_color_pitch
; /* EG and later */
234 unsigned cb_color_slice
; /* EG and later */
235 unsigned cb_dcc_base
; /* VI and later */
236 unsigned cb_color_attrib
; /* EG and later */
237 unsigned cb_dcc_control
; /* VI and later */
238 unsigned cb_color_fmask
; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
239 unsigned cb_color_fmask_slice
; /* EG and later */
240 unsigned cb_color_cmask
; /* CB_COLORn_TILE (r600 only) */
241 unsigned cb_color_mask
; /* R600 only */
242 struct r600_resource
*cb_buffer_fmask
; /* Used for FMASK relocations. R600 only */
243 struct r600_resource
*cb_buffer_cmask
; /* Used for CMASK relocations. R600 only */
246 unsigned db_depth_info
; /* R600 only, then SI and later */
247 unsigned db_z_info
; /* EG and later */
248 unsigned db_depth_base
; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
249 unsigned db_depth_view
;
250 unsigned db_depth_size
;
251 unsigned db_depth_slice
; /* EG and later */
252 unsigned db_stencil_base
; /* EG and later */
253 unsigned db_stencil_info
; /* EG and later */
254 unsigned db_prefetch_limit
; /* R600 only */
255 unsigned db_htile_surface
;
256 unsigned db_htile_data_base
;
257 unsigned db_preload_control
; /* EG and later */
258 unsigned pa_su_poly_offset_db_fmt_cntl
;
261 struct r600_tiling_info
{
262 unsigned num_channels
;
264 unsigned group_bytes
;
267 struct r600_common_screen
{
268 struct pipe_screen b
;
269 struct radeon_winsys
*ws
;
270 enum radeon_family family
;
271 enum chip_class chip_class
;
272 struct radeon_info info
;
273 struct r600_tiling_info tiling_info
;
274 uint64_t debug_flags
;
278 /* Auxiliary context. Mainly used to initialize resources.
279 * It must be locked prior to using and flushed before unlocking. */
280 struct pipe_context
*aux_context
;
281 pipe_mutex aux_context_lock
;
283 struct r600_resource
*trace_bo
;
287 /* This must be in the screen, because UE4 uses one context for
288 * compilation and another one for rendering.
290 unsigned num_compilations
;
291 /* Along with ST_DEBUG=precompile, this should show if applications
292 * are loading shaders on demand. This is a monotonic counter.
294 unsigned num_shaders_created
;
296 /* GPU load thread. */
297 pipe_mutex gpu_load_mutex
;
298 pipe_thread gpu_load_thread
;
299 unsigned gpu_load_counter_busy
;
300 unsigned gpu_load_counter_idle
;
301 volatile unsigned gpu_load_stop_thread
; /* bool */
303 char renderer_string
[64];
305 /* Performance counters. */
306 struct r600_perfcounters
*perfcounters
;
309 /* This encapsulates a state or an operation which can emitted into the GPU
312 void (*emit
)(struct r600_common_context
*ctx
, struct r600_atom
*state
);
317 struct r600_so_target
{
318 struct pipe_stream_output_target b
;
320 /* The buffer where BUFFER_FILLED_SIZE is stored. */
321 struct r600_resource
*buf_filled_size
;
322 unsigned buf_filled_size_offset
;
323 bool buf_filled_size_valid
;
325 unsigned stride_in_dw
;
328 struct r600_streamout
{
329 struct r600_atom begin_atom
;
331 unsigned num_dw_for_end
;
333 unsigned enabled_mask
;
334 unsigned num_targets
;
335 struct r600_so_target
*targets
[PIPE_MAX_SO_BUFFERS
];
337 unsigned append_bitmask
;
340 /* External state which comes from the vertex shader,
341 * it must be set explicitly when binding a shader. */
342 unsigned *stride_in_dw
;
343 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
345 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
346 unsigned hw_enabled_mask
;
348 /* The state of VGT_STRMOUT_(CONFIG|EN). */
349 struct r600_atom enable_atom
;
350 bool streamout_enabled
;
351 bool prims_gen_query_enabled
;
352 int num_prims_gen_queries
;
356 struct radeon_winsys_cs
*cs
;
357 void (*flush
)(void *ctx
, unsigned flags
,
358 struct pipe_fence_handle
**fence
);
361 struct r600_common_context
{
362 struct pipe_context b
; /* base class */
364 struct r600_common_screen
*screen
;
365 struct radeon_winsys
*ws
;
366 struct radeon_winsys_ctx
*ctx
;
367 enum radeon_family family
;
368 enum chip_class chip_class
;
369 struct r600_ring gfx
;
370 struct r600_ring dma
;
371 struct pipe_fence_handle
*last_sdma_fence
;
372 unsigned initial_gfx_cs_size
;
373 unsigned gpu_reset_counter
;
375 struct u_upload_mgr
*uploader
;
376 struct u_suballocator
*allocator_so_filled_size
;
377 struct util_slab_mempool pool_transfers
;
379 /* Current unaccounted memory usage. */
384 struct r600_streamout streamout
;
386 /* Additional context states. */
387 unsigned flags
; /* flush flags */
390 /* The list of active queries. Only one query of each type can be active. */
391 int num_occlusion_queries
;
392 /* Keep track of non-timer queries, because they should be suspended
393 * during context flushing.
394 * The timer queries (TIME_ELAPSED) shouldn't be suspended for blits,
395 * but they should be suspended between IBs. */
396 struct list_head active_nontimer_queries
;
397 struct list_head active_timer_queries
;
398 unsigned num_cs_dw_nontimer_queries_suspend
;
399 unsigned num_cs_dw_timer_queries_suspend
;
400 /* Additional hardware info. */
401 unsigned backend_mask
;
402 unsigned max_db
; /* for OQ */
404 unsigned num_draw_calls
;
406 /* Render condition. */
407 struct r600_atom render_cond_atom
;
408 struct pipe_query
*render_cond
;
409 unsigned render_cond_mode
;
410 boolean render_cond_invert
;
411 bool render_cond_force_off
; /* for u_blitter */
413 /* MSAA sample locations.
414 * The first index is the sample index.
415 * The second index is the coordinate: X, Y. */
416 float sample_locations_1x
[1][2];
417 float sample_locations_2x
[2][2];
418 float sample_locations_4x
[4][2];
419 float sample_locations_8x
[8][2];
420 float sample_locations_16x
[16][2];
422 /* The list of all texture buffer objects in this context.
423 * This list is walked when a buffer is invalidated/reallocated and
424 * the GPU addresses are updated. */
425 struct list_head texture_buffers
;
427 /* Copy one resource to another using async DMA. */
428 void (*dma_copy
)(struct pipe_context
*ctx
,
429 struct pipe_resource
*dst
,
431 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
432 struct pipe_resource
*src
,
434 const struct pipe_box
*src_box
);
436 void (*clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
437 unsigned offset
, unsigned size
, unsigned value
,
438 bool is_framebuffer
);
440 void (*blit_decompress_depth
)(struct pipe_context
*ctx
,
441 struct r600_texture
*texture
,
442 struct r600_texture
*staging
,
443 unsigned first_level
, unsigned last_level
,
444 unsigned first_layer
, unsigned last_layer
,
445 unsigned first_sample
, unsigned last_sample
);
447 /* Reallocate the buffer and update all resource bindings where
448 * the buffer is bound, including all resource descriptors. */
449 void (*invalidate_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
);
451 /* Enable or disable occlusion queries. */
452 void (*set_occlusion_query_state
)(struct pipe_context
*ctx
, bool enable
);
454 /* This ensures there is enough space in the command stream. */
455 void (*need_gfx_cs_space
)(struct pipe_context
*ctx
, unsigned num_dw
,
456 bool include_draw_vbo
);
458 void (*set_atom_dirty
)(struct r600_common_context
*ctx
,
459 struct r600_atom
*atom
, bool dirty
);
463 boolean
r600_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
464 struct radeon_winsys_cs_handle
*buf
,
465 enum radeon_bo_usage usage
);
466 void *r600_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
467 struct r600_resource
*resource
,
469 bool r600_init_resource(struct r600_common_screen
*rscreen
,
470 struct r600_resource
*res
,
471 unsigned size
, unsigned alignment
,
472 bool use_reusable_pool
);
473 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
474 const struct pipe_resource
*templ
,
476 struct pipe_resource
* r600_aligned_buffer_create(struct pipe_screen
*screen
,
481 struct pipe_resource
*
482 r600_buffer_from_user_memory(struct pipe_screen
*screen
,
483 const struct pipe_resource
*templ
,
486 /* r600_common_pipe.c */
487 void r600_draw_rectangle(struct blitter_context
*blitter
,
488 int x1
, int y1
, int x2
, int y2
, float depth
,
489 enum blitter_attrib_type type
,
490 const union pipe_color_union
*attrib
);
491 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
492 struct radeon_winsys
*ws
);
493 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
);
494 void r600_preflush_suspend_features(struct r600_common_context
*ctx
);
495 void r600_postflush_resume_features(struct r600_common_context
*ctx
);
496 bool r600_common_context_init(struct r600_common_context
*rctx
,
497 struct r600_common_screen
*rscreen
);
498 void r600_common_context_cleanup(struct r600_common_context
*rctx
);
499 void r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
);
500 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
501 const struct tgsi_token
*tokens
);
502 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
503 unsigned offset
, unsigned size
, unsigned value
,
504 bool is_framebuffer
);
505 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
506 const struct pipe_resource
*templ
);
507 const char *r600_get_llvm_processor_name(enum radeon_family family
);
508 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
);
510 /* r600_gpu_load.c */
511 void r600_gpu_load_kill_thread(struct r600_common_screen
*rscreen
);
512 uint64_t r600_gpu_load_begin(struct r600_common_screen
*rscreen
);
513 unsigned r600_gpu_load_end(struct r600_common_screen
*rscreen
, uint64_t begin
);
515 /* r600_perfcounters.c */
516 void r600_perfcounters_destroy(struct r600_common_screen
*rscreen
);
519 void r600_init_screen_query_functions(struct r600_common_screen
*rscreen
);
520 void r600_query_init(struct r600_common_context
*rctx
);
521 void r600_suspend_nontimer_queries(struct r600_common_context
*ctx
);
522 void r600_resume_nontimer_queries(struct r600_common_context
*ctx
);
523 void r600_suspend_timer_queries(struct r600_common_context
*ctx
);
524 void r600_resume_timer_queries(struct r600_common_context
*ctx
);
525 void r600_query_init_backend_mask(struct r600_common_context
*ctx
);
527 /* r600_streamout.c */
528 void r600_streamout_buffers_dirty(struct r600_common_context
*rctx
);
529 void r600_set_streamout_targets(struct pipe_context
*ctx
,
530 unsigned num_targets
,
531 struct pipe_stream_output_target
**targets
,
532 const unsigned *offset
);
533 void r600_emit_streamout_end(struct r600_common_context
*rctx
);
534 void r600_update_prims_generated_query_state(struct r600_common_context
*rctx
,
535 unsigned type
, int diff
);
536 void r600_streamout_init(struct r600_common_context
*rctx
);
539 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
540 struct r600_texture
*rtex
,
542 struct r600_fmask_info
*out
);
543 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
544 struct r600_texture
*rtex
,
545 struct r600_cmask_info
*out
);
546 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
547 struct pipe_resource
*texture
,
548 struct r600_texture
**staging
);
549 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
550 const struct pipe_resource
*templ
);
551 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
552 struct pipe_resource
*texture
,
553 const struct pipe_surface
*templ
,
554 unsigned width
, unsigned height
);
555 unsigned r600_translate_colorswap(enum pipe_format format
);
556 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
557 struct pipe_framebuffer_state
*fb
,
558 struct r600_atom
*fb_state
,
559 unsigned *buffers
, unsigned *dirty_cbufs
,
560 const union pipe_color_union
*color
);
561 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
);
562 void r600_init_context_texture_functions(struct r600_common_context
*rctx
);
565 extern const uint32_t eg_sample_locs_2x
[4];
566 extern const unsigned eg_max_dist_2x
;
567 extern const uint32_t eg_sample_locs_4x
[4];
568 extern const unsigned eg_max_dist_4x
;
569 void cayman_get_sample_position(struct pipe_context
*ctx
, unsigned sample_count
,
570 unsigned sample_index
, float *out_value
);
571 void cayman_init_msaa(struct pipe_context
*ctx
);
572 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
573 void cayman_emit_msaa_config(struct radeon_winsys_cs
*cs
, int nr_samples
,
574 int ps_iter_samples
, int overrast_samples
);
577 /* Inline helpers. */
579 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
581 return (struct r600_resource
*)r
;
585 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
587 pipe_resource_reference((struct pipe_resource
**)ptr
,
588 (struct pipe_resource
*)res
);
591 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
593 if (filter
<= 1) return 0;
594 if (filter
<= 2) return 1;
595 if (filter
<= 4) return 2;
596 if (filter
<= 8) return 3;
600 static inline unsigned r600_wavefront_size(enum radeon_family family
)
620 static inline enum radeon_bo_priority
621 r600_get_sampler_view_priority(struct r600_resource
*res
)
623 if (res
->b
.b
.target
== PIPE_BUFFER
)
624 return RADEON_PRIO_SAMPLER_BUFFER
;
626 if (res
->b
.b
.nr_samples
> 1)
627 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
629 return RADEON_PRIO_SAMPLER_TEXTURE
;
632 #define COMPUTE_DBG(rscreen, fmt, args...) \
634 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
637 #define R600_ERR(fmt, args...) \
638 fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
640 /* For MSAA sample positions. */
641 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
642 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
643 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
644 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
645 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))