src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/u_slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  47 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  48 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  49
  50 #define R600_QUERY_DRAW_CALLS           (PIPE_QUERY_DRIVER_SPECIFIC + 0)
  51 #define R600_QUERY_REQUESTED_VRAM       (PIPE_QUERY_DRIVER_SPECIFIC + 1)
  52 #define R600_QUERY_REQUESTED_GTT        (PIPE_QUERY_DRIVER_SPECIFIC + 2)
  53 #define R600_QUERY_BUFFER_WAIT_TIME     (PIPE_QUERY_DRIVER_SPECIFIC + 3)
  54 #define R600_QUERY_NUM_CS_FLUSHES       (PIPE_QUERY_DRIVER_SPECIFIC + 4)
  55 #define R600_QUERY_NUM_BYTES_MOVED      (PIPE_QUERY_DRIVER_SPECIFIC + 5)
  56 #define R600_QUERY_VRAM_USAGE           (PIPE_QUERY_DRIVER_SPECIFIC + 6)
  57 #define R600_QUERY_GTT_USAGE            (PIPE_QUERY_DRIVER_SPECIFIC + 7)
  58 #define R600_QUERY_GPU_TEMPERATURE      (PIPE_QUERY_DRIVER_SPECIFIC + 8)
  59 #define R600_QUERY_CURRENT_GPU_SCLK     (PIPE_QUERY_DRIVER_SPECIFIC + 9)
  60 #define R600_QUERY_CURRENT_GPU_MCLK     (PIPE_QUERY_DRIVER_SPECIFIC + 10)
  61 #define R600_QUERY_GPU_LOAD             (PIPE_QUERY_DRIVER_SPECIFIC + 11)
  62 #define R600_QUERY_NUM_COMPILATIONS     (PIPE_QUERY_DRIVER_SPECIFIC + 12)
  63 #define R600_QUERY_NUM_SHADERS_CREATED  (PIPE_QUERY_DRIVER_SPECIFIC + 13)
  64
  65 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  66 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 1)
  67
  68 /* special primitive types */
  69 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  70
  71 /* Debug flags. */
  72 /* logging */
  73 #define DBG_TEX                 (1 << 0)
  74 #define DBG_TEXMIP              (1 << 1)
  75 #define DBG_COMPUTE             (1 << 2)
  76 #define DBG_VM                  (1 << 3)
  77 #define DBG_TRACE_CS            (1 << 4)
  78 /* shader logging */
  79 #define DBG_FS                  (1 << 5)
  80 #define DBG_VS                  (1 << 6)
  81 #define DBG_GS                  (1 << 7)
  82 #define DBG_PS                  (1 << 8)
  83 #define DBG_CS                  (1 << 9)
  84 #define DBG_TCS                 (1 << 10)
  85 #define DBG_TES                 (1 << 11)
  86 #define DBG_NO_IR               (1 << 12)
  87 #define DBG_NO_TGSI             (1 << 13)
  88 #define DBG_NO_ASM              (1 << 14)
  89 /* Bits 21-31 are reserved for the r600g driver. */
  90 /* features */
  91 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  92 #define DBG_NO_HYPERZ           (1llu << 33)
  93 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  94 #define DBG_NO_2D_TILING        (1llu << 35)
  95 #define DBG_NO_TILING           (1llu << 36)
  96 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  97 #define DBG_FORCE_DMA           (1llu << 38)
  98 #define DBG_PRECOMPILE          (1llu << 39)
  99 #define DBG_INFO                (1llu << 40)
 100 #define DBG_NO_WC               (1llu << 41)
 101
 102 #define R600_MAP_BUFFER_ALIGNMENT 64
 103
 104 struct r600_common_context;
 105
 106 struct radeon_shader_reloc {
 107         char *name;
 108         uint64_t offset;
 109 };
 110
 111 struct radeon_shader_binary {
 112         /** Shader code */
 113         unsigned char *code;
 114         unsigned code_size;
 115
 116         /** Config/Context register state that accompanies this shader.
 117          * This is a stream of dword pairs.  First dword contains the
 118          * register address, the second dword contains the value.*/
 119         unsigned char *config;
 120         unsigned config_size;
 121
 122         /** The number of bytes of config information for each global symbol.
 123          */
 124         unsigned config_size_per_symbol;
 125
 126         /** Constant data accessed by the shader.  This will be uploaded
 127          * into a constant buffer. */
 128         unsigned char *rodata;
 129         unsigned rodata_size;
 130
 131         /** List of symbol offsets for the shader */
 132         uint64_t *global_symbol_offsets;
 133         unsigned global_symbol_count;
 134
 135         struct radeon_shader_reloc *relocs;
 136         unsigned reloc_count;
 137
 138         /** Disassembled shader in a string. */
 139         char *disasm_string;
 140 };
 141
 142 struct r600_resource {
 143         struct u_resource               b;
 144
 145         /* Winsys objects. */
 146         struct pb_buffer                *buf;
 147         struct radeon_winsys_cs_handle  *cs_buf;
 148         uint64_t                        gpu_address;
 149
 150         /* Resource state. */
 151         enum radeon_bo_domain           domains;
 152
 153         /* The buffer range which is initialized (with a write transfer,
 154          * streamout, DMA, or as a random access target). The rest of
 155          * the buffer is considered invalid and can be mapped unsynchronized.
 156          *
 157          * This allows unsychronized mapping of a buffer range which hasn't
 158          * been used yet. It's for applications which forget to use
 159          * the unsynchronized map flag and expect the driver to figure it out.
 160          */
 161         struct util_range               valid_buffer_range;
 162
 163         /* For buffers only. This indicates that a write operation has been
 164          * performed by TC L2, but the cache hasn't been flushed.
 165          * Any hw block which doesn't use or bypasses TC L2 should check this
 166          * flag and flush the cache before using the buffer.
 167          *
 168          * For example, TC L2 must be flushed if a buffer which has been
 169          * modified by a shader store instruction is about to be used as
 170          * an index buffer. The reason is that VGT DMA index fetching doesn't
 171          * use TC L2.
 172          */
 173         bool                            TC_L2_dirty;
 174 };
 175
 176 struct r600_transfer {
 177         struct pipe_transfer            transfer;
 178         struct r600_resource            *staging;
 179         unsigned                        offset;
 180 };
 181
 182 struct r600_fmask_info {
 183         unsigned offset;
 184         unsigned size;
 185         unsigned alignment;
 186         unsigned pitch;
 187         unsigned bank_height;
 188         unsigned slice_tile_max;
 189         unsigned tile_mode_index;
 190 };
 191
 192 struct r600_cmask_info {
 193         unsigned offset;
 194         unsigned size;
 195         unsigned alignment;
 196         unsigned slice_tile_max;
 197         unsigned base_address_reg;
 198 };
 199
 200 struct r600_texture {
 201         struct r600_resource            resource;
 202
 203         unsigned                        size;
 204         unsigned                        pitch_override;
 205         bool                            is_depth;
 206         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 207         struct r600_texture             *flushed_depth_texture;
 208         boolean                         is_flushing_texture;
 209         struct radeon_surf              surface;
 210
 211         /* Colorbuffer compression and fast clear. */
 212         struct r600_fmask_info          fmask;
 213         struct r600_cmask_info          cmask;
 214         struct r600_resource            *cmask_buffer;
 215         unsigned                        cb_color_info; /* fast clear enable bit */
 216         unsigned                        color_clear_value[2];
 217
 218         /* Depth buffer compression and fast clear. */
 219         struct r600_resource            *htile_buffer;
 220         bool                            depth_cleared; /* if it was cleared at least once */
 221         float                           depth_clear_value;
 222
 223         bool                            non_disp_tiling; /* R600-Cayman only */
 224 };
 225
 226 struct r600_surface {
 227         struct pipe_surface             base;
 228
 229         bool color_initialized;
 230         bool depth_initialized;
 231
 232         /* Misc. color flags. */
 233         bool alphatest_bypass;
 234         bool export_16bpc;
 235
 236         /* Color registers. */
 237         unsigned cb_color_info;
 238         unsigned cb_color_base;
 239         unsigned cb_color_view;
 240         unsigned cb_color_size;         /* R600 only */
 241         unsigned cb_color_dim;          /* EG only */
 242         unsigned cb_color_pitch;        /* EG and later */
 243         unsigned cb_color_slice;        /* EG and later */
 244         unsigned cb_color_attrib;       /* EG and later */
 245         unsigned cb_dcc_control;        /* VI and later */
 246         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 247         unsigned cb_color_fmask_slice;  /* EG and later */
 248         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 249         unsigned cb_color_mask;         /* R600 only */
 250         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 251         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 252
 253         /* DB registers. */
 254         unsigned db_depth_info;         /* R600 only, then SI and later */
 255         unsigned db_z_info;             /* EG and later */
 256         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 257         unsigned db_depth_view;
 258         unsigned db_depth_size;
 259         unsigned db_depth_slice;        /* EG and later */
 260         unsigned db_stencil_base;       /* EG and later */
 261         unsigned db_stencil_info;       /* EG and later */
 262         unsigned db_prefetch_limit;     /* R600 only */
 263         unsigned db_htile_surface;
 264         unsigned db_htile_data_base;
 265         unsigned db_preload_control;    /* EG and later */
 266         unsigned pa_su_poly_offset_db_fmt_cntl;
 267 };
 268
 269 struct r600_tiling_info {
 270         unsigned num_channels;
 271         unsigned num_banks;
 272         unsigned group_bytes;
 273 };
 274
 275 struct r600_common_screen {
 276         struct pipe_screen              b;
 277         struct radeon_winsys            *ws;
 278         enum radeon_family              family;
 279         enum chip_class                 chip_class;
 280         struct radeon_info              info;
 281         struct r600_tiling_info         tiling_info;
 282         uint64_t                        debug_flags;
 283         bool                            has_cp_dma;
 284         bool                            has_streamout;
 285
 286         /* Auxiliary context. Mainly used to initialize resources.
 287          * It must be locked prior to using and flushed before unlocking. */
 288         struct pipe_context             *aux_context;
 289         pipe_mutex                      aux_context_lock;
 290
 291         struct r600_resource            *trace_bo;
 292         uint32_t                        *trace_ptr;
 293         unsigned                        cs_count;
 294
 295         /* This must be in the screen, because UE4 uses one context for
 296          * compilation and another one for rendering.
 297          */
 298         unsigned                        num_compilations;
 299         /* Along with ST_DEBUG=precompile, this should show if applications
 300          * are loading shaders on demand. This is a monotonic counter.
 301          */
 302         unsigned                        num_shaders_created;
 303
 304         /* GPU load thread. */
 305         pipe_mutex                      gpu_load_mutex;
 306         pipe_thread                     gpu_load_thread;
 307         unsigned                        gpu_load_counter_busy;
 308         unsigned                        gpu_load_counter_idle;
 309         volatile unsigned               gpu_load_stop_thread; /* bool */
 310
 311         char                            renderer_string[64];
 312 };
 313
 314 /* This encapsulates a state or an operation which can emitted into the GPU
 315  * command stream. */
 316 struct r600_atom {
 317         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 318         unsigned                num_dw;
 319         unsigned short          id;     /* used by r600 only */
 320         bool                    dirty;
 321 };
 322
 323 struct r600_so_target {
 324         struct pipe_stream_output_target b;
 325
 326         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 327         struct r600_resource    *buf_filled_size;
 328         unsigned                buf_filled_size_offset;
 329         bool                    buf_filled_size_valid;
 330
 331         unsigned                stride_in_dw;
 332 };
 333
 334 struct r600_streamout {
 335         struct r600_atom                begin_atom;
 336         bool                            begin_emitted;
 337         unsigned                        num_dw_for_end;
 338
 339         unsigned                        enabled_mask;
 340         unsigned                        num_targets;
 341         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 342
 343         unsigned                        append_bitmask;
 344         bool                            suspended;
 345
 346         /* External state which comes from the vertex shader,
 347          * it must be set explicitly when binding a shader. */
 348         unsigned                        *stride_in_dw;
 349         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 350
 351         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 352         unsigned                        hw_enabled_mask;
 353
 354         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 355         struct r600_atom                enable_atom;
 356         bool                            streamout_enabled;
 357         bool                            prims_gen_query_enabled;
 358         int                             num_prims_gen_queries;
 359 };
 360
 361 struct r600_ring {
 362         struct radeon_winsys_cs         *cs;
 363         bool                            flushing;
 364         void (*flush)(void *ctx, unsigned flags,
 365                       struct pipe_fence_handle **fence);
 366 };
 367
 368 struct r600_rings {
 369         struct r600_ring                gfx;
 370         struct r600_ring                dma;
 371 };
 372
 373 struct r600_common_context {
 374         struct pipe_context b; /* base class */
 375
 376         struct r600_common_screen       *screen;
 377         struct radeon_winsys            *ws;
 378         struct radeon_winsys_ctx        *ctx;
 379         enum radeon_family              family;
 380         enum chip_class                 chip_class;
 381         struct r600_rings               rings;
 382         unsigned                        initial_gfx_cs_size;
 383         unsigned                        gpu_reset_counter;
 384
 385         struct u_upload_mgr             *uploader;
 386         struct u_suballocator           *allocator_so_filled_size;
 387         struct util_slab_mempool        pool_transfers;
 388
 389         /* Current unaccounted memory usage. */
 390         uint64_t                        vram;
 391         uint64_t                        gtt;
 392
 393         /* States. */
 394         struct r600_streamout           streamout;
 395
 396         /* Additional context states. */
 397         unsigned flags; /* flush flags */
 398
 399         /* Queries. */
 400         /* The list of active queries. Only one query of each type can be active. */
 401         int                             num_occlusion_queries;
 402         /* Keep track of non-timer queries, because they should be suspended
 403          * during context flushing.
 404          * The timer queries (TIME_ELAPSED) shouldn't be suspended for blits,
 405          * but they should be suspended between IBs. */
 406         struct list_head                active_nontimer_queries;
 407         struct list_head                active_timer_queries;
 408         unsigned                        num_cs_dw_nontimer_queries_suspend;
 409         unsigned                        num_cs_dw_timer_queries_suspend;
 410         /* If queries have been suspended. */
 411         bool                            queries_suspended_for_flush;
 412         /* Additional hardware info. */
 413         unsigned                        backend_mask;
 414         unsigned                        max_db; /* for OQ */
 415         /* Misc stats. */
 416         unsigned                        num_draw_calls;
 417
 418         /* Render condition. */
 419         struct pipe_query               *current_render_cond;
 420         unsigned                        current_render_cond_mode;
 421         boolean                         current_render_cond_cond;
 422         boolean                         predicate_drawing;
 423         /* For context flushing. */
 424         struct pipe_query               *saved_render_cond;
 425         boolean                         saved_render_cond_cond;
 426         unsigned                        saved_render_cond_mode;
 427
 428         /* MSAA sample locations.
 429          * The first index is the sample index.
 430          * The second index is the coordinate: X, Y. */
 431         float                           sample_locations_1x[1][2];
 432         float                           sample_locations_2x[2][2];
 433         float                           sample_locations_4x[4][2];
 434         float                           sample_locations_8x[8][2];
 435         float                           sample_locations_16x[16][2];
 436
 437         /* The list of all texture buffer objects in this context.
 438          * This list is walked when a buffer is invalidated/reallocated and
 439          * the GPU addresses are updated. */
 440         struct list_head                texture_buffers;
 441
 442         /* Copy one resource to another using async DMA. */
 443         void (*dma_copy)(struct pipe_context *ctx,
 444                          struct pipe_resource *dst,
 445                          unsigned dst_level,
 446                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 447                          struct pipe_resource *src,
 448                          unsigned src_level,
 449                          const struct pipe_box *src_box);
 450
 451         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 452                              unsigned offset, unsigned size, unsigned value,
 453                              bool is_framebuffer);
 454
 455         void (*blit_decompress_depth)(struct pipe_context *ctx,
 456                                       struct r600_texture *texture,
 457                                       struct r600_texture *staging,
 458                                       unsigned first_level, unsigned last_level,
 459                                       unsigned first_layer, unsigned last_layer,
 460                                       unsigned first_sample, unsigned last_sample);
 461
 462         /* Reallocate the buffer and update all resource bindings where
 463          * the buffer is bound, including all resource descriptors. */
 464         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 465
 466         /* Enable or disable occlusion queries. */
 467         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 468
 469         /* This ensures there is enough space in the command stream. */
 470         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 471                                   bool include_draw_vbo);
 472
 473         void (*set_atom_dirty)(struct r600_common_context *ctx,
 474                                struct r600_atom *atom, bool dirty);
 475 };
 476
 477 /* r600_buffer.c */
 478 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 479                                         struct radeon_winsys_cs_handle *buf,
 480                                         enum radeon_bo_usage usage);
 481 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 482                                       struct r600_resource *resource,
 483                                       unsigned usage);
 484 bool r600_init_resource(struct r600_common_screen *rscreen,
 485                         struct r600_resource *res,
 486                         unsigned size, unsigned alignment,
 487                         bool use_reusable_pool);
 488 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 489                                          const struct pipe_resource *templ,
 490                                          unsigned alignment);
 491 struct pipe_resource *
 492 r600_buffer_from_user_memory(struct pipe_screen *screen,
 493                              const struct pipe_resource *templ,
 494                              void *user_memory);
 495
 496 /* r600_common_pipe.c */
 497 void r600_draw_rectangle(struct blitter_context *blitter,
 498                          int x1, int y1, int x2, int y2, float depth,
 499                          enum blitter_attrib_type type,
 500                          const union pipe_color_union *attrib);
 501 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 502                              struct radeon_winsys *ws);
 503 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 504 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 505 void r600_postflush_resume_features(struct r600_common_context *ctx);
 506 bool r600_common_context_init(struct r600_common_context *rctx,
 507                               struct r600_common_screen *rscreen);
 508 void r600_common_context_cleanup(struct r600_common_context *rctx);
 509 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 510 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 511                           const struct tgsi_token *tokens);
 512 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 513                               unsigned offset, unsigned size, unsigned value,
 514                               bool is_framebuffer);
 515 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 516                                                   const struct pipe_resource *templ);
 517 const char *r600_get_llvm_processor_name(enum radeon_family family);
 518 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw);
 519
 520 /* r600_gpu_load.c */
 521 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 522 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
 523 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 524
 525 /* r600_query.c */
 526 void r600_query_init(struct r600_common_context *rctx);
 527 void r600_suspend_nontimer_queries(struct r600_common_context *ctx);
 528 void r600_resume_nontimer_queries(struct r600_common_context *ctx);
 529 void r600_suspend_timer_queries(struct r600_common_context *ctx);
 530 void r600_resume_timer_queries(struct r600_common_context *ctx);
 531 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 532
 533 /* r600_streamout.c */
 534 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 535 void r600_set_streamout_targets(struct pipe_context *ctx,
 536                                 unsigned num_targets,
 537                                 struct pipe_stream_output_target **targets,
 538                                 const unsigned *offset);
 539 void r600_emit_streamout_end(struct r600_common_context *rctx);
 540 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 541                                              unsigned type, int diff);
 542 void r600_streamout_init(struct r600_common_context *rctx);
 543
 544 /* r600_texture.c */
 545 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 546                                  struct r600_texture *rtex,
 547                                  unsigned nr_samples,
 548                                  struct r600_fmask_info *out);
 549 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 550                                  struct r600_texture *rtex,
 551                                  struct r600_cmask_info *out);
 552 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 553                                      struct pipe_resource *texture,
 554                                      struct r600_texture **staging);
 555 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 556                                         const struct pipe_resource *templ);
 557 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 558                                                 struct pipe_resource *texture,
 559                                                 const struct pipe_surface *templ,
 560                                                 unsigned width, unsigned height);
 561 unsigned r600_translate_colorswap(enum pipe_format format);
 562 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 563                                    struct pipe_framebuffer_state *fb,
 564                                    struct r600_atom *fb_state,
 565                                    unsigned *buffers,
 566                                    const union pipe_color_union *color);
 567 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 568 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 569
 570 /* cayman_msaa.c */
 571 extern const uint32_t eg_sample_locs_2x[4];
 572 extern const unsigned eg_max_dist_2x;
 573 extern const uint32_t eg_sample_locs_4x[4];
 574 extern const unsigned eg_max_dist_4x;
 575 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 576                                 unsigned sample_index, float *out_value);
 577 void cayman_init_msaa(struct pipe_context *ctx);
 578 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 579 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 580                              int ps_iter_samples, int overrast_samples);
 581
 582
 583 /* Inline helpers. */
 584
 585 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 586 {
 587         return (struct r600_resource*)r;
 588 }
 589
 590 static inline void
 591 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 592 {
 593         pipe_resource_reference((struct pipe_resource **)ptr,
 594                                 (struct pipe_resource *)res);
 595 }
 596
 597 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 598 {
 599         if (filter <= 1)   return 0;
 600         if (filter <= 2)   return 1;
 601         if (filter <= 4)   return 2;
 602         if (filter <= 8)   return 3;
 603          /* else */        return 4;
 604 }
 605
 606 static inline unsigned r600_wavefront_size(enum radeon_family family)
 607 {
 608         switch (family) {
 609         case CHIP_RV610:
 610         case CHIP_RS780:
 611         case CHIP_RV620:
 612         case CHIP_RS880:
 613                 return 16;
 614         case CHIP_RV630:
 615         case CHIP_RV635:
 616         case CHIP_RV730:
 617         case CHIP_RV710:
 618         case CHIP_PALM:
 619         case CHIP_CEDAR:
 620                 return 32;
 621         default:
 622                 return 64;
 623         }
 624 }
 625
 626 #define COMPUTE_DBG(rscreen, fmt, args...) \
 627         do { \
 628                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 629         } while (0);
 630
 631 #define R600_ERR(fmt, args...) \
 632         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
 633
 634 /* For MSAA sample positions. */
 635 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 636         (((s0x) & 0xf) | (((s0y) & 0xf) << 4) |            \
 637         (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |     \
 638         (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |    \
 639          (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
 640
 641 #endif