radeonsi: inline util_blitter_copy_texture
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.h
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 /**
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
30 */
31
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
34
35 #include <stdio.h>
36
37 #include "../../winsys/radeon/drm/radeon_winsys.h"
38
39 #include "util/u_double_list.h"
40 #include "util/u_range.h"
41 #include "util/u_slab.h"
42 #include "util/u_suballoc.h"
43 #include "util/u_transfer.h"
44
45 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
46 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
47 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
48
49 #define R600_QUERY_DRAW_CALLS (PIPE_QUERY_DRIVER_SPECIFIC + 0)
50 #define R600_QUERY_REQUESTED_VRAM (PIPE_QUERY_DRIVER_SPECIFIC + 1)
51 #define R600_QUERY_REQUESTED_GTT (PIPE_QUERY_DRIVER_SPECIFIC + 2)
52 #define R600_QUERY_BUFFER_WAIT_TIME (PIPE_QUERY_DRIVER_SPECIFIC + 3)
53
54 /* read caches */
55 #define R600_CONTEXT_INV_VERTEX_CACHE (1 << 0)
56 #define R600_CONTEXT_INV_TEX_CACHE (1 << 1)
57 #define R600_CONTEXT_INV_CONST_CACHE (1 << 2)
58 #define R600_CONTEXT_INV_SHADER_CACHE (1 << 3)
59 /* read-write caches */
60 #define R600_CONTEXT_STREAMOUT_FLUSH (1 << 8)
61 #define R600_CONTEXT_FLUSH_AND_INV (1 << 9)
62 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (1 << 10)
63 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (1 << 11)
64 #define R600_CONTEXT_FLUSH_AND_INV_DB (1 << 12)
65 #define R600_CONTEXT_FLUSH_AND_INV_CB (1 << 13)
66 /* engine synchronization */
67 #define R600_CONTEXT_PS_PARTIAL_FLUSH (1 << 16)
68 #define R600_CONTEXT_WAIT_3D_IDLE (1 << 17)
69 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (1 << 18)
70 #define R600_CONTEXT_VGT_FLUSH (1 << 19)
71
72 /* Debug flags. */
73 /* logging */
74 #define DBG_TEX (1 << 0)
75 #define DBG_TEXMIP (1 << 1)
76 #define DBG_COMPUTE (1 << 2)
77 #define DBG_VM (1 << 3)
78 #define DBG_TRACE_CS (1 << 4)
79 /* shaders */
80 #define DBG_FS (1 << 8)
81 #define DBG_VS (1 << 9)
82 #define DBG_GS (1 << 10)
83 #define DBG_PS (1 << 11)
84 #define DBG_CS (1 << 12)
85 /* features */
86 #define DBG_HYPERZ (1 << 13)
87 #define DBG_NO_DISCARD_RANGE (1 << 14)
88 /* The maximum allowed bit is 15. */
89
90 #define R600_MAP_BUFFER_ALIGNMENT 64
91
92 struct r600_common_context;
93
94 struct r600_resource {
95 struct u_resource b;
96
97 /* Winsys objects. */
98 struct pb_buffer *buf;
99 struct radeon_winsys_cs_handle *cs_buf;
100
101 /* Resource state. */
102 enum radeon_bo_domain domains;
103
104 /* The buffer range which is initialized (with a write transfer,
105 * streamout, DMA, or as a random access target). The rest of
106 * the buffer is considered invalid and can be mapped unsynchronized.
107 *
108 * This allows unsychronized mapping of a buffer range which hasn't
109 * been used yet. It's for applications which forget to use
110 * the unsynchronized map flag and expect the driver to figure it out.
111 */
112 struct util_range valid_buffer_range;
113 };
114
115 struct r600_transfer {
116 struct pipe_transfer transfer;
117 struct r600_resource *staging;
118 unsigned offset;
119 };
120
121 struct r600_fmask_info {
122 unsigned offset;
123 unsigned size;
124 unsigned alignment;
125 unsigned pitch;
126 unsigned bank_height;
127 unsigned slice_tile_max;
128 unsigned tile_mode_index;
129 };
130
131 struct r600_cmask_info {
132 unsigned offset;
133 unsigned size;
134 unsigned alignment;
135 unsigned slice_tile_max;
136 };
137
138 struct r600_texture {
139 struct r600_resource resource;
140
141 unsigned size;
142 unsigned pitch_override;
143 bool is_depth;
144 unsigned dirty_level_mask; /* each bit says if that mipmap is compressed */
145 struct r600_texture *flushed_depth_texture;
146 boolean is_flushing_texture;
147 struct radeon_surface surface;
148
149 /* Colorbuffer compression and fast clear. */
150 struct r600_fmask_info fmask;
151 struct r600_cmask_info cmask;
152 struct r600_resource *cmask_buffer;
153 unsigned color_clear_value[2];
154
155 /* Depth buffer compression and fast clear. */
156 struct r600_resource *htile_buffer;
157 float depth_clear_value;
158
159 bool non_disp_tiling; /* R600-Cayman only */
160 unsigned mipmap_shift;
161 };
162
163 struct r600_surface {
164 struct pipe_surface base;
165
166 bool color_initialized;
167 bool depth_initialized;
168
169 /* Misc. color flags. */
170 bool alphatest_bypass;
171 bool export_16bpc;
172
173 /* Color registers. */
174 unsigned cb_color_info;
175 unsigned cb_color_base;
176 unsigned cb_color_view;
177 unsigned cb_color_size; /* R600 only */
178 unsigned cb_color_dim; /* EG only */
179 unsigned cb_color_pitch; /* EG and later */
180 unsigned cb_color_slice; /* EG and later */
181 unsigned cb_color_attrib; /* EG and later */
182 unsigned cb_color_fmask; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
183 unsigned cb_color_fmask_slice; /* EG and later */
184 unsigned cb_color_cmask; /* CB_COLORn_CMASK (EG and later) or CB_COLORn_TILE (r600) */
185 unsigned cb_color_cmask_slice; /* EG and later */
186 unsigned cb_color_mask; /* R600 only */
187 struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
188 struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
189
190 /* DB registers. */
191 unsigned db_depth_info; /* R600 only, then SI and later */
192 unsigned db_z_info; /* EG and later */
193 unsigned db_depth_base; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
194 unsigned db_depth_view;
195 unsigned db_depth_size;
196 unsigned db_depth_slice; /* EG and later */
197 unsigned db_stencil_base; /* EG and later */
198 unsigned db_stencil_info; /* EG and later */
199 unsigned db_prefetch_limit; /* R600 only */
200 unsigned db_htile_surface;
201 unsigned db_htile_data_base;
202 unsigned db_preload_control; /* EG and later */
203 unsigned pa_su_poly_offset_db_fmt_cntl;
204 };
205
206 struct r600_tiling_info {
207 unsigned num_channels;
208 unsigned num_banks;
209 unsigned group_bytes;
210 };
211
212 struct r600_common_screen {
213 struct pipe_screen b;
214 struct radeon_winsys *ws;
215 enum radeon_family family;
216 enum chip_class chip_class;
217 struct radeon_info info;
218 struct r600_tiling_info tiling_info;
219 unsigned debug_flags;
220 bool has_cp_dma;
221 bool has_streamout;
222
223 /* Auxiliary context. Mainly used to initialize resources.
224 * It must be locked prior to using and flushed before unlocking. */
225 struct pipe_context *aux_context;
226 pipe_mutex aux_context_lock;
227
228 struct r600_resource *trace_bo;
229 uint32_t *trace_ptr;
230 unsigned cs_count;
231 };
232
233 /* This encapsulates a state or an operation which can emitted into the GPU
234 * command stream. */
235 struct r600_atom {
236 void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
237 unsigned num_dw;
238 bool dirty;
239 };
240
241 struct r600_so_target {
242 struct pipe_stream_output_target b;
243
244 /* The buffer where BUFFER_FILLED_SIZE is stored. */
245 struct r600_resource *buf_filled_size;
246 unsigned buf_filled_size_offset;
247
248 unsigned stride_in_dw;
249 };
250
251 struct r600_streamout {
252 struct r600_atom begin_atom;
253 bool begin_emitted;
254 unsigned num_dw_for_end;
255
256 unsigned enabled_mask;
257 unsigned num_targets;
258 struct r600_so_target *targets[PIPE_MAX_SO_BUFFERS];
259
260 unsigned append_bitmask;
261 bool suspended;
262
263 /* External state which comes from the vertex shader,
264 * it must be set explicitly when binding a shader. */
265 unsigned *stride_in_dw;
266 };
267
268 struct r600_ring {
269 struct radeon_winsys_cs *cs;
270 bool flushing;
271 void (*flush)(void *ctx, unsigned flags);
272 };
273
274 struct r600_rings {
275 struct r600_ring gfx;
276 struct r600_ring dma;
277 };
278
279 struct r600_common_context {
280 struct pipe_context b; /* base class */
281
282 struct r600_common_screen *screen;
283 struct radeon_winsys *ws;
284 enum radeon_family family;
285 enum chip_class chip_class;
286 struct r600_rings rings;
287 unsigned initial_gfx_cs_size;
288
289 struct u_upload_mgr *uploader;
290 struct u_suballocator *allocator_so_filled_size;
291 struct util_slab_mempool pool_transfers;
292
293 /* Current unaccounted memory usage. */
294 uint64_t vram;
295 uint64_t gtt;
296
297 /* States. */
298 struct r600_streamout streamout;
299
300 /* Additional context states. */
301 unsigned flags; /* flush flags */
302
303 /* Queries. */
304 /* The list of active queries. Only one query of each type can be active. */
305 int num_occlusion_queries;
306 int num_pipelinestat_queries;
307 /* Keep track of non-timer queries, because they should be suspended
308 * during context flushing.
309 * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
310 struct list_head active_nontimer_queries;
311 unsigned num_cs_dw_nontimer_queries_suspend;
312 /* If queries have been suspended. */
313 bool nontimer_queries_suspended;
314 /* Additional hardware info. */
315 unsigned backend_mask;
316 unsigned max_db; /* for OQ */
317 /* Misc stats. */
318 unsigned num_draw_calls;
319
320 /* Render condition. */
321 struct pipe_query *current_render_cond;
322 unsigned current_render_cond_mode;
323 boolean current_render_cond_cond;
324 boolean predicate_drawing;
325
326 /* Copy one resource to another using async DMA.
327 * False is returned if the copy couldn't be done. */
328 boolean (*dma_copy)(struct pipe_context *ctx,
329 struct pipe_resource *dst,
330 unsigned dst_level,
331 unsigned dst_x, unsigned dst_y, unsigned dst_z,
332 struct pipe_resource *src,
333 unsigned src_level,
334 const struct pipe_box *src_box);
335
336 void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
337 unsigned offset, unsigned size, unsigned value);
338
339 void (*blit_decompress_depth)(struct pipe_context *ctx,
340 struct r600_texture *texture,
341 struct r600_texture *staging,
342 unsigned first_level, unsigned last_level,
343 unsigned first_layer, unsigned last_layer,
344 unsigned first_sample, unsigned last_sample);
345
346 /* Reallocate the buffer and update all resource bindings where
347 * the buffer is bound, including all resource descriptors. */
348 void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
349
350 /* Enable or disable occlusion queries. */
351 void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
352
353 /* This ensures there is enough space in the command stream. */
354 void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
355 bool include_draw_vbo);
356 };
357
358 /* r600_buffer.c */
359 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
360 struct radeon_winsys_cs_handle *buf,
361 enum radeon_bo_usage usage);
362 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
363 struct r600_resource *resource,
364 unsigned usage);
365 bool r600_init_resource(struct r600_common_screen *rscreen,
366 struct r600_resource *res,
367 unsigned size, unsigned alignment,
368 bool use_reusable_pool);
369 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
370 const struct pipe_resource *templ,
371 unsigned alignment);
372
373 /* r600_common_pipe.c */
374 bool r600_common_screen_init(struct r600_common_screen *rscreen,
375 struct radeon_winsys *ws);
376 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
377 bool r600_common_context_init(struct r600_common_context *rctx,
378 struct r600_common_screen *rscreen);
379 void r600_common_context_cleanup(struct r600_common_context *rctx);
380 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
381 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
382 const struct tgsi_token *tokens);
383 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
384 unsigned offset, unsigned size, unsigned value);
385 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
386 const struct pipe_resource *templ);
387 const char *r600_get_llvm_processor_name(enum radeon_family family);
388
389 /* r600_query.c */
390 void r600_query_init(struct r600_common_context *rctx);
391 void r600_suspend_nontimer_queries(struct r600_common_context *ctx);
392 void r600_resume_nontimer_queries(struct r600_common_context *ctx);
393 void r600_query_init_backend_mask(struct r600_common_context *ctx);
394
395 /* r600_streamout.c */
396 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
397 void r600_set_streamout_targets(struct pipe_context *ctx,
398 unsigned num_targets,
399 struct pipe_stream_output_target **targets,
400 unsigned append_bitmask);
401 void r600_emit_streamout_end(struct r600_common_context *rctx);
402 void r600_streamout_init(struct r600_common_context *rctx);
403
404 /* r600_texture.c */
405 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
406 struct r600_texture *rtex,
407 unsigned nr_samples,
408 struct r600_fmask_info *out);
409 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
410 struct r600_texture *rtex,
411 struct r600_cmask_info *out);
412 void r600_texture_init_cmask(struct r600_common_screen *rscreen,
413 struct r600_texture *rtex);
414 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
415 struct pipe_resource *texture,
416 struct r600_texture **staging);
417 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
418 const struct pipe_resource *templ);
419 void r600_init_texture_functions(struct r600_common_screen *rscreen);
420
421
422 /* Inline helpers. */
423
424 static INLINE struct r600_resource *r600_resource(struct pipe_resource *r)
425 {
426 return (struct r600_resource*)r;
427 }
428
429 static INLINE void
430 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
431 {
432 pipe_resource_reference((struct pipe_resource **)ptr,
433 (struct pipe_resource *)res);
434 }
435
436 #define R600_ERR(fmt, args...) \
437 fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
438
439 #endif