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[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.h
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 /**
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
30 */
31
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
34
35 #include <stdio.h>
36
37 #include "radeon/radeon_winsys.h"
38
39 #include "util/u_blitter.h"
40 #include "util/list.h"
41 #include "util/u_range.h"
42 #include "util/u_slab.h"
43 #include "util/u_suballoc.h"
44 #include "util/u_transfer.h"
45
46 #define ATI_VENDOR_ID 0x1002
47
48 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
49 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
50 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
51 #define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
52
53 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
54 /* Pipeline & streamout query controls. */
55 #define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
56 #define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
57 #define R600_CONTEXT_PRIVATE_FLAG (1u << 3)
58
59 /* special primitive types */
60 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
61
62 /* Debug flags. */
63 /* logging */
64 #define DBG_TEX (1 << 0)
65 /* gap - reuse */
66 #define DBG_COMPUTE (1 << 2)
67 #define DBG_VM (1 << 3)
68 /* gap - reuse */
69 /* shader logging */
70 #define DBG_FS (1 << 5)
71 #define DBG_VS (1 << 6)
72 #define DBG_GS (1 << 7)
73 #define DBG_PS (1 << 8)
74 #define DBG_CS (1 << 9)
75 #define DBG_TCS (1 << 10)
76 #define DBG_TES (1 << 11)
77 #define DBG_NO_IR (1 << 12)
78 #define DBG_NO_TGSI (1 << 13)
79 #define DBG_NO_ASM (1 << 14)
80 #define DBG_PREOPT_IR (1 << 15)
81 /* gaps */
82 #define DBG_TEST_DMA (1 << 20)
83 /* Bits 21-31 are reserved for the r600g driver. */
84 /* features */
85 #define DBG_NO_ASYNC_DMA (1llu << 32)
86 #define DBG_NO_HYPERZ (1llu << 33)
87 #define DBG_NO_DISCARD_RANGE (1llu << 34)
88 #define DBG_NO_2D_TILING (1llu << 35)
89 #define DBG_NO_TILING (1llu << 36)
90 #define DBG_SWITCH_ON_EOP (1llu << 37)
91 #define DBG_FORCE_DMA (1llu << 38)
92 #define DBG_PRECOMPILE (1llu << 39)
93 #define DBG_INFO (1llu << 40)
94 #define DBG_NO_WC (1llu << 41)
95 #define DBG_CHECK_VM (1llu << 42)
96 #define DBG_NO_DCC (1llu << 43)
97 #define DBG_NO_DCC_CLEAR (1llu << 44)
98 #define DBG_NO_RB_PLUS (1llu << 45)
99 #define DBG_SI_SCHED (1llu << 46)
100 #define DBG_MONOLITHIC_SHADERS (1llu << 47)
101 #define DBG_NO_CE (1llu << 48)
102
103 #define R600_MAP_BUFFER_ALIGNMENT 64
104 #define R600_MAX_VIEWPORTS 16
105
106 enum r600_coherency {
107 R600_COHERENCY_NONE, /* no cache flushes needed */
108 R600_COHERENCY_SHADER,
109 R600_COHERENCY_CB_META,
110 };
111
112 #ifdef PIPE_ARCH_BIG_ENDIAN
113 #define R600_BIG_ENDIAN 1
114 #else
115 #define R600_BIG_ENDIAN 0
116 #endif
117
118 struct r600_common_context;
119 struct r600_perfcounters;
120 struct tgsi_shader_info;
121
122 struct radeon_shader_reloc {
123 char name[32];
124 uint64_t offset;
125 };
126
127 struct radeon_shader_binary {
128 /** Shader code */
129 unsigned char *code;
130 unsigned code_size;
131
132 /** Config/Context register state that accompanies this shader.
133 * This is a stream of dword pairs. First dword contains the
134 * register address, the second dword contains the value.*/
135 unsigned char *config;
136 unsigned config_size;
137
138 /** The number of bytes of config information for each global symbol.
139 */
140 unsigned config_size_per_symbol;
141
142 /** Constant data accessed by the shader. This will be uploaded
143 * into a constant buffer. */
144 unsigned char *rodata;
145 unsigned rodata_size;
146
147 /** List of symbol offsets for the shader */
148 uint64_t *global_symbol_offsets;
149 unsigned global_symbol_count;
150
151 struct radeon_shader_reloc *relocs;
152 unsigned reloc_count;
153
154 /** Disassembled shader in a string. */
155 char *disasm_string;
156 };
157
158 void radeon_shader_binary_init(struct radeon_shader_binary *b);
159 void radeon_shader_binary_clean(struct radeon_shader_binary *b);
160
161 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
162 * at the moment.
163 */
164 struct r600_resource {
165 struct u_resource b;
166
167 /* Winsys objects. */
168 struct pb_buffer *buf;
169 uint64_t gpu_address;
170
171 /* Resource state. */
172 enum radeon_bo_domain domains;
173
174 /* The buffer range which is initialized (with a write transfer,
175 * streamout, DMA, or as a random access target). The rest of
176 * the buffer is considered invalid and can be mapped unsynchronized.
177 *
178 * This allows unsychronized mapping of a buffer range which hasn't
179 * been used yet. It's for applications which forget to use
180 * the unsynchronized map flag and expect the driver to figure it out.
181 */
182 struct util_range valid_buffer_range;
183
184 /* For buffers only. This indicates that a write operation has been
185 * performed by TC L2, but the cache hasn't been flushed.
186 * Any hw block which doesn't use or bypasses TC L2 should check this
187 * flag and flush the cache before using the buffer.
188 *
189 * For example, TC L2 must be flushed if a buffer which has been
190 * modified by a shader store instruction is about to be used as
191 * an index buffer. The reason is that VGT DMA index fetching doesn't
192 * use TC L2.
193 */
194 bool TC_L2_dirty;
195
196 /* Whether the resource has been exported via resource_get_handle. */
197 bool is_shared;
198 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
199 };
200
201 struct r600_transfer {
202 struct pipe_transfer transfer;
203 struct r600_resource *staging;
204 unsigned offset;
205 };
206
207 struct r600_fmask_info {
208 uint64_t offset;
209 uint64_t size;
210 unsigned alignment;
211 unsigned pitch_in_pixels;
212 unsigned bank_height;
213 unsigned slice_tile_max;
214 unsigned tile_mode_index;
215 };
216
217 struct r600_cmask_info {
218 uint64_t offset;
219 uint64_t size;
220 unsigned alignment;
221 unsigned pitch;
222 unsigned height;
223 unsigned xalign;
224 unsigned yalign;
225 unsigned slice_tile_max;
226 unsigned base_address_reg;
227 };
228
229 struct r600_htile_info {
230 unsigned pitch;
231 unsigned height;
232 unsigned xalign;
233 unsigned yalign;
234 };
235
236 struct r600_texture {
237 struct r600_resource resource;
238
239 uint64_t size;
240 unsigned num_level0_transfers;
241 bool is_depth;
242 unsigned dirty_level_mask; /* each bit says if that mipmap is compressed */
243 unsigned stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
244 struct r600_texture *flushed_depth_texture;
245 boolean is_flushing_texture;
246 struct radeon_surf surface;
247
248 /* Colorbuffer compression and fast clear. */
249 struct r600_fmask_info fmask;
250 struct r600_cmask_info cmask;
251 struct r600_resource *cmask_buffer;
252 uint64_t dcc_offset; /* 0 = disabled */
253 unsigned cb_color_info; /* fast clear enable bit */
254 unsigned color_clear_value[2];
255 unsigned last_msaa_resolve_target_micro_mode;
256
257 /* Depth buffer compression and fast clear. */
258 struct r600_htile_info htile;
259 struct r600_resource *htile_buffer;
260 bool depth_cleared; /* if it was cleared at least once */
261 float depth_clear_value;
262 bool stencil_cleared; /* if it was cleared at least once */
263 uint8_t stencil_clear_value;
264
265 bool non_disp_tiling; /* R600-Cayman only */
266
267 /* Counter that should be non-zero if the texture is bound to a
268 * framebuffer. Implemented in radeonsi only.
269 */
270 uint32_t framebuffers_bound;
271 };
272
273 struct r600_surface {
274 struct pipe_surface base;
275 const struct radeon_surf_level *level_info;
276
277 bool color_initialized;
278 bool depth_initialized;
279
280 /* Misc. color flags. */
281 bool alphatest_bypass;
282 bool export_16bpc;
283 bool color_is_int8;
284
285 /* Color registers. */
286 unsigned cb_color_info;
287 unsigned cb_color_base;
288 unsigned cb_color_view;
289 unsigned cb_color_size; /* R600 only */
290 unsigned cb_color_dim; /* EG only */
291 unsigned cb_color_pitch; /* EG and later */
292 unsigned cb_color_slice; /* EG and later */
293 unsigned cb_color_attrib; /* EG and later */
294 unsigned cb_dcc_control; /* VI and later */
295 unsigned cb_color_fmask; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
296 unsigned cb_color_fmask_slice; /* EG and later */
297 unsigned cb_color_cmask; /* CB_COLORn_TILE (r600 only) */
298 unsigned cb_color_mask; /* R600 only */
299 unsigned spi_shader_col_format; /* SI+, no blending, no alpha-to-coverage. */
300 unsigned spi_shader_col_format_alpha; /* SI+, alpha-to-coverage */
301 unsigned spi_shader_col_format_blend; /* SI+, blending without alpha. */
302 unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
303 struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
304 struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
305
306 /* DB registers. */
307 unsigned db_depth_info; /* R600 only, then SI and later */
308 unsigned db_z_info; /* EG and later */
309 unsigned db_depth_base; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
310 unsigned db_depth_view;
311 unsigned db_depth_size;
312 unsigned db_depth_slice; /* EG and later */
313 unsigned db_stencil_base; /* EG and later */
314 unsigned db_stencil_info; /* EG and later */
315 unsigned db_prefetch_limit; /* R600 only */
316 unsigned db_htile_surface;
317 unsigned db_htile_data_base;
318 unsigned db_preload_control; /* EG and later */
319 unsigned pa_su_poly_offset_db_fmt_cntl;
320 };
321
322 struct r600_common_screen {
323 struct pipe_screen b;
324 struct radeon_winsys *ws;
325 enum radeon_family family;
326 enum chip_class chip_class;
327 struct radeon_info info;
328 uint64_t debug_flags;
329 bool has_cp_dma;
330 bool has_streamout;
331
332 /* Texture filter settings. */
333 int force_aniso; /* -1 = disabled */
334
335 /* Auxiliary context. Mainly used to initialize resources.
336 * It must be locked prior to using and flushed before unlocking. */
337 struct pipe_context *aux_context;
338 pipe_mutex aux_context_lock;
339
340 /* This must be in the screen, because UE4 uses one context for
341 * compilation and another one for rendering.
342 */
343 unsigned num_compilations;
344 /* Along with ST_DEBUG=precompile, this should show if applications
345 * are loading shaders on demand. This is a monotonic counter.
346 */
347 unsigned num_shaders_created;
348
349 /* GPU load thread. */
350 pipe_mutex gpu_load_mutex;
351 pipe_thread gpu_load_thread;
352 unsigned gpu_load_counter_busy;
353 unsigned gpu_load_counter_idle;
354 volatile unsigned gpu_load_stop_thread; /* bool */
355
356 char renderer_string[64];
357
358 /* Performance counters. */
359 struct r600_perfcounters *perfcounters;
360
361 /* If pipe_screen wants to re-emit the framebuffer state of all
362 * contexts, it should atomically increment this. Each context will
363 * compare this with its own last known value of the counter before
364 * drawing and re-emit the framebuffer state accordingly.
365 */
366 unsigned dirty_fb_counter;
367
368 /* Atomically increment this counter when an existing texture's
369 * metadata is enabled or disabled in a way that requires changing
370 * contexts' compressed texture binding masks.
371 */
372 unsigned compressed_colortex_counter;
373
374 /* Atomically increment this counter when an existing texture's
375 * backing buffer or tile mode parameters have changed that requires
376 * recomputation of shader descriptors.
377 */
378 unsigned dirty_tex_descriptor_counter;
379
380 void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
381 struct r600_texture *rtex,
382 struct radeon_bo_metadata *md);
383
384 void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
385 struct r600_texture *rtex,
386 struct radeon_bo_metadata *md);
387 };
388
389 /* This encapsulates a state or an operation which can emitted into the GPU
390 * command stream. */
391 struct r600_atom {
392 void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
393 unsigned num_dw;
394 unsigned short id;
395 };
396
397 struct r600_so_target {
398 struct pipe_stream_output_target b;
399
400 /* The buffer where BUFFER_FILLED_SIZE is stored. */
401 struct r600_resource *buf_filled_size;
402 unsigned buf_filled_size_offset;
403 bool buf_filled_size_valid;
404
405 unsigned stride_in_dw;
406 };
407
408 struct r600_streamout {
409 struct r600_atom begin_atom;
410 bool begin_emitted;
411 unsigned num_dw_for_end;
412
413 unsigned enabled_mask;
414 unsigned num_targets;
415 struct r600_so_target *targets[PIPE_MAX_SO_BUFFERS];
416
417 unsigned append_bitmask;
418 bool suspended;
419
420 /* External state which comes from the vertex shader,
421 * it must be set explicitly when binding a shader. */
422 unsigned *stride_in_dw;
423 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
424
425 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
426 unsigned hw_enabled_mask;
427
428 /* The state of VGT_STRMOUT_(CONFIG|EN). */
429 struct r600_atom enable_atom;
430 bool streamout_enabled;
431 bool prims_gen_query_enabled;
432 int num_prims_gen_queries;
433 };
434
435 struct r600_signed_scissor {
436 int minx;
437 int miny;
438 int maxx;
439 int maxy;
440 };
441
442 struct r600_scissors {
443 struct r600_atom atom;
444 unsigned dirty_mask;
445 struct pipe_scissor_state states[R600_MAX_VIEWPORTS];
446 };
447
448 struct r600_viewports {
449 struct r600_atom atom;
450 unsigned dirty_mask;
451 struct pipe_viewport_state states[R600_MAX_VIEWPORTS];
452 struct r600_signed_scissor as_scissor[R600_MAX_VIEWPORTS];
453 };
454
455 struct r600_ring {
456 struct radeon_winsys_cs *cs;
457 void (*flush)(void *ctx, unsigned flags,
458 struct pipe_fence_handle **fence);
459 };
460
461 struct r600_common_context {
462 struct pipe_context b; /* base class */
463
464 struct r600_common_screen *screen;
465 struct radeon_winsys *ws;
466 struct radeon_winsys_ctx *ctx;
467 enum radeon_family family;
468 enum chip_class chip_class;
469 struct r600_ring gfx;
470 struct r600_ring dma;
471 struct pipe_fence_handle *last_sdma_fence;
472 unsigned initial_gfx_cs_size;
473 unsigned gpu_reset_counter;
474 unsigned last_dirty_fb_counter;
475 unsigned last_compressed_colortex_counter;
476 unsigned last_dirty_tex_descriptor_counter;
477
478 struct u_upload_mgr *uploader;
479 struct u_suballocator *allocator_zeroed_memory;
480 struct util_slab_mempool pool_transfers;
481
482 /* Current unaccounted memory usage. */
483 uint64_t vram;
484 uint64_t gtt;
485
486 /* States. */
487 struct r600_streamout streamout;
488 struct r600_scissors scissors;
489 struct r600_viewports viewports;
490 bool scissor_enabled;
491 bool vs_writes_viewport_index;
492 bool vs_disables_clipping_viewport;
493
494 /* Additional context states. */
495 unsigned flags; /* flush flags */
496
497 /* Queries. */
498 /* Maintain the list of active queries for pausing between IBs. */
499 int num_occlusion_queries;
500 int num_perfect_occlusion_queries;
501 struct list_head active_queries;
502 unsigned num_cs_dw_queries_suspend;
503 /* Additional hardware info. */
504 unsigned backend_mask;
505 unsigned max_db; /* for OQ */
506 /* Misc stats. */
507 unsigned num_draw_calls;
508 unsigned num_dma_calls;
509 uint64_t num_alloc_tex_transfer_bytes;
510
511 /* Render condition. */
512 struct r600_atom render_cond_atom;
513 struct pipe_query *render_cond;
514 unsigned render_cond_mode;
515 boolean render_cond_invert;
516 bool render_cond_force_off; /* for u_blitter */
517
518 /* MSAA sample locations.
519 * The first index is the sample index.
520 * The second index is the coordinate: X, Y. */
521 float sample_locations_1x[1][2];
522 float sample_locations_2x[2][2];
523 float sample_locations_4x[4][2];
524 float sample_locations_8x[8][2];
525 float sample_locations_16x[16][2];
526
527 /* The list of all texture buffer objects in this context.
528 * This list is walked when a buffer is invalidated/reallocated and
529 * the GPU addresses are updated. */
530 struct list_head texture_buffers;
531
532 struct pipe_debug_callback debug;
533
534 /* Copy one resource to another using async DMA. */
535 void (*dma_copy)(struct pipe_context *ctx,
536 struct pipe_resource *dst,
537 unsigned dst_level,
538 unsigned dst_x, unsigned dst_y, unsigned dst_z,
539 struct pipe_resource *src,
540 unsigned src_level,
541 const struct pipe_box *src_box);
542
543 void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
544 uint64_t offset, uint64_t size, unsigned value,
545 enum r600_coherency coher);
546
547 void (*blit_decompress_depth)(struct pipe_context *ctx,
548 struct r600_texture *texture,
549 struct r600_texture *staging,
550 unsigned first_level, unsigned last_level,
551 unsigned first_layer, unsigned last_layer,
552 unsigned first_sample, unsigned last_sample);
553
554 void (*decompress_dcc)(struct pipe_context *ctx,
555 struct r600_texture *rtex);
556
557 /* Reallocate the buffer and update all resource bindings where
558 * the buffer is bound, including all resource descriptors. */
559 void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
560
561 /* Enable or disable occlusion queries. */
562 void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
563
564 /* This ensures there is enough space in the command stream. */
565 void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
566 bool include_draw_vbo);
567
568 void (*set_atom_dirty)(struct r600_common_context *ctx,
569 struct r600_atom *atom, bool dirty);
570 };
571
572 /* r600_buffer.c */
573 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
574 struct pb_buffer *buf,
575 enum radeon_bo_usage usage);
576 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
577 struct r600_resource *resource,
578 unsigned usage);
579 bool r600_init_resource(struct r600_common_screen *rscreen,
580 struct r600_resource *res,
581 uint64_t size, unsigned alignment);
582 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
583 const struct pipe_resource *templ,
584 unsigned alignment);
585 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
586 unsigned bind,
587 unsigned usage,
588 unsigned size,
589 unsigned alignment);
590 struct pipe_resource *
591 r600_buffer_from_user_memory(struct pipe_screen *screen,
592 const struct pipe_resource *templ,
593 void *user_memory);
594 void
595 r600_invalidate_resource(struct pipe_context *ctx,
596 struct pipe_resource *resource);
597
598 /* r600_common_pipe.c */
599 void r600_draw_rectangle(struct blitter_context *blitter,
600 int x1, int y1, int x2, int y2, float depth,
601 enum blitter_attrib_type type,
602 const union pipe_color_union *attrib);
603 bool r600_common_screen_init(struct r600_common_screen *rscreen,
604 struct radeon_winsys *ws);
605 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
606 void r600_preflush_suspend_features(struct r600_common_context *ctx);
607 void r600_postflush_resume_features(struct r600_common_context *ctx);
608 bool r600_common_context_init(struct r600_common_context *rctx,
609 struct r600_common_screen *rscreen);
610 void r600_common_context_cleanup(struct r600_common_context *rctx);
611 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
612 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
613 unsigned processor);
614 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
615 uint64_t offset, uint64_t size, unsigned value,
616 enum r600_coherency coher);
617 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
618 const struct pipe_resource *templ);
619 const char *r600_get_llvm_processor_name(enum radeon_family family);
620 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
621 struct r600_resource *dst, struct r600_resource *src);
622 void r600_dma_emit_wait_idle(struct r600_common_context *rctx);
623
624 /* r600_gpu_load.c */
625 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
626 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
627 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
628
629 /* r600_perfcounters.c */
630 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
631
632 /* r600_query.c */
633 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
634 void r600_query_init(struct r600_common_context *rctx);
635 void r600_suspend_queries(struct r600_common_context *ctx);
636 void r600_resume_queries(struct r600_common_context *ctx);
637 void r600_query_init_backend_mask(struct r600_common_context *ctx);
638
639 /* r600_streamout.c */
640 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
641 void r600_set_streamout_targets(struct pipe_context *ctx,
642 unsigned num_targets,
643 struct pipe_stream_output_target **targets,
644 const unsigned *offset);
645 void r600_emit_streamout_end(struct r600_common_context *rctx);
646 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
647 unsigned type, int diff);
648 void r600_streamout_init(struct r600_common_context *rctx);
649
650 /* r600_test_dma.c */
651 void r600_test_dma(struct r600_common_screen *rscreen);
652
653 /* r600_texture.c */
654 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
655 struct r600_texture *rdst,
656 unsigned dst_level, unsigned dstx,
657 unsigned dsty, unsigned dstz,
658 struct r600_texture *rsrc,
659 unsigned src_level,
660 const struct pipe_box *src_box);
661 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
662 struct r600_texture *rtex,
663 unsigned nr_samples,
664 struct r600_fmask_info *out);
665 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
666 struct r600_texture *rtex,
667 struct r600_cmask_info *out);
668 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
669 struct pipe_resource *texture,
670 struct r600_texture **staging);
671 void r600_print_texture_info(struct r600_texture *rtex, FILE *f);
672 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
673 const struct pipe_resource *templ);
674 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
675 struct pipe_resource *texture,
676 const struct pipe_surface *templ,
677 unsigned width, unsigned height);
678 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
679 void vi_dcc_clear_level(struct r600_common_context *rctx,
680 struct r600_texture *rtex,
681 unsigned level, unsigned clear_value);
682 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
683 struct pipe_framebuffer_state *fb,
684 struct r600_atom *fb_state,
685 unsigned *buffers, unsigned *dirty_cbufs,
686 const union pipe_color_union *color);
687 bool r600_texture_disable_dcc(struct r600_common_screen *rscreen,
688 struct r600_texture *rtex);
689 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
690 void r600_init_context_texture_functions(struct r600_common_context *rctx);
691
692 /* r600_viewport.c */
693 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
694 struct pipe_scissor_state *scissor);
695 void r600_set_scissor_enable(struct r600_common_context *rctx, bool enable);
696 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
697 struct tgsi_shader_info *info);
698 void r600_init_viewport_functions(struct r600_common_context *rctx);
699
700 /* cayman_msaa.c */
701 extern const uint32_t eg_sample_locs_2x[4];
702 extern const unsigned eg_max_dist_2x;
703 extern const uint32_t eg_sample_locs_4x[4];
704 extern const unsigned eg_max_dist_4x;
705 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
706 unsigned sample_index, float *out_value);
707 void cayman_init_msaa(struct pipe_context *ctx);
708 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
709 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
710 int ps_iter_samples, int overrast_samples);
711
712
713 /* Inline helpers. */
714
715 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
716 {
717 return (struct r600_resource*)r;
718 }
719
720 static inline void
721 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
722 {
723 pipe_resource_reference((struct pipe_resource **)ptr,
724 (struct pipe_resource *)res);
725 }
726
727 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
728 {
729 return rctx->streamout.streamout_enabled ||
730 rctx->streamout.prims_gen_query_enabled;
731 }
732
733 #define SQ_TEX_XY_FILTER_POINT 0x00
734 #define SQ_TEX_XY_FILTER_BILINEAR 0x01
735 #define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
736 #define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03
737
738 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
739 {
740 if (filter == PIPE_TEX_FILTER_LINEAR)
741 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
742 : SQ_TEX_XY_FILTER_BILINEAR;
743 else
744 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
745 : SQ_TEX_XY_FILTER_POINT;
746 }
747
748 static inline unsigned r600_tex_aniso_filter(unsigned filter)
749 {
750 if (filter < 2)
751 return 0;
752 if (filter < 4)
753 return 1;
754 if (filter < 8)
755 return 2;
756 if (filter < 16)
757 return 3;
758 return 4;
759 }
760
761 static inline unsigned r600_wavefront_size(enum radeon_family family)
762 {
763 switch (family) {
764 case CHIP_RV610:
765 case CHIP_RS780:
766 case CHIP_RV620:
767 case CHIP_RS880:
768 return 16;
769 case CHIP_RV630:
770 case CHIP_RV635:
771 case CHIP_RV730:
772 case CHIP_RV710:
773 case CHIP_PALM:
774 case CHIP_CEDAR:
775 return 32;
776 default:
777 return 64;
778 }
779 }
780
781 static inline enum radeon_bo_priority
782 r600_get_sampler_view_priority(struct r600_resource *res)
783 {
784 if (res->b.b.target == PIPE_BUFFER)
785 return RADEON_PRIO_SAMPLER_BUFFER;
786
787 if (res->b.b.nr_samples > 1)
788 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
789
790 return RADEON_PRIO_SAMPLER_TEXTURE;
791 }
792
793 #define COMPUTE_DBG(rscreen, fmt, args...) \
794 do { \
795 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
796 } while (0);
797
798 #define R600_ERR(fmt, args...) \
799 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
800
801 /* For MSAA sample positions. */
802 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
803 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
804 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
805 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
806 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
807
808 #endif