2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
37 #include "radeon/radeon_winsys.h"
39 #include "util/u_blitter.h"
40 #include "util/list.h"
41 #include "util/u_range.h"
42 #include "util/u_slab.h"
43 #include "util/u_suballoc.h"
44 #include "util/u_transfer.h"
46 #define ATI_VENDOR_ID 0x1002
48 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
49 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
50 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
51 #define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
53 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
54 /* Pipeline & streamout query controls. */
55 #define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
56 #define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
57 #define R600_CONTEXT_PRIVATE_FLAG (1u << 3)
59 /* special primitive types */
60 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
64 #define DBG_TEX (1 << 0)
66 #define DBG_COMPUTE (1 << 2)
67 #define DBG_VM (1 << 3)
70 #define DBG_FS (1 << 5)
71 #define DBG_VS (1 << 6)
72 #define DBG_GS (1 << 7)
73 #define DBG_PS (1 << 8)
74 #define DBG_CS (1 << 9)
75 #define DBG_TCS (1 << 10)
76 #define DBG_TES (1 << 11)
77 #define DBG_NO_IR (1 << 12)
78 #define DBG_NO_TGSI (1 << 13)
79 #define DBG_NO_ASM (1 << 14)
80 #define DBG_PREOPT_IR (1 << 15)
82 #define DBG_TEST_DMA (1 << 20)
83 /* Bits 21-31 are reserved for the r600g driver. */
85 #define DBG_NO_ASYNC_DMA (1llu << 32)
86 #define DBG_NO_HYPERZ (1llu << 33)
87 #define DBG_NO_DISCARD_RANGE (1llu << 34)
88 #define DBG_NO_2D_TILING (1llu << 35)
89 #define DBG_NO_TILING (1llu << 36)
90 #define DBG_SWITCH_ON_EOP (1llu << 37)
91 #define DBG_FORCE_DMA (1llu << 38)
92 #define DBG_PRECOMPILE (1llu << 39)
93 #define DBG_INFO (1llu << 40)
94 #define DBG_NO_WC (1llu << 41)
95 #define DBG_CHECK_VM (1llu << 42)
96 #define DBG_NO_DCC (1llu << 43)
97 #define DBG_NO_DCC_CLEAR (1llu << 44)
98 #define DBG_NO_RB_PLUS (1llu << 45)
99 #define DBG_SI_SCHED (1llu << 46)
100 #define DBG_MONOLITHIC_SHADERS (1llu << 47)
101 #define DBG_NO_CE (1llu << 48)
102 #define DBG_UNSAFE_MATH (1llu << 49)
104 #define R600_MAP_BUFFER_ALIGNMENT 64
105 #define R600_MAX_VIEWPORTS 16
107 enum r600_coherency
{
108 R600_COHERENCY_NONE
, /* no cache flushes needed */
109 R600_COHERENCY_SHADER
,
110 R600_COHERENCY_CB_META
,
113 #ifdef PIPE_ARCH_BIG_ENDIAN
114 #define R600_BIG_ENDIAN 1
116 #define R600_BIG_ENDIAN 0
119 struct r600_common_context
;
120 struct r600_perfcounters
;
121 struct tgsi_shader_info
;
123 struct radeon_shader_reloc
{
128 struct radeon_shader_binary
{
133 /** Config/Context register state that accompanies this shader.
134 * This is a stream of dword pairs. First dword contains the
135 * register address, the second dword contains the value.*/
136 unsigned char *config
;
137 unsigned config_size
;
139 /** The number of bytes of config information for each global symbol.
141 unsigned config_size_per_symbol
;
143 /** Constant data accessed by the shader. This will be uploaded
144 * into a constant buffer. */
145 unsigned char *rodata
;
146 unsigned rodata_size
;
148 /** List of symbol offsets for the shader */
149 uint64_t *global_symbol_offsets
;
150 unsigned global_symbol_count
;
152 struct radeon_shader_reloc
*relocs
;
153 unsigned reloc_count
;
155 /** Disassembled shader in a string. */
159 void radeon_shader_binary_init(struct radeon_shader_binary
*b
);
160 void radeon_shader_binary_clean(struct radeon_shader_binary
*b
);
162 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
165 struct r600_resource
{
168 /* Winsys objects. */
169 struct pb_buffer
*buf
;
170 uint64_t gpu_address
;
172 /* Resource state. */
173 enum radeon_bo_domain domains
;
175 /* The buffer range which is initialized (with a write transfer,
176 * streamout, DMA, or as a random access target). The rest of
177 * the buffer is considered invalid and can be mapped unsynchronized.
179 * This allows unsychronized mapping of a buffer range which hasn't
180 * been used yet. It's for applications which forget to use
181 * the unsynchronized map flag and expect the driver to figure it out.
183 struct util_range valid_buffer_range
;
185 /* For buffers only. This indicates that a write operation has been
186 * performed by TC L2, but the cache hasn't been flushed.
187 * Any hw block which doesn't use or bypasses TC L2 should check this
188 * flag and flush the cache before using the buffer.
190 * For example, TC L2 must be flushed if a buffer which has been
191 * modified by a shader store instruction is about to be used as
192 * an index buffer. The reason is that VGT DMA index fetching doesn't
197 /* Whether the resource has been exported via resource_get_handle. */
199 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
202 struct r600_transfer
{
203 struct pipe_transfer transfer
;
204 struct r600_resource
*staging
;
208 struct r600_fmask_info
{
212 unsigned pitch_in_pixels
;
213 unsigned bank_height
;
214 unsigned slice_tile_max
;
215 unsigned tile_mode_index
;
218 struct r600_cmask_info
{
226 unsigned slice_tile_max
;
227 unsigned base_address_reg
;
230 struct r600_htile_info
{
237 struct r600_texture
{
238 struct r600_resource resource
;
241 unsigned num_level0_transfers
;
243 unsigned dirty_level_mask
; /* each bit says if that mipmap is compressed */
244 unsigned stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
245 struct r600_texture
*flushed_depth_texture
;
246 bool is_flushing_texture
;
247 struct radeon_surf surface
;
249 /* Colorbuffer compression and fast clear. */
250 struct r600_fmask_info fmask
;
251 struct r600_cmask_info cmask
;
252 struct r600_resource
*cmask_buffer
;
253 uint64_t dcc_offset
; /* 0 = disabled */
254 unsigned cb_color_info
; /* fast clear enable bit */
255 unsigned color_clear_value
[2];
256 unsigned last_msaa_resolve_target_micro_mode
;
258 /* Depth buffer compression and fast clear. */
259 struct r600_htile_info htile
;
260 struct r600_resource
*htile_buffer
;
261 bool depth_cleared
; /* if it was cleared at least once */
262 float depth_clear_value
;
263 bool stencil_cleared
; /* if it was cleared at least once */
264 uint8_t stencil_clear_value
;
266 bool non_disp_tiling
; /* R600-Cayman only */
268 /* Whether the texture is a displayable back buffer and needs DCC
269 * decompression, which is expensive. Therefore, it's enabled only
270 * if statistics suggest that it will pay off and it's allocated
271 * separately. It can't be bound as a sampler by apps. Limited to
272 * target == 2D and last_level == 0. If enabled, dcc_offset contains
273 * the absolute GPUVM address, not the relative one.
275 struct r600_resource
*dcc_separate_buffer
;
276 /* When DCC is temporarily disabled, the separate buffer is here. */
277 struct r600_resource
*last_dcc_separate_buffer
;
278 /* We need to track DCC dirtiness, because st/dri usually calls
279 * flush_resource twice per frame (not a bug) and we don't wanna
280 * decompress DCC twice. Also, the dirty tracking must be done even
281 * if DCC isn't used, because it's required by the DCC usage analysis
282 * for a possible future enablement.
284 bool separate_dcc_dirty
;
285 /* Statistics gathering for the DCC enablement heuristic. */
286 bool dcc_gather_statistics
;
287 /* Estimate of how much this color buffer is written to in units of
288 * full-screen draws: ps_invocations / (width * height)
289 * Shader kills, late Z, and blending with trivial discards make it
290 * inaccurate (we need to count CB updates, not PS invocations).
292 unsigned ps_draw_ratio
;
293 /* The number of clears since the last DCC usage analysis. */
294 unsigned num_slow_clears
;
296 /* Counter that should be non-zero if the texture is bound to a
297 * framebuffer. Implemented in radeonsi only.
299 uint32_t framebuffers_bound
;
302 struct r600_surface
{
303 struct pipe_surface base
;
304 const struct radeon_surf_level
*level_info
;
306 bool color_initialized
;
307 bool depth_initialized
;
309 /* Misc. color flags. */
310 bool alphatest_bypass
;
314 /* Color registers. */
315 unsigned cb_color_info
;
316 unsigned cb_color_base
;
317 unsigned cb_color_view
;
318 unsigned cb_color_size
; /* R600 only */
319 unsigned cb_color_dim
; /* EG only */
320 unsigned cb_color_pitch
; /* EG and later */
321 unsigned cb_color_slice
; /* EG and later */
322 unsigned cb_color_attrib
; /* EG and later */
323 unsigned cb_dcc_control
; /* VI and later */
324 unsigned cb_color_fmask
; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
325 unsigned cb_color_fmask_slice
; /* EG and later */
326 unsigned cb_color_cmask
; /* CB_COLORn_TILE (r600 only) */
327 unsigned cb_color_mask
; /* R600 only */
328 unsigned spi_shader_col_format
; /* SI+, no blending, no alpha-to-coverage. */
329 unsigned spi_shader_col_format_alpha
; /* SI+, alpha-to-coverage */
330 unsigned spi_shader_col_format_blend
; /* SI+, blending without alpha. */
331 unsigned spi_shader_col_format_blend_alpha
; /* SI+, blending with alpha. */
332 struct r600_resource
*cb_buffer_fmask
; /* Used for FMASK relocations. R600 only */
333 struct r600_resource
*cb_buffer_cmask
; /* Used for CMASK relocations. R600 only */
336 unsigned db_depth_info
; /* R600 only, then SI and later */
337 unsigned db_z_info
; /* EG and later */
338 unsigned db_depth_base
; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
339 unsigned db_depth_view
;
340 unsigned db_depth_size
;
341 unsigned db_depth_slice
; /* EG and later */
342 unsigned db_stencil_base
; /* EG and later */
343 unsigned db_stencil_info
; /* EG and later */
344 unsigned db_prefetch_limit
; /* R600 only */
345 unsigned db_htile_surface
;
346 unsigned db_htile_data_base
;
347 unsigned db_preload_control
; /* EG and later */
350 struct r600_common_screen
{
351 struct pipe_screen b
;
352 struct radeon_winsys
*ws
;
353 enum radeon_family family
;
354 enum chip_class chip_class
;
355 struct radeon_info info
;
356 uint64_t debug_flags
;
360 /* Texture filter settings. */
361 int force_aniso
; /* -1 = disabled */
363 /* Auxiliary context. Mainly used to initialize resources.
364 * It must be locked prior to using and flushed before unlocking. */
365 struct pipe_context
*aux_context
;
366 pipe_mutex aux_context_lock
;
368 /* This must be in the screen, because UE4 uses one context for
369 * compilation and another one for rendering.
371 unsigned num_compilations
;
372 /* Along with ST_DEBUG=precompile, this should show if applications
373 * are loading shaders on demand. This is a monotonic counter.
375 unsigned num_shaders_created
;
377 /* GPU load thread. */
378 pipe_mutex gpu_load_mutex
;
379 pipe_thread gpu_load_thread
;
380 unsigned gpu_load_counter_busy
;
381 unsigned gpu_load_counter_idle
;
382 volatile unsigned gpu_load_stop_thread
; /* bool */
384 char renderer_string
[64];
386 /* Performance counters. */
387 struct r600_perfcounters
*perfcounters
;
389 /* If pipe_screen wants to re-emit the framebuffer state of all
390 * contexts, it should atomically increment this. Each context will
391 * compare this with its own last known value of the counter before
392 * drawing and re-emit the framebuffer state accordingly.
394 unsigned dirty_fb_counter
;
396 /* Atomically increment this counter when an existing texture's
397 * metadata is enabled or disabled in a way that requires changing
398 * contexts' compressed texture binding masks.
400 unsigned compressed_colortex_counter
;
402 /* Atomically increment this counter when an existing texture's
403 * backing buffer or tile mode parameters have changed that requires
404 * recomputation of shader descriptors.
406 unsigned dirty_tex_descriptor_counter
;
408 void (*query_opaque_metadata
)(struct r600_common_screen
*rscreen
,
409 struct r600_texture
*rtex
,
410 struct radeon_bo_metadata
*md
);
412 void (*apply_opaque_metadata
)(struct r600_common_screen
*rscreen
,
413 struct r600_texture
*rtex
,
414 struct radeon_bo_metadata
*md
);
417 /* This encapsulates a state or an operation which can emitted into the GPU
420 void (*emit
)(struct r600_common_context
*ctx
, struct r600_atom
*state
);
425 struct r600_so_target
{
426 struct pipe_stream_output_target b
;
428 /* The buffer where BUFFER_FILLED_SIZE is stored. */
429 struct r600_resource
*buf_filled_size
;
430 unsigned buf_filled_size_offset
;
431 bool buf_filled_size_valid
;
433 unsigned stride_in_dw
;
436 struct r600_streamout
{
437 struct r600_atom begin_atom
;
439 unsigned num_dw_for_end
;
441 unsigned enabled_mask
;
442 unsigned num_targets
;
443 struct r600_so_target
*targets
[PIPE_MAX_SO_BUFFERS
];
445 unsigned append_bitmask
;
448 /* External state which comes from the vertex shader,
449 * it must be set explicitly when binding a shader. */
450 unsigned *stride_in_dw
;
451 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
453 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
454 unsigned hw_enabled_mask
;
456 /* The state of VGT_STRMOUT_(CONFIG|EN). */
457 struct r600_atom enable_atom
;
458 bool streamout_enabled
;
459 bool prims_gen_query_enabled
;
460 int num_prims_gen_queries
;
463 struct r600_signed_scissor
{
470 struct r600_scissors
{
471 struct r600_atom atom
;
473 struct pipe_scissor_state states
[R600_MAX_VIEWPORTS
];
476 struct r600_viewports
{
477 struct r600_atom atom
;
479 struct pipe_viewport_state states
[R600_MAX_VIEWPORTS
];
480 struct r600_signed_scissor as_scissor
[R600_MAX_VIEWPORTS
];
484 struct radeon_winsys_cs
*cs
;
485 void (*flush
)(void *ctx
, unsigned flags
,
486 struct pipe_fence_handle
**fence
);
489 /* Saved CS data for debugging features. */
490 struct radeon_saved_cs
{
494 struct radeon_bo_list_item
*bo_list
;
498 struct r600_common_context
{
499 struct pipe_context b
; /* base class */
501 struct r600_common_screen
*screen
;
502 struct radeon_winsys
*ws
;
503 struct radeon_winsys_ctx
*ctx
;
504 enum radeon_family family
;
505 enum chip_class chip_class
;
506 struct r600_ring gfx
;
507 struct r600_ring dma
;
508 struct pipe_fence_handle
*last_sdma_fence
;
509 unsigned initial_gfx_cs_size
;
510 unsigned gpu_reset_counter
;
511 unsigned last_dirty_fb_counter
;
512 unsigned last_compressed_colortex_counter
;
513 unsigned last_dirty_tex_descriptor_counter
;
515 struct u_upload_mgr
*uploader
;
516 struct u_suballocator
*allocator_zeroed_memory
;
517 struct util_slab_mempool pool_transfers
;
519 /* Current unaccounted memory usage. */
524 struct r600_streamout streamout
;
525 struct r600_scissors scissors
;
526 struct r600_viewports viewports
;
527 bool scissor_enabled
;
528 bool vs_writes_viewport_index
;
529 bool vs_disables_clipping_viewport
;
531 /* Additional context states. */
532 unsigned flags
; /* flush flags */
535 /* Maintain the list of active queries for pausing between IBs. */
536 int num_occlusion_queries
;
537 int num_perfect_occlusion_queries
;
538 struct list_head active_queries
;
539 unsigned num_cs_dw_queries_suspend
;
540 /* Additional hardware info. */
541 unsigned backend_mask
;
542 unsigned max_db
; /* for OQ */
544 unsigned num_draw_calls
;
545 unsigned num_spill_draw_calls
;
546 unsigned num_compute_calls
;
547 unsigned num_spill_compute_calls
;
548 unsigned num_dma_calls
;
549 uint64_t num_alloc_tex_transfer_bytes
;
550 unsigned last_tex_ps_draw_ratio
; /* for query */
552 /* Render condition. */
553 struct r600_atom render_cond_atom
;
554 struct pipe_query
*render_cond
;
555 unsigned render_cond_mode
;
556 bool render_cond_invert
;
557 bool render_cond_force_off
; /* for u_blitter */
559 /* MSAA sample locations.
560 * The first index is the sample index.
561 * The second index is the coordinate: X, Y. */
562 float sample_locations_1x
[1][2];
563 float sample_locations_2x
[2][2];
564 float sample_locations_4x
[4][2];
565 float sample_locations_8x
[8][2];
566 float sample_locations_16x
[16][2];
568 /* Statistics gathering for the DCC enablement heuristic. It can't be
569 * in r600_texture because r600_texture can be shared by multiple
570 * contexts. This is for back buffers only. We shouldn't get too many
574 struct r600_texture
*tex
;
575 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
576 struct pipe_query
*ps_stats
[3];
577 /* If all slots are used and another slot is needed,
578 * the least recently used slot is evicted based on this. */
579 int64_t last_use_timestamp
;
583 /* The list of all texture buffer objects in this context.
584 * This list is walked when a buffer is invalidated/reallocated and
585 * the GPU addresses are updated. */
586 struct list_head texture_buffers
;
588 struct pipe_debug_callback debug
;
590 /* Copy one resource to another using async DMA. */
591 void (*dma_copy
)(struct pipe_context
*ctx
,
592 struct pipe_resource
*dst
,
594 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
595 struct pipe_resource
*src
,
597 const struct pipe_box
*src_box
);
599 void (*clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
600 uint64_t offset
, uint64_t size
, unsigned value
,
601 enum r600_coherency coher
);
603 void (*blit_decompress_depth
)(struct pipe_context
*ctx
,
604 struct r600_texture
*texture
,
605 struct r600_texture
*staging
,
606 unsigned first_level
, unsigned last_level
,
607 unsigned first_layer
, unsigned last_layer
,
608 unsigned first_sample
, unsigned last_sample
);
610 void (*decompress_dcc
)(struct pipe_context
*ctx
,
611 struct r600_texture
*rtex
);
613 /* Reallocate the buffer and update all resource bindings where
614 * the buffer is bound, including all resource descriptors. */
615 void (*invalidate_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
);
617 /* Enable or disable occlusion queries. */
618 void (*set_occlusion_query_state
)(struct pipe_context
*ctx
, bool enable
);
620 /* This ensures there is enough space in the command stream. */
621 void (*need_gfx_cs_space
)(struct pipe_context
*ctx
, unsigned num_dw
,
622 bool include_draw_vbo
);
624 void (*set_atom_dirty
)(struct r600_common_context
*ctx
,
625 struct r600_atom
*atom
, bool dirty
);
627 void (*check_vm_faults
)(struct r600_common_context
*ctx
,
628 struct radeon_saved_cs
*saved
,
629 enum ring_type ring
);
633 bool r600_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
634 struct pb_buffer
*buf
,
635 enum radeon_bo_usage usage
);
636 void *r600_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
637 struct r600_resource
*resource
,
639 bool r600_init_resource(struct r600_common_screen
*rscreen
,
640 struct r600_resource
*res
,
641 uint64_t size
, unsigned alignment
);
642 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
643 const struct pipe_resource
*templ
,
645 struct pipe_resource
* r600_aligned_buffer_create(struct pipe_screen
*screen
,
650 struct pipe_resource
*
651 r600_buffer_from_user_memory(struct pipe_screen
*screen
,
652 const struct pipe_resource
*templ
,
655 r600_invalidate_resource(struct pipe_context
*ctx
,
656 struct pipe_resource
*resource
);
658 /* r600_common_pipe.c */
659 void r600_draw_rectangle(struct blitter_context
*blitter
,
660 int x1
, int y1
, int x2
, int y2
, float depth
,
661 enum blitter_attrib_type type
,
662 const union pipe_color_union
*attrib
);
663 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
664 struct radeon_winsys
*ws
);
665 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
);
666 void r600_preflush_suspend_features(struct r600_common_context
*ctx
);
667 void r600_postflush_resume_features(struct r600_common_context
*ctx
);
668 bool r600_common_context_init(struct r600_common_context
*rctx
,
669 struct r600_common_screen
*rscreen
);
670 void r600_common_context_cleanup(struct r600_common_context
*rctx
);
671 void r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
);
672 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
674 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
675 uint64_t offset
, uint64_t size
, unsigned value
,
676 enum r600_coherency coher
);
677 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
678 const struct pipe_resource
*templ
);
679 const char *r600_get_llvm_processor_name(enum radeon_family family
);
680 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
,
681 struct r600_resource
*dst
, struct r600_resource
*src
);
682 void r600_dma_emit_wait_idle(struct r600_common_context
*rctx
);
683 void radeon_save_cs(struct radeon_winsys
*ws
, struct radeon_winsys_cs
*cs
,
684 struct radeon_saved_cs
*saved
);
685 void radeon_clear_saved_cs(struct radeon_saved_cs
*saved
);
687 /* r600_gpu_load.c */
688 void r600_gpu_load_kill_thread(struct r600_common_screen
*rscreen
);
689 uint64_t r600_gpu_load_begin(struct r600_common_screen
*rscreen
);
690 unsigned r600_gpu_load_end(struct r600_common_screen
*rscreen
, uint64_t begin
);
692 /* r600_perfcounters.c */
693 void r600_perfcounters_destroy(struct r600_common_screen
*rscreen
);
696 void r600_init_screen_query_functions(struct r600_common_screen
*rscreen
);
697 void r600_query_init(struct r600_common_context
*rctx
);
698 void r600_suspend_queries(struct r600_common_context
*ctx
);
699 void r600_resume_queries(struct r600_common_context
*ctx
);
700 void r600_query_init_backend_mask(struct r600_common_context
*ctx
);
702 /* r600_streamout.c */
703 void r600_streamout_buffers_dirty(struct r600_common_context
*rctx
);
704 void r600_set_streamout_targets(struct pipe_context
*ctx
,
705 unsigned num_targets
,
706 struct pipe_stream_output_target
**targets
,
707 const unsigned *offset
);
708 void r600_emit_streamout_end(struct r600_common_context
*rctx
);
709 void r600_update_prims_generated_query_state(struct r600_common_context
*rctx
,
710 unsigned type
, int diff
);
711 void r600_streamout_init(struct r600_common_context
*rctx
);
713 /* r600_test_dma.c */
714 void r600_test_dma(struct r600_common_screen
*rscreen
);
717 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
718 struct r600_texture
*rdst
,
719 unsigned dst_level
, unsigned dstx
,
720 unsigned dsty
, unsigned dstz
,
721 struct r600_texture
*rsrc
,
723 const struct pipe_box
*src_box
);
724 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
725 struct r600_texture
*rtex
,
727 struct r600_fmask_info
*out
);
728 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
729 struct r600_texture
*rtex
,
730 struct r600_cmask_info
*out
);
731 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
732 struct pipe_resource
*texture
,
733 struct r600_texture
**staging
);
734 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
);
735 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
736 const struct pipe_resource
*templ
);
737 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
738 struct pipe_resource
*texture
,
739 const struct pipe_surface
*templ
,
740 unsigned width
, unsigned height
);
741 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
742 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
743 struct r600_texture
*tex
);
744 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
745 struct r600_texture
*tex
);
746 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
747 struct r600_texture
*tex
);
748 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
749 struct r600_texture
*rtex
,
750 unsigned level
, unsigned clear_value
);
751 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
752 struct pipe_framebuffer_state
*fb
,
753 struct r600_atom
*fb_state
,
754 unsigned *buffers
, unsigned *dirty_cbufs
,
755 const union pipe_color_union
*color
);
756 bool r600_texture_disable_dcc(struct r600_common_screen
*rscreen
,
757 struct r600_texture
*rtex
);
758 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
);
759 void r600_init_context_texture_functions(struct r600_common_context
*rctx
);
761 /* r600_viewport.c */
762 void evergreen_apply_scissor_bug_workaround(struct r600_common_context
*rctx
,
763 struct pipe_scissor_state
*scissor
);
764 void r600_set_scissor_enable(struct r600_common_context
*rctx
, bool enable
);
765 void r600_update_vs_writes_viewport_index(struct r600_common_context
*rctx
,
766 struct tgsi_shader_info
*info
);
767 void r600_init_viewport_functions(struct r600_common_context
*rctx
);
770 extern const uint32_t eg_sample_locs_2x
[4];
771 extern const unsigned eg_max_dist_2x
;
772 extern const uint32_t eg_sample_locs_4x
[4];
773 extern const unsigned eg_max_dist_4x
;
774 void cayman_get_sample_position(struct pipe_context
*ctx
, unsigned sample_count
,
775 unsigned sample_index
, float *out_value
);
776 void cayman_init_msaa(struct pipe_context
*ctx
);
777 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
778 void cayman_emit_msaa_config(struct radeon_winsys_cs
*cs
, int nr_samples
,
779 int ps_iter_samples
, int overrast_samples
,
780 unsigned sc_mode_cntl_1
);
783 /* Inline helpers. */
785 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
787 return (struct r600_resource
*)r
;
791 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
793 pipe_resource_reference((struct pipe_resource
**)ptr
,
794 (struct pipe_resource
*)res
);
797 static inline bool r600_get_strmout_en(struct r600_common_context
*rctx
)
799 return rctx
->streamout
.streamout_enabled
||
800 rctx
->streamout
.prims_gen_query_enabled
;
803 #define SQ_TEX_XY_FILTER_POINT 0x00
804 #define SQ_TEX_XY_FILTER_BILINEAR 0x01
805 #define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
806 #define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03
808 static inline unsigned eg_tex_filter(unsigned filter
, unsigned max_aniso
)
810 if (filter
== PIPE_TEX_FILTER_LINEAR
)
811 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
812 : SQ_TEX_XY_FILTER_BILINEAR
;
814 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
815 : SQ_TEX_XY_FILTER_POINT
;
818 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
831 static inline unsigned r600_wavefront_size(enum radeon_family family
)
851 static inline enum radeon_bo_priority
852 r600_get_sampler_view_priority(struct r600_resource
*res
)
854 if (res
->b
.b
.target
== PIPE_BUFFER
)
855 return RADEON_PRIO_SAMPLER_BUFFER
;
857 if (res
->b
.b
.nr_samples
> 1)
858 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
860 return RADEON_PRIO_SAMPLER_TEXTURE
;
863 #define COMPUTE_DBG(rscreen, fmt, args...) \
865 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
868 #define R600_ERR(fmt, args...) \
869 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
871 /* For MSAA sample positions. */
872 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
873 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
874 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
875 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
876 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))