src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/u_slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  47 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  48 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  49
  50 #define R600_QUERY_DRAW_CALLS           (PIPE_QUERY_DRIVER_SPECIFIC + 0)
  51 #define R600_QUERY_REQUESTED_VRAM       (PIPE_QUERY_DRIVER_SPECIFIC + 1)
  52 #define R600_QUERY_REQUESTED_GTT        (PIPE_QUERY_DRIVER_SPECIFIC + 2)
  53 #define R600_QUERY_BUFFER_WAIT_TIME     (PIPE_QUERY_DRIVER_SPECIFIC + 3)
  54 #define R600_QUERY_NUM_CS_FLUSHES       (PIPE_QUERY_DRIVER_SPECIFIC + 4)
  55 #define R600_QUERY_NUM_BYTES_MOVED      (PIPE_QUERY_DRIVER_SPECIFIC + 5)
  56 #define R600_QUERY_VRAM_USAGE           (PIPE_QUERY_DRIVER_SPECIFIC + 6)
  57 #define R600_QUERY_GTT_USAGE            (PIPE_QUERY_DRIVER_SPECIFIC + 7)
  58 #define R600_QUERY_GPU_TEMPERATURE      (PIPE_QUERY_DRIVER_SPECIFIC + 8)
  59 #define R600_QUERY_CURRENT_GPU_SCLK     (PIPE_QUERY_DRIVER_SPECIFIC + 9)
  60 #define R600_QUERY_CURRENT_GPU_MCLK     (PIPE_QUERY_DRIVER_SPECIFIC + 10)
  61 #define R600_QUERY_GPU_LOAD             (PIPE_QUERY_DRIVER_SPECIFIC + 11)
  62
  63 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  64 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 1)
  65
  66 /* special primitive types */
  67 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  68
  69 /* Debug flags. */
  70 /* logging */
  71 #define DBG_TEX                 (1 << 0)
  72 #define DBG_TEXMIP              (1 << 1)
  73 #define DBG_COMPUTE             (1 << 2)
  74 #define DBG_VM                  (1 << 3)
  75 #define DBG_TRACE_CS            (1 << 4)
  76 /* shader logging */
  77 #define DBG_FS                  (1 << 5)
  78 #define DBG_VS                  (1 << 6)
  79 #define DBG_GS                  (1 << 7)
  80 #define DBG_PS                  (1 << 8)
  81 #define DBG_CS                  (1 << 9)
  82 /* features */
  83 #define DBG_NO_ASYNC_DMA        (1 << 10)
  84 #define DBG_NO_HYPERZ           (1 << 11)
  85 #define DBG_NO_DISCARD_RANGE    (1 << 12)
  86 #define DBG_NO_2D_TILING        (1 << 13)
  87 #define DBG_NO_TILING           (1 << 14)
  88 #define DBG_SWITCH_ON_EOP       (1 << 15)
  89 #define DBG_FORCE_DMA           (1 << 16)
  90 #define DBG_PRECOMPILE          (1 << 17)
  91 #define DBG_INFO                (1 << 18)
  92 /* The maximum allowed bit is 20. */
  93
  94 #define R600_MAP_BUFFER_ALIGNMENT 64
  95
  96 struct r600_common_context;
  97
  98 struct radeon_shader_reloc {
  99         char *name;
 100         uint64_t offset;
 101 };
 102
 103 struct radeon_shader_binary {
 104         /** Shader code */
 105         unsigned char *code;
 106         unsigned code_size;
 107
 108         /** Config/Context register state that accompanies this shader.
 109          * This is a stream of dword pairs.  First dword contains the
 110          * register address, the second dword contains the value.*/
 111         unsigned char *config;
 112         unsigned config_size;
 113
 114         /** The number of bytes of config information for each global symbol.
 115          */
 116         unsigned config_size_per_symbol;
 117
 118         /** Constant data accessed by the shader.  This will be uploaded
 119          * into a constant buffer. */
 120         unsigned char *rodata;
 121         unsigned rodata_size;
 122
 123         /** List of symbol offsets for the shader */
 124         uint64_t *global_symbol_offsets;
 125         unsigned global_symbol_count;
 126
 127         struct radeon_shader_reloc *relocs;
 128         unsigned reloc_count;
 129
 130         /** Set to 1 if the disassembly for this binary has been dumped to
 131          *  stderr. */
 132         int disassembled;
 133 };
 134
 135 struct r600_resource {
 136         struct u_resource               b;
 137
 138         /* Winsys objects. */
 139         struct pb_buffer                *buf;
 140         struct radeon_winsys_cs_handle  *cs_buf;
 141         uint64_t                        gpu_address;
 142
 143         /* Resource state. */
 144         enum radeon_bo_domain           domains;
 145
 146         /* The buffer range which is initialized (with a write transfer,
 147          * streamout, DMA, or as a random access target). The rest of
 148          * the buffer is considered invalid and can be mapped unsynchronized.
 149          *
 150          * This allows unsychronized mapping of a buffer range which hasn't
 151          * been used yet. It's for applications which forget to use
 152          * the unsynchronized map flag and expect the driver to figure it out.
 153          */
 154         struct util_range               valid_buffer_range;
 155
 156         /* For buffers only. This indicates that a write operation has been
 157          * performed by TC L2, but the cache hasn't been flushed.
 158          * Any hw block which doesn't use or bypasses TC L2 should check this
 159          * flag and flush the cache before using the buffer.
 160          *
 161          * For example, TC L2 must be flushed if a buffer which has been
 162          * modified by a shader store instruction is about to be used as
 163          * an index buffer. The reason is that VGT DMA index fetching doesn't
 164          * use TC L2.
 165          */
 166         bool                            TC_L2_dirty;
 167 };
 168
 169 struct r600_transfer {
 170         struct pipe_transfer            transfer;
 171         struct r600_resource            *staging;
 172         unsigned                        offset;
 173 };
 174
 175 struct r600_fmask_info {
 176         unsigned offset;
 177         unsigned size;
 178         unsigned alignment;
 179         unsigned pitch;
 180         unsigned bank_height;
 181         unsigned slice_tile_max;
 182         unsigned tile_mode_index;
 183 };
 184
 185 struct r600_cmask_info {
 186         unsigned offset;
 187         unsigned size;
 188         unsigned alignment;
 189         unsigned slice_tile_max;
 190         unsigned base_address_reg;
 191 };
 192
 193 struct r600_texture {
 194         struct r600_resource            resource;
 195
 196         unsigned                        size;
 197         unsigned                        pitch_override;
 198         bool                            is_depth;
 199         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 200         struct r600_texture             *flushed_depth_texture;
 201         boolean                         is_flushing_texture;
 202         struct radeon_surf              surface;
 203
 204         /* Colorbuffer compression and fast clear. */
 205         struct r600_fmask_info          fmask;
 206         struct r600_cmask_info          cmask;
 207         struct r600_resource            *cmask_buffer;
 208         unsigned                        cb_color_info; /* fast clear enable bit */
 209         unsigned                        color_clear_value[2];
 210
 211         /* Depth buffer compression and fast clear. */
 212         struct r600_resource            *htile_buffer;
 213         bool                            depth_cleared; /* if it was cleared at least once */
 214         float                           depth_clear_value;
 215
 216         bool                            non_disp_tiling; /* R600-Cayman only */
 217 };
 218
 219 struct r600_surface {
 220         struct pipe_surface             base;
 221
 222         bool color_initialized;
 223         bool depth_initialized;
 224
 225         /* Misc. color flags. */
 226         bool alphatest_bypass;
 227         bool export_16bpc;
 228
 229         /* Color registers. */
 230         unsigned cb_color_info;
 231         unsigned cb_color_base;
 232         unsigned cb_color_view;
 233         unsigned cb_color_size;         /* R600 only */
 234         unsigned cb_color_dim;          /* EG only */
 235         unsigned cb_color_pitch;        /* EG and later */
 236         unsigned cb_color_slice;        /* EG and later */
 237         unsigned cb_color_attrib;       /* EG and later */
 238         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 239         unsigned cb_color_fmask_slice;  /* EG and later */
 240         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 241         unsigned cb_color_mask;         /* R600 only */
 242         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 243         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 244
 245         /* DB registers. */
 246         unsigned db_depth_info;         /* R600 only, then SI and later */
 247         unsigned db_z_info;             /* EG and later */
 248         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 249         unsigned db_depth_view;
 250         unsigned db_depth_size;
 251         unsigned db_depth_slice;        /* EG and later */
 252         unsigned db_stencil_base;       /* EG and later */
 253         unsigned db_stencil_info;       /* EG and later */
 254         unsigned db_prefetch_limit;     /* R600 only */
 255         unsigned db_htile_surface;
 256         unsigned db_htile_data_base;
 257         unsigned db_preload_control;    /* EG and later */
 258         unsigned pa_su_poly_offset_db_fmt_cntl;
 259 };
 260
 261 struct r600_tiling_info {
 262         unsigned num_channels;
 263         unsigned num_banks;
 264         unsigned group_bytes;
 265 };
 266
 267 struct r600_common_screen {
 268         struct pipe_screen              b;
 269         struct radeon_winsys            *ws;
 270         enum radeon_family              family;
 271         enum chip_class                 chip_class;
 272         struct radeon_info              info;
 273         struct r600_tiling_info         tiling_info;
 274         unsigned                        debug_flags;
 275         bool                            has_cp_dma;
 276         bool                            has_streamout;
 277
 278         /* Auxiliary context. Mainly used to initialize resources.
 279          * It must be locked prior to using and flushed before unlocking. */
 280         struct pipe_context             *aux_context;
 281         pipe_mutex                      aux_context_lock;
 282
 283         struct r600_resource            *trace_bo;
 284         uint32_t                        *trace_ptr;
 285         unsigned                        cs_count;
 286
 287         /* GPU load thread. */
 288         pipe_mutex                      gpu_load_mutex;
 289         pipe_thread                     gpu_load_thread;
 290         unsigned                        gpu_load_counter_busy;
 291         unsigned                        gpu_load_counter_idle;
 292         volatile unsigned               gpu_load_stop_thread; /* bool */
 293 };
 294
 295 /* This encapsulates a state or an operation which can emitted into the GPU
 296  * command stream. */
 297 struct r600_atom {
 298         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 299         unsigned                num_dw;
 300         bool                    dirty;
 301 };
 302
 303 struct r600_so_target {
 304         struct pipe_stream_output_target b;
 305
 306         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 307         struct r600_resource    *buf_filled_size;
 308         unsigned                buf_filled_size_offset;
 309         bool                    buf_filled_size_valid;
 310
 311         unsigned                stride_in_dw;
 312 };
 313
 314 struct r600_streamout {
 315         struct r600_atom                begin_atom;
 316         bool                            begin_emitted;
 317         unsigned                        num_dw_for_end;
 318
 319         unsigned                        enabled_mask;
 320         unsigned                        num_targets;
 321         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 322
 323         unsigned                        append_bitmask;
 324         bool                            suspended;
 325
 326         /* External state which comes from the vertex shader,
 327          * it must be set explicitly when binding a shader. */
 328         unsigned                        *stride_in_dw;
 329
 330         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 331         struct r600_atom                enable_atom;
 332         bool                            streamout_enabled;
 333         bool                            prims_gen_query_enabled;
 334         int                             num_prims_gen_queries;
 335 };
 336
 337 struct r600_ring {
 338         struct radeon_winsys_cs         *cs;
 339         bool                            flushing;
 340         void (*flush)(void *ctx, unsigned flags,
 341                       struct pipe_fence_handle **fence);
 342 };
 343
 344 struct r600_rings {
 345         struct r600_ring                gfx;
 346         struct r600_ring                dma;
 347 };
 348
 349 struct r600_common_context {
 350         struct pipe_context b; /* base class */
 351
 352         struct r600_common_screen       *screen;
 353         struct radeon_winsys            *ws;
 354         enum radeon_family              family;
 355         enum chip_class                 chip_class;
 356         struct r600_rings               rings;
 357         unsigned                        initial_gfx_cs_size;
 358         unsigned                        gpu_reset_counter;
 359
 360         struct u_upload_mgr             *uploader;
 361         struct u_suballocator           *allocator_so_filled_size;
 362         struct util_slab_mempool        pool_transfers;
 363
 364         /* Current unaccounted memory usage. */
 365         uint64_t                        vram;
 366         uint64_t                        gtt;
 367
 368         /* States. */
 369         struct r600_streamout           streamout;
 370
 371         /* Additional context states. */
 372         unsigned flags; /* flush flags */
 373
 374         /* Queries. */
 375         /* The list of active queries. Only one query of each type can be active. */
 376         int                             num_occlusion_queries;
 377         /* Keep track of non-timer queries, because they should be suspended
 378          * during context flushing.
 379          * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
 380         struct list_head                active_nontimer_queries;
 381         unsigned                        num_cs_dw_nontimer_queries_suspend;
 382         /* If queries have been suspended. */
 383         bool                            nontimer_queries_suspended;
 384         /* Additional hardware info. */
 385         unsigned                        backend_mask;
 386         unsigned                        max_db; /* for OQ */
 387         /* Misc stats. */
 388         unsigned                        num_draw_calls;
 389
 390         /* Render condition. */
 391         struct pipe_query               *current_render_cond;
 392         unsigned                        current_render_cond_mode;
 393         boolean                         current_render_cond_cond;
 394         boolean                         predicate_drawing;
 395         /* For context flushing. */
 396         struct pipe_query               *saved_render_cond;
 397         boolean                         saved_render_cond_cond;
 398         unsigned                        saved_render_cond_mode;
 399
 400         /* MSAA sample locations.
 401          * The first index is the sample index.
 402          * The second index is the coordinate: X, Y. */
 403         float                           sample_locations_1x[1][2];
 404         float                           sample_locations_2x[2][2];
 405         float                           sample_locations_4x[4][2];
 406         float                           sample_locations_8x[8][2];
 407         float                           sample_locations_16x[16][2];
 408
 409         /* The list of all texture buffer objects in this context.
 410          * This list is walked when a buffer is invalidated/reallocated and
 411          * the GPU addresses are updated. */
 412         struct list_head                texture_buffers;
 413
 414         /* Copy one resource to another using async DMA. */
 415         void (*dma_copy)(struct pipe_context *ctx,
 416                          struct pipe_resource *dst,
 417                          unsigned dst_level,
 418                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 419                          struct pipe_resource *src,
 420                          unsigned src_level,
 421                          const struct pipe_box *src_box);
 422
 423         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 424                              unsigned offset, unsigned size, unsigned value,
 425                              bool is_framebuffer);
 426
 427         void (*blit_decompress_depth)(struct pipe_context *ctx,
 428                                       struct r600_texture *texture,
 429                                       struct r600_texture *staging,
 430                                       unsigned first_level, unsigned last_level,
 431                                       unsigned first_layer, unsigned last_layer,
 432                                       unsigned first_sample, unsigned last_sample);
 433
 434         /* Reallocate the buffer and update all resource bindings where
 435          * the buffer is bound, including all resource descriptors. */
 436         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 437
 438         /* Enable or disable occlusion queries. */
 439         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 440
 441         /* This ensures there is enough space in the command stream. */
 442         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 443                                   bool include_draw_vbo);
 444 };
 445
 446 /* r600_buffer.c */
 447 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 448                                         struct radeon_winsys_cs_handle *buf,
 449                                         enum radeon_bo_usage usage);
 450 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 451                                       struct r600_resource *resource,
 452                                       unsigned usage);
 453 bool r600_init_resource(struct r600_common_screen *rscreen,
 454                         struct r600_resource *res,
 455                         unsigned size, unsigned alignment,
 456                         bool use_reusable_pool);
 457 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 458                                          const struct pipe_resource *templ,
 459                                          unsigned alignment);
 460 struct pipe_resource *
 461 r600_buffer_from_user_memory(struct pipe_screen *screen,
 462                              const struct pipe_resource *templ,
 463                              void *user_memory);
 464
 465 /* r600_common_pipe.c */
 466 void r600_draw_rectangle(struct blitter_context *blitter,
 467                          int x1, int y1, int x2, int y2, float depth,
 468                          enum blitter_attrib_type type,
 469                          const union pipe_color_union *attrib);
 470 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 471                              struct radeon_winsys *ws);
 472 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 473 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 474 void r600_postflush_resume_features(struct r600_common_context *ctx);
 475 bool r600_common_context_init(struct r600_common_context *rctx,
 476                               struct r600_common_screen *rscreen);
 477 void r600_common_context_cleanup(struct r600_common_context *rctx);
 478 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 479 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 480                           const struct tgsi_token *tokens);
 481 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 482                               unsigned offset, unsigned size, unsigned value,
 483                               bool is_framebuffer);
 484 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 485                                                   const struct pipe_resource *templ);
 486 const char *r600_get_llvm_processor_name(enum radeon_family family);
 487 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw);
 488
 489 /* r600_gpu_load.c */
 490 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 491 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
 492 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 493
 494 /* r600_query.c */
 495 void r600_query_init(struct r600_common_context *rctx);
 496 void r600_suspend_nontimer_queries(struct r600_common_context *ctx);
 497 void r600_resume_nontimer_queries(struct r600_common_context *ctx);
 498 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 499
 500 /* r600_streamout.c */
 501 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 502 void r600_set_streamout_targets(struct pipe_context *ctx,
 503                                 unsigned num_targets,
 504                                 struct pipe_stream_output_target **targets,
 505                                 const unsigned *offset);
 506 void r600_emit_streamout_end(struct r600_common_context *rctx);
 507 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 508                                              unsigned type, int diff);
 509 void r600_streamout_init(struct r600_common_context *rctx);
 510
 511 /* r600_texture.c */
 512 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 513                                  struct r600_texture *rtex,
 514                                  unsigned nr_samples,
 515                                  struct r600_fmask_info *out);
 516 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 517                                  struct r600_texture *rtex,
 518                                  struct r600_cmask_info *out);
 519 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 520                                      struct pipe_resource *texture,
 521                                      struct r600_texture **staging);
 522 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 523                                         const struct pipe_resource *templ);
 524 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 525                                                 struct pipe_resource *texture,
 526                                                 const struct pipe_surface *templ,
 527                                                 unsigned width, unsigned height);
 528 unsigned r600_translate_colorswap(enum pipe_format format);
 529 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 530                                    struct pipe_framebuffer_state *fb,
 531                                    struct r600_atom *fb_state,
 532                                    unsigned *buffers,
 533                                    const union pipe_color_union *color);
 534 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 535 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 536
 537 /* cayman_msaa.c */
 538 extern const uint32_t eg_sample_locs_2x[4];
 539 extern const unsigned eg_max_dist_2x;
 540 extern const uint32_t eg_sample_locs_4x[4];
 541 extern const unsigned eg_max_dist_4x;
 542 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 543                                 unsigned sample_index, float *out_value);
 544 void cayman_init_msaa(struct pipe_context *ctx);
 545 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 546 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 547                              int ps_iter_samples, int overrast_samples);
 548
 549
 550 /* Inline helpers. */
 551
 552 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 553 {
 554         return (struct r600_resource*)r;
 555 }
 556
 557 static inline void
 558 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 559 {
 560         pipe_resource_reference((struct pipe_resource **)ptr,
 561                                 (struct pipe_resource *)res);
 562 }
 563
 564 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 565 {
 566         if (filter <= 1)   return 0;
 567         if (filter <= 2)   return 1;
 568         if (filter <= 4)   return 2;
 569         if (filter <= 8)   return 3;
 570          /* else */        return 4;
 571 }
 572
 573 static inline unsigned r600_wavefront_size(enum radeon_family family)
 574 {
 575         switch (family) {
 576         case CHIP_RV610:
 577         case CHIP_RS780:
 578         case CHIP_RV620:
 579         case CHIP_RS880:
 580                 return 16;
 581         case CHIP_RV630:
 582         case CHIP_RV635:
 583         case CHIP_RV730:
 584         case CHIP_RV710:
 585         case CHIP_PALM:
 586         case CHIP_CEDAR:
 587                 return 32;
 588         default:
 589                 return 64;
 590         }
 591 }
 592
 593 #define COMPUTE_DBG(rscreen, fmt, args...) \
 594         do { \
 595                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 596         } while (0);
 597
 598 #define R600_ERR(fmt, args...) \
 599         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
 600
 601 /* For MSAA sample positions. */
 602 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 603         (((s0x) & 0xf) | (((s0y) & 0xf) << 4) |            \
 604         (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |     \
 605         (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |    \
 606          (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
 607
 608 #endif