src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/u_slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  47 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  48 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  49
  50 #define R600_QUERY_DRAW_CALLS           (PIPE_QUERY_DRIVER_SPECIFIC + 0)
  51 #define R600_QUERY_REQUESTED_VRAM       (PIPE_QUERY_DRIVER_SPECIFIC + 1)
  52 #define R600_QUERY_REQUESTED_GTT        (PIPE_QUERY_DRIVER_SPECIFIC + 2)
  53 #define R600_QUERY_BUFFER_WAIT_TIME     (PIPE_QUERY_DRIVER_SPECIFIC + 3)
  54 #define R600_QUERY_NUM_CS_FLUSHES       (PIPE_QUERY_DRIVER_SPECIFIC + 4)
  55 #define R600_QUERY_NUM_BYTES_MOVED      (PIPE_QUERY_DRIVER_SPECIFIC + 5)
  56 #define R600_QUERY_VRAM_USAGE           (PIPE_QUERY_DRIVER_SPECIFIC + 6)
  57 #define R600_QUERY_GTT_USAGE            (PIPE_QUERY_DRIVER_SPECIFIC + 7)
  58 #define R600_QUERY_GPU_TEMPERATURE      (PIPE_QUERY_DRIVER_SPECIFIC + 8)
  59 #define R600_QUERY_CURRENT_GPU_SCLK     (PIPE_QUERY_DRIVER_SPECIFIC + 9)
  60 #define R600_QUERY_CURRENT_GPU_MCLK     (PIPE_QUERY_DRIVER_SPECIFIC + 10)
  61 #define R600_QUERY_GPU_LOAD             (PIPE_QUERY_DRIVER_SPECIFIC + 11)
  62 #define R600_QUERY_NUM_COMPILATIONS     (PIPE_QUERY_DRIVER_SPECIFIC + 12)
  63 #define R600_QUERY_NUM_SHADERS_CREATED  (PIPE_QUERY_DRIVER_SPECIFIC + 13)
  64
  65 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  66 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 1)
  67
  68 /* special primitive types */
  69 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  70
  71 /* Debug flags. */
  72 /* logging */
  73 #define DBG_TEX                 (1 << 0)
  74 #define DBG_TEXMIP              (1 << 1)
  75 #define DBG_COMPUTE             (1 << 2)
  76 #define DBG_VM                  (1 << 3)
  77 #define DBG_TRACE_CS            (1 << 4)
  78 /* shader logging */
  79 #define DBG_FS                  (1 << 5)
  80 #define DBG_VS                  (1 << 6)
  81 #define DBG_GS                  (1 << 7)
  82 #define DBG_PS                  (1 << 8)
  83 #define DBG_CS                  (1 << 9)
  84 #define DBG_TCS                 (1 << 10)
  85 #define DBG_TES                 (1 << 11)
  86 #define DBG_NO_IR               (1 << 12)
  87 #define DBG_NO_TGSI             (1 << 13)
  88 #define DBG_NO_ASM              (1 << 14)
  89 /* Bits 21-31 are reserved for the r600g driver. */
  90 /* features */
  91 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  92 #define DBG_NO_HYPERZ           (1llu << 33)
  93 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  94 #define DBG_NO_2D_TILING        (1llu << 35)
  95 #define DBG_NO_TILING           (1llu << 36)
  96 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  97 #define DBG_FORCE_DMA           (1llu << 38)
  98 #define DBG_PRECOMPILE          (1llu << 39)
  99 #define DBG_INFO                (1llu << 40)
 100 #define DBG_NO_WC               (1llu << 41)
 101
 102 #define R600_MAP_BUFFER_ALIGNMENT 64
 103
 104 struct r600_common_context;
 105
 106 struct radeon_shader_reloc {
 107         char *name;
 108         uint64_t offset;
 109 };
 110
 111 struct radeon_shader_binary {
 112         /** Shader code */
 113         unsigned char *code;
 114         unsigned code_size;
 115
 116         /** Config/Context register state that accompanies this shader.
 117          * This is a stream of dword pairs.  First dword contains the
 118          * register address, the second dword contains the value.*/
 119         unsigned char *config;
 120         unsigned config_size;
 121
 122         /** The number of bytes of config information for each global symbol.
 123          */
 124         unsigned config_size_per_symbol;
 125
 126         /** Constant data accessed by the shader.  This will be uploaded
 127          * into a constant buffer. */
 128         unsigned char *rodata;
 129         unsigned rodata_size;
 130
 131         /** List of symbol offsets for the shader */
 132         uint64_t *global_symbol_offsets;
 133         unsigned global_symbol_count;
 134
 135         struct radeon_shader_reloc *relocs;
 136         unsigned reloc_count;
 137
 138         /** Disassembled shader in a string. */
 139         char *disasm_string;
 140 };
 141
 142 struct r600_resource {
 143         struct u_resource               b;
 144
 145         /* Winsys objects. */
 146         struct pb_buffer                *buf;
 147         struct radeon_winsys_cs_handle  *cs_buf;
 148         uint64_t                        gpu_address;
 149
 150         /* Resource state. */
 151         enum radeon_bo_domain           domains;
 152
 153         /* The buffer range which is initialized (with a write transfer,
 154          * streamout, DMA, or as a random access target). The rest of
 155          * the buffer is considered invalid and can be mapped unsynchronized.
 156          *
 157          * This allows unsychronized mapping of a buffer range which hasn't
 158          * been used yet. It's for applications which forget to use
 159          * the unsynchronized map flag and expect the driver to figure it out.
 160          */
 161         struct util_range               valid_buffer_range;
 162
 163         /* For buffers only. This indicates that a write operation has been
 164          * performed by TC L2, but the cache hasn't been flushed.
 165          * Any hw block which doesn't use or bypasses TC L2 should check this
 166          * flag and flush the cache before using the buffer.
 167          *
 168          * For example, TC L2 must be flushed if a buffer which has been
 169          * modified by a shader store instruction is about to be used as
 170          * an index buffer. The reason is that VGT DMA index fetching doesn't
 171          * use TC L2.
 172          */
 173         bool                            TC_L2_dirty;
 174 };
 175
 176 struct r600_transfer {
 177         struct pipe_transfer            transfer;
 178         struct r600_resource            *staging;
 179         unsigned                        offset;
 180 };
 181
 182 struct r600_fmask_info {
 183         unsigned offset;
 184         unsigned size;
 185         unsigned alignment;
 186         unsigned pitch;
 187         unsigned bank_height;
 188         unsigned slice_tile_max;
 189         unsigned tile_mode_index;
 190 };
 191
 192 struct r600_cmask_info {
 193         unsigned offset;
 194         unsigned size;
 195         unsigned alignment;
 196         unsigned slice_tile_max;
 197         unsigned base_address_reg;
 198 };
 199
 200 struct r600_texture {
 201         struct r600_resource            resource;
 202
 203         unsigned                        size;
 204         unsigned                        pitch_override;
 205         bool                            is_depth;
 206         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 207         struct r600_texture             *flushed_depth_texture;
 208         boolean                         is_flushing_texture;
 209         struct radeon_surf              surface;
 210
 211         /* Colorbuffer compression and fast clear. */
 212         struct r600_fmask_info          fmask;
 213         struct r600_cmask_info          cmask;
 214         struct r600_resource            *cmask_buffer;
 215         unsigned                        cb_color_info; /* fast clear enable bit */
 216         unsigned                        color_clear_value[2];
 217
 218         /* Depth buffer compression and fast clear. */
 219         struct r600_resource            *htile_buffer;
 220         bool                            depth_cleared; /* if it was cleared at least once */
 221         float                           depth_clear_value;
 222
 223         bool                            non_disp_tiling; /* R600-Cayman only */
 224 };
 225
 226 struct r600_surface {
 227         struct pipe_surface             base;
 228
 229         bool color_initialized;
 230         bool depth_initialized;
 231
 232         /* Misc. color flags. */
 233         bool alphatest_bypass;
 234         bool export_16bpc;
 235
 236         /* Color registers. */
 237         unsigned cb_color_info;
 238         unsigned cb_color_base;
 239         unsigned cb_color_view;
 240         unsigned cb_color_size;         /* R600 only */
 241         unsigned cb_color_dim;          /* EG only */
 242         unsigned cb_color_pitch;        /* EG and later */
 243         unsigned cb_color_slice;        /* EG and later */
 244         unsigned cb_color_attrib;       /* EG and later */
 245         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 246         unsigned cb_color_fmask_slice;  /* EG and later */
 247         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 248         unsigned cb_color_mask;         /* R600 only */
 249         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 250         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 251
 252         /* DB registers. */
 253         unsigned db_depth_info;         /* R600 only, then SI and later */
 254         unsigned db_z_info;             /* EG and later */
 255         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 256         unsigned db_depth_view;
 257         unsigned db_depth_size;
 258         unsigned db_depth_slice;        /* EG and later */
 259         unsigned db_stencil_base;       /* EG and later */
 260         unsigned db_stencil_info;       /* EG and later */
 261         unsigned db_prefetch_limit;     /* R600 only */
 262         unsigned db_htile_surface;
 263         unsigned db_htile_data_base;
 264         unsigned db_preload_control;    /* EG and later */
 265         unsigned pa_su_poly_offset_db_fmt_cntl;
 266 };
 267
 268 struct r600_tiling_info {
 269         unsigned num_channels;
 270         unsigned num_banks;
 271         unsigned group_bytes;
 272 };
 273
 274 struct r600_common_screen {
 275         struct pipe_screen              b;
 276         struct radeon_winsys            *ws;
 277         enum radeon_family              family;
 278         enum chip_class                 chip_class;
 279         struct radeon_info              info;
 280         struct r600_tiling_info         tiling_info;
 281         uint64_t                        debug_flags;
 282         bool                            has_cp_dma;
 283         bool                            has_streamout;
 284
 285         /* Auxiliary context. Mainly used to initialize resources.
 286          * It must be locked prior to using and flushed before unlocking. */
 287         struct pipe_context             *aux_context;
 288         pipe_mutex                      aux_context_lock;
 289
 290         struct r600_resource            *trace_bo;
 291         uint32_t                        *trace_ptr;
 292         unsigned                        cs_count;
 293
 294         /* This must be in the screen, because UE4 uses one context for
 295          * compilation and another one for rendering.
 296          */
 297         unsigned                        num_compilations;
 298         /* Along with ST_DEBUG=precompile, this should show if applications
 299          * are loading shaders on demand. This is a monotonic counter.
 300          */
 301         unsigned                        num_shaders_created;
 302
 303         /* GPU load thread. */
 304         pipe_mutex                      gpu_load_mutex;
 305         pipe_thread                     gpu_load_thread;
 306         unsigned                        gpu_load_counter_busy;
 307         unsigned                        gpu_load_counter_idle;
 308         volatile unsigned               gpu_load_stop_thread; /* bool */
 309
 310         char                            renderer_string[64];
 311 };
 312
 313 /* This encapsulates a state or an operation which can emitted into the GPU
 314  * command stream. */
 315 struct r600_atom {
 316         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 317         unsigned                num_dw;
 318         unsigned short          id;     /* used by r600 only */
 319         bool                    dirty;
 320 };
 321
 322 struct r600_so_target {
 323         struct pipe_stream_output_target b;
 324
 325         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 326         struct r600_resource    *buf_filled_size;
 327         unsigned                buf_filled_size_offset;
 328         bool                    buf_filled_size_valid;
 329
 330         unsigned                stride_in_dw;
 331 };
 332
 333 struct r600_streamout {
 334         struct r600_atom                begin_atom;
 335         bool                            begin_emitted;
 336         unsigned                        num_dw_for_end;
 337
 338         unsigned                        enabled_mask;
 339         unsigned                        num_targets;
 340         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 341
 342         unsigned                        append_bitmask;
 343         bool                            suspended;
 344
 345         /* External state which comes from the vertex shader,
 346          * it must be set explicitly when binding a shader. */
 347         unsigned                        *stride_in_dw;
 348         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 349
 350         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 351         unsigned                        hw_enabled_mask;
 352
 353         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 354         struct r600_atom                enable_atom;
 355         bool                            streamout_enabled;
 356         bool                            prims_gen_query_enabled;
 357         int                             num_prims_gen_queries;
 358 };
 359
 360 struct r600_ring {
 361         struct radeon_winsys_cs         *cs;
 362         bool                            flushing;
 363         void (*flush)(void *ctx, unsigned flags,
 364                       struct pipe_fence_handle **fence);
 365 };
 366
 367 struct r600_rings {
 368         struct r600_ring                gfx;
 369         struct r600_ring                dma;
 370 };
 371
 372 struct r600_common_context {
 373         struct pipe_context b; /* base class */
 374
 375         struct r600_common_screen       *screen;
 376         struct radeon_winsys            *ws;
 377         struct radeon_winsys_ctx        *ctx;
 378         enum radeon_family              family;
 379         enum chip_class                 chip_class;
 380         struct r600_rings               rings;
 381         unsigned                        initial_gfx_cs_size;
 382         unsigned                        gpu_reset_counter;
 383
 384         struct u_upload_mgr             *uploader;
 385         struct u_suballocator           *allocator_so_filled_size;
 386         struct util_slab_mempool        pool_transfers;
 387
 388         /* Current unaccounted memory usage. */
 389         uint64_t                        vram;
 390         uint64_t                        gtt;
 391
 392         /* States. */
 393         struct r600_streamout           streamout;
 394
 395         /* Additional context states. */
 396         unsigned flags; /* flush flags */
 397
 398         /* Queries. */
 399         /* The list of active queries. Only one query of each type can be active. */
 400         int                             num_occlusion_queries;
 401         /* Keep track of non-timer queries, because they should be suspended
 402          * during context flushing.
 403          * The timer queries (TIME_ELAPSED) shouldn't be suspended for blits,
 404          * but they should be suspended between IBs. */
 405         struct list_head                active_nontimer_queries;
 406         struct list_head                active_timer_queries;
 407         unsigned                        num_cs_dw_nontimer_queries_suspend;
 408         unsigned                        num_cs_dw_timer_queries_suspend;
 409         /* If queries have been suspended. */
 410         bool                            queries_suspended_for_flush;
 411         /* Additional hardware info. */
 412         unsigned                        backend_mask;
 413         unsigned                        max_db; /* for OQ */
 414         /* Misc stats. */
 415         unsigned                        num_draw_calls;
 416
 417         /* Render condition. */
 418         struct pipe_query               *current_render_cond;
 419         unsigned                        current_render_cond_mode;
 420         boolean                         current_render_cond_cond;
 421         boolean                         predicate_drawing;
 422         /* For context flushing. */
 423         struct pipe_query               *saved_render_cond;
 424         boolean                         saved_render_cond_cond;
 425         unsigned                        saved_render_cond_mode;
 426
 427         /* MSAA sample locations.
 428          * The first index is the sample index.
 429          * The second index is the coordinate: X, Y. */
 430         float                           sample_locations_1x[1][2];
 431         float                           sample_locations_2x[2][2];
 432         float                           sample_locations_4x[4][2];
 433         float                           sample_locations_8x[8][2];
 434         float                           sample_locations_16x[16][2];
 435
 436         /* The list of all texture buffer objects in this context.
 437          * This list is walked when a buffer is invalidated/reallocated and
 438          * the GPU addresses are updated. */
 439         struct list_head                texture_buffers;
 440
 441         /* Copy one resource to another using async DMA. */
 442         void (*dma_copy)(struct pipe_context *ctx,
 443                          struct pipe_resource *dst,
 444                          unsigned dst_level,
 445                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 446                          struct pipe_resource *src,
 447                          unsigned src_level,
 448                          const struct pipe_box *src_box);
 449
 450         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 451                              unsigned offset, unsigned size, unsigned value,
 452                              bool is_framebuffer);
 453
 454         void (*blit_decompress_depth)(struct pipe_context *ctx,
 455                                       struct r600_texture *texture,
 456                                       struct r600_texture *staging,
 457                                       unsigned first_level, unsigned last_level,
 458                                       unsigned first_layer, unsigned last_layer,
 459                                       unsigned first_sample, unsigned last_sample);
 460
 461         /* Reallocate the buffer and update all resource bindings where
 462          * the buffer is bound, including all resource descriptors. */
 463         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 464
 465         /* Enable or disable occlusion queries. */
 466         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 467
 468         /* This ensures there is enough space in the command stream. */
 469         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 470                                   bool include_draw_vbo);
 471
 472         void (*set_atom_dirty)(struct r600_common_context *ctx,
 473                                struct r600_atom *atom, bool dirty);
 474 };
 475
 476 /* r600_buffer.c */
 477 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 478                                         struct radeon_winsys_cs_handle *buf,
 479                                         enum radeon_bo_usage usage);
 480 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 481                                       struct r600_resource *resource,
 482                                       unsigned usage);
 483 bool r600_init_resource(struct r600_common_screen *rscreen,
 484                         struct r600_resource *res,
 485                         unsigned size, unsigned alignment,
 486                         bool use_reusable_pool);
 487 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 488                                          const struct pipe_resource *templ,
 489                                          unsigned alignment);
 490 struct pipe_resource *
 491 r600_buffer_from_user_memory(struct pipe_screen *screen,
 492                              const struct pipe_resource *templ,
 493                              void *user_memory);
 494
 495 /* r600_common_pipe.c */
 496 void r600_draw_rectangle(struct blitter_context *blitter,
 497                          int x1, int y1, int x2, int y2, float depth,
 498                          enum blitter_attrib_type type,
 499                          const union pipe_color_union *attrib);
 500 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 501                              struct radeon_winsys *ws);
 502 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 503 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 504 void r600_postflush_resume_features(struct r600_common_context *ctx);
 505 bool r600_common_context_init(struct r600_common_context *rctx,
 506                               struct r600_common_screen *rscreen);
 507 void r600_common_context_cleanup(struct r600_common_context *rctx);
 508 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 509 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 510                           const struct tgsi_token *tokens);
 511 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 512                               unsigned offset, unsigned size, unsigned value,
 513                               bool is_framebuffer);
 514 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 515                                                   const struct pipe_resource *templ);
 516 const char *r600_get_llvm_processor_name(enum radeon_family family);
 517 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw);
 518
 519 /* r600_gpu_load.c */
 520 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 521 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
 522 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 523
 524 /* r600_query.c */
 525 void r600_query_init(struct r600_common_context *rctx);
 526 void r600_suspend_nontimer_queries(struct r600_common_context *ctx);
 527 void r600_resume_nontimer_queries(struct r600_common_context *ctx);
 528 void r600_suspend_timer_queries(struct r600_common_context *ctx);
 529 void r600_resume_timer_queries(struct r600_common_context *ctx);
 530 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 531
 532 /* r600_streamout.c */
 533 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 534 void r600_set_streamout_targets(struct pipe_context *ctx,
 535                                 unsigned num_targets,
 536                                 struct pipe_stream_output_target **targets,
 537                                 const unsigned *offset);
 538 void r600_emit_streamout_end(struct r600_common_context *rctx);
 539 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 540                                              unsigned type, int diff);
 541 void r600_streamout_init(struct r600_common_context *rctx);
 542
 543 /* r600_texture.c */
 544 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 545                                  struct r600_texture *rtex,
 546                                  unsigned nr_samples,
 547                                  struct r600_fmask_info *out);
 548 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 549                                  struct r600_texture *rtex,
 550                                  struct r600_cmask_info *out);
 551 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 552                                      struct pipe_resource *texture,
 553                                      struct r600_texture **staging);
 554 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 555                                         const struct pipe_resource *templ);
 556 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 557                                                 struct pipe_resource *texture,
 558                                                 const struct pipe_surface *templ,
 559                                                 unsigned width, unsigned height);
 560 unsigned r600_translate_colorswap(enum pipe_format format);
 561 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 562                                    struct pipe_framebuffer_state *fb,
 563                                    struct r600_atom *fb_state,
 564                                    unsigned *buffers,
 565                                    const union pipe_color_union *color);
 566 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 567 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 568
 569 /* cayman_msaa.c */
 570 extern const uint32_t eg_sample_locs_2x[4];
 571 extern const unsigned eg_max_dist_2x;
 572 extern const uint32_t eg_sample_locs_4x[4];
 573 extern const unsigned eg_max_dist_4x;
 574 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 575                                 unsigned sample_index, float *out_value);
 576 void cayman_init_msaa(struct pipe_context *ctx);
 577 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 578 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 579                              int ps_iter_samples, int overrast_samples);
 580
 581
 582 /* Inline helpers. */
 583
 584 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 585 {
 586         return (struct r600_resource*)r;
 587 }
 588
 589 static inline void
 590 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 591 {
 592         pipe_resource_reference((struct pipe_resource **)ptr,
 593                                 (struct pipe_resource *)res);
 594 }
 595
 596 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 597 {
 598         if (filter <= 1)   return 0;
 599         if (filter <= 2)   return 1;
 600         if (filter <= 4)   return 2;
 601         if (filter <= 8)   return 3;
 602          /* else */        return 4;
 603 }
 604
 605 static inline unsigned r600_wavefront_size(enum radeon_family family)
 606 {
 607         switch (family) {
 608         case CHIP_RV610:
 609         case CHIP_RS780:
 610         case CHIP_RV620:
 611         case CHIP_RS880:
 612                 return 16;
 613         case CHIP_RV630:
 614         case CHIP_RV635:
 615         case CHIP_RV730:
 616         case CHIP_RV710:
 617         case CHIP_PALM:
 618         case CHIP_CEDAR:
 619                 return 32;
 620         default:
 621                 return 64;
 622         }
 623 }
 624
 625 #define COMPUTE_DBG(rscreen, fmt, args...) \
 626         do { \
 627                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 628         } while (0);
 629
 630 #define R600_ERR(fmt, args...) \
 631         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
 632
 633 /* For MSAA sample positions. */
 634 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 635         (((s0x) & 0xf) | (((s0y) & 0xf) << 4) |            \
 636         (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |     \
 637         (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |    \
 638          (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
 639
 640 #endif