2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * This file contains common screen and context structures and functions
26 * for r600g and radeonsi.
29 #ifndef R600_PIPE_COMMON_H
30 #define R600_PIPE_COMMON_H
34 #include "amd/common/ac_binary.h"
36 #include "radeon/radeon_winsys.h"
38 #include "util/disk_cache.h"
39 #include "util/u_blitter.h"
40 #include "util/list.h"
41 #include "util/u_range.h"
42 #include "util/slab.h"
43 #include "util/u_suballoc.h"
44 #include "util/u_transfer.h"
45 #include "util/u_threaded_context.h"
51 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
52 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
53 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
54 #define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
55 #define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
56 #define R600_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
57 #define R600_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
61 /* Shader logging options: */
62 DBG_VS
= PIPE_SHADER_VERTEX
,
63 DBG_PS
= PIPE_SHADER_FRAGMENT
,
64 DBG_GS
= PIPE_SHADER_GEOMETRY
,
65 DBG_TCS
= PIPE_SHADER_TESS_CTRL
,
66 DBG_TES
= PIPE_SHADER_TESS_EVAL
,
67 DBG_CS
= PIPE_SHADER_COMPUTE
,
73 /* Shader compiler options the shader cache should be aware of: */
74 DBG_FS_CORRECT_DERIVS_AFTER_KILL
,
78 /* Shader compiler options (with no effect on the shader cache): */
81 DBG_MONOLITHIC_SHADERS
,
84 /* Information logging options: */
97 /* 3D engine options: */
118 DBG_TEST_VMFAULT_SDMA
,
119 DBG_TEST_VMFAULT_SHADER
,
122 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
123 #define DBG(name) (1ull << DBG_##name)
125 #define R600_MAP_BUFFER_ALIGNMENT 64
127 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
129 struct r600_common_context
;
130 struct r600_perfcounters
;
131 struct tgsi_shader_info
;
132 struct r600_qbo_state
;
134 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
137 struct r600_resource
{
138 struct threaded_resource b
;
140 /* Winsys objects. */
141 struct pb_buffer
*buf
;
142 uint64_t gpu_address
;
143 /* Memory usage if the buffer placement is optimal. */
147 /* Resource properties. */
149 unsigned bo_alignment
;
150 enum radeon_bo_domain domains
;
151 enum radeon_bo_flag flags
;
152 unsigned bind_history
;
153 int max_forced_staging_uploads
;
155 /* The buffer range which is initialized (with a write transfer,
156 * streamout, DMA, or as a random access target). The rest of
157 * the buffer is considered invalid and can be mapped unsynchronized.
159 * This allows unsychronized mapping of a buffer range which hasn't
160 * been used yet. It's for applications which forget to use
161 * the unsynchronized map flag and expect the driver to figure it out.
163 struct util_range valid_buffer_range
;
165 /* For buffers only. This indicates that a write operation has been
166 * performed by TC L2, but the cache hasn't been flushed.
167 * Any hw block which doesn't use or bypasses TC L2 should check this
168 * flag and flush the cache before using the buffer.
170 * For example, TC L2 must be flushed if a buffer which has been
171 * modified by a shader store instruction is about to be used as
172 * an index buffer. The reason is that VGT DMA index fetching doesn't
177 /* Whether the resource has been exported via resource_get_handle. */
178 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
180 /* Whether this resource is referenced by bindless handles. */
181 bool texture_handle_allocated
;
182 bool image_handle_allocated
;
185 struct r600_transfer
{
186 struct threaded_transfer b
;
187 struct r600_resource
*staging
;
191 struct r600_fmask_info
{
195 unsigned pitch_in_pixels
;
196 unsigned bank_height
;
197 unsigned slice_tile_max
;
198 unsigned tile_mode_index
;
199 unsigned tile_swizzle
;
202 struct r600_cmask_info
{
206 unsigned slice_tile_max
;
207 uint64_t base_address_reg
;
210 struct r600_texture
{
211 struct r600_resource resource
;
213 struct radeon_surf surface
;
215 struct r600_texture
*flushed_depth_texture
;
217 /* Colorbuffer compression and fast clear. */
218 struct r600_fmask_info fmask
;
219 struct r600_cmask_info cmask
;
220 struct r600_resource
*cmask_buffer
;
221 uint64_t dcc_offset
; /* 0 = disabled */
222 unsigned cb_color_info
; /* fast clear enable bit */
223 unsigned color_clear_value
[2];
224 unsigned last_msaa_resolve_target_micro_mode
;
225 unsigned num_level0_transfers
;
227 /* Depth buffer compression and fast clear. */
228 uint64_t htile_offset
;
229 float depth_clear_value
;
230 uint16_t dirty_level_mask
; /* each bit says if that mipmap is compressed */
231 uint16_t stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
232 enum pipe_format db_render_format
:16;
233 uint8_t stencil_clear_value
;
234 bool tc_compatible_htile
:1;
235 bool depth_cleared
:1; /* if it was cleared at least once */
236 bool stencil_cleared
:1; /* if it was cleared at least once */
237 bool upgraded_depth
:1; /* upgraded from unorm to Z32_FLOAT */
239 bool db_compatible
:1;
243 /* We need to track DCC dirtiness, because st/dri usually calls
244 * flush_resource twice per frame (not a bug) and we don't wanna
245 * decompress DCC twice. Also, the dirty tracking must be done even
246 * if DCC isn't used, because it's required by the DCC usage analysis
247 * for a possible future enablement.
249 bool separate_dcc_dirty
:1;
250 /* Statistics gathering for the DCC enablement heuristic. */
251 bool dcc_gather_statistics
:1;
252 /* Counter that should be non-zero if the texture is bound to a
255 unsigned framebuffers_bound
;
256 /* Whether the texture is a displayable back buffer and needs DCC
257 * decompression, which is expensive. Therefore, it's enabled only
258 * if statistics suggest that it will pay off and it's allocated
259 * separately. It can't be bound as a sampler by apps. Limited to
260 * target == 2D and last_level == 0. If enabled, dcc_offset contains
261 * the absolute GPUVM address, not the relative one.
263 struct r600_resource
*dcc_separate_buffer
;
264 /* When DCC is temporarily disabled, the separate buffer is here. */
265 struct r600_resource
*last_dcc_separate_buffer
;
266 /* Estimate of how much this color buffer is written to in units of
267 * full-screen draws: ps_invocations / (width * height)
268 * Shader kills, late Z, and blending with trivial discards make it
269 * inaccurate (we need to count CB updates, not PS invocations).
271 unsigned ps_draw_ratio
;
272 /* The number of clears since the last DCC usage analysis. */
273 unsigned num_slow_clears
;
276 struct r600_surface
{
277 struct pipe_surface base
;
279 /* These can vary with block-compressed textures. */
283 bool color_initialized
:1;
284 bool depth_initialized
:1;
286 /* Misc. color flags. */
287 bool color_is_int8
:1;
288 bool color_is_int10
:1;
289 bool dcc_incompatible
:1;
291 /* Color registers. */
292 unsigned cb_color_info
;
293 unsigned cb_color_view
;
294 unsigned cb_color_attrib
;
295 unsigned cb_color_attrib2
; /* GFX9 and later */
296 unsigned cb_dcc_control
; /* VI and later */
297 unsigned spi_shader_col_format
:8; /* no blending, no alpha-to-coverage. */
298 unsigned spi_shader_col_format_alpha
:8; /* alpha-to-coverage */
299 unsigned spi_shader_col_format_blend
:8; /* blending without alpha. */
300 unsigned spi_shader_col_format_blend_alpha
:8; /* blending with alpha. */
303 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE */
304 uint64_t db_stencil_base
;
305 uint64_t db_htile_data_base
;
306 unsigned db_depth_info
;
308 unsigned db_z_info2
; /* GFX9+ */
309 unsigned db_depth_view
;
310 unsigned db_depth_size
;
311 unsigned db_depth_slice
;
312 unsigned db_stencil_info
;
313 unsigned db_stencil_info2
; /* GFX9+ */
314 unsigned db_htile_surface
;
317 struct r600_mmio_counter
{
322 union r600_mmio_counters
{
324 /* For global GPU load including SDMA. */
325 struct r600_mmio_counter gpu
;
328 struct r600_mmio_counter spi
;
329 struct r600_mmio_counter gui
;
330 struct r600_mmio_counter ta
;
331 struct r600_mmio_counter gds
;
332 struct r600_mmio_counter vgt
;
333 struct r600_mmio_counter ia
;
334 struct r600_mmio_counter sx
;
335 struct r600_mmio_counter wd
;
336 struct r600_mmio_counter bci
;
337 struct r600_mmio_counter sc
;
338 struct r600_mmio_counter pa
;
339 struct r600_mmio_counter db
;
340 struct r600_mmio_counter cp
;
341 struct r600_mmio_counter cb
;
344 struct r600_mmio_counter sdma
;
347 struct r600_mmio_counter pfp
;
348 struct r600_mmio_counter meq
;
349 struct r600_mmio_counter me
;
350 struct r600_mmio_counter surf_sync
;
351 struct r600_mmio_counter cp_dma
;
352 struct r600_mmio_counter scratch_ram
;
357 struct r600_memory_object
{
358 struct pipe_memory_object b
;
359 struct pb_buffer
*buf
;
364 /* This encapsulates a state or an operation which can emitted into the GPU
367 void (*emit
)(struct r600_common_context
*ctx
, struct r600_atom
*state
);
372 struct radeon_winsys_cs
*cs
;
373 void (*flush
)(void *ctx
, unsigned flags
,
374 struct pipe_fence_handle
**fence
);
377 /* Saved CS data for debugging features. */
378 struct radeon_saved_cs
{
382 struct radeon_bo_list_item
*bo_list
;
386 struct r600_common_context
{
387 struct pipe_context b
; /* base class */
389 struct si_screen
*screen
;
390 struct radeon_winsys
*ws
;
391 struct radeon_winsys_ctx
*ctx
;
392 enum radeon_family family
;
393 enum chip_class chip_class
;
394 struct r600_ring gfx
;
395 struct r600_ring dma
;
396 struct pipe_fence_handle
*last_gfx_fence
;
397 struct pipe_fence_handle
*last_sdma_fence
;
398 struct r600_resource
*eop_bug_scratch
;
399 struct u_upload_mgr
*cached_gtt_allocator
;
400 unsigned num_gfx_cs_flushes
;
401 unsigned initial_gfx_cs_size
;
402 unsigned gpu_reset_counter
;
403 unsigned last_dirty_tex_counter
;
404 unsigned last_compressed_colortex_counter
;
405 unsigned last_num_draw_calls
;
407 struct threaded_context
*tc
;
408 struct u_suballocator
*allocator_zeroed_memory
;
409 struct slab_child_pool pool_transfers
;
410 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
412 /* Current unaccounted memory usage. */
416 /* Additional context states. */
417 unsigned flags
; /* flush flags */
420 /* Maintain the list of active queries for pausing between IBs. */
421 int num_occlusion_queries
;
422 int num_perfect_occlusion_queries
;
423 struct list_head active_queries
;
424 unsigned num_cs_dw_queries_suspend
;
426 unsigned num_draw_calls
;
427 unsigned num_decompress_calls
;
428 unsigned num_mrt_draw_calls
;
429 unsigned num_prim_restart_calls
;
430 unsigned num_spill_draw_calls
;
431 unsigned num_compute_calls
;
432 unsigned num_spill_compute_calls
;
433 unsigned num_dma_calls
;
434 unsigned num_cp_dma_calls
;
435 unsigned num_vs_flushes
;
436 unsigned num_ps_flushes
;
437 unsigned num_cs_flushes
;
438 unsigned num_cb_cache_flushes
;
439 unsigned num_db_cache_flushes
;
440 unsigned num_L2_invalidates
;
441 unsigned num_L2_writebacks
;
442 unsigned num_resident_handles
;
443 uint64_t num_alloc_tex_transfer_bytes
;
444 unsigned last_tex_ps_draw_ratio
; /* for query */
446 /* Render condition. */
447 struct r600_atom render_cond_atom
;
448 struct pipe_query
*render_cond
;
449 unsigned render_cond_mode
;
450 bool render_cond_invert
;
451 bool render_cond_force_off
; /* for u_blitter */
453 /* Statistics gathering for the DCC enablement heuristic. It can't be
454 * in r600_texture because r600_texture can be shared by multiple
455 * contexts. This is for back buffers only. We shouldn't get too many
458 * X11 DRI3 rotates among a finite set of back buffers. They should
459 * all fit in this array. If they don't, separate DCC might never be
460 * enabled by DCC stat gathering.
463 struct r600_texture
*tex
;
464 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
465 struct pipe_query
*ps_stats
[3];
466 /* If all slots are used and another slot is needed,
467 * the least recently used slot is evicted based on this. */
468 int64_t last_use_timestamp
;
472 struct pipe_device_reset_callback device_reset_callback
;
473 struct u_log_context
*log
;
475 void *query_result_shader
;
477 /* Copy one resource to another using async DMA. */
478 void (*dma_copy
)(struct pipe_context
*ctx
,
479 struct pipe_resource
*dst
,
481 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
482 struct pipe_resource
*src
,
484 const struct pipe_box
*src_box
);
486 void (*dma_clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
487 uint64_t offset
, uint64_t size
, unsigned value
);
489 void (*blit_decompress_depth
)(struct pipe_context
*ctx
,
490 struct r600_texture
*texture
,
491 struct r600_texture
*staging
,
492 unsigned first_level
, unsigned last_level
,
493 unsigned first_layer
, unsigned last_layer
,
494 unsigned first_sample
, unsigned last_sample
);
496 void (*decompress_dcc
)(struct pipe_context
*ctx
,
497 struct r600_texture
*rtex
);
499 /* Reallocate the buffer and update all resource bindings where
500 * the buffer is bound, including all resource descriptors. */
501 void (*invalidate_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
);
504 /* r600_buffer_common.c */
505 bool si_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
506 struct pb_buffer
*buf
,
507 enum radeon_bo_usage usage
);
508 void *si_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
509 struct r600_resource
*resource
,
511 void si_init_resource_fields(struct si_screen
*sscreen
,
512 struct r600_resource
*res
,
513 uint64_t size
, unsigned alignment
);
514 bool si_alloc_resource(struct si_screen
*sscreen
,
515 struct r600_resource
*res
);
516 struct pipe_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
521 void si_replace_buffer_storage(struct pipe_context
*ctx
,
522 struct pipe_resource
*dst
,
523 struct pipe_resource
*src
);
524 void si_init_screen_buffer_functions(struct si_screen
*sscreen
);
525 void si_init_buffer_functions(struct si_context
*sctx
);
527 /* r600_common_pipe.c */
528 void si_gfx_write_event_eop(struct r600_common_context
*ctx
,
529 unsigned event
, unsigned event_flags
,
531 struct r600_resource
*buf
, uint64_t va
,
532 uint32_t new_fence
, unsigned query_type
);
533 unsigned si_gfx_write_fence_dwords(struct si_screen
*screen
);
534 void si_gfx_wait_fence(struct r600_common_context
*ctx
,
535 uint64_t va
, uint32_t ref
, uint32_t mask
);
536 bool si_common_context_init(struct r600_common_context
*rctx
,
537 struct si_screen
*sscreen
,
538 unsigned context_flags
);
539 void si_common_context_cleanup(struct r600_common_context
*rctx
);
540 void si_screen_clear_buffer(struct si_screen
*sscreen
, struct pipe_resource
*dst
,
541 uint64_t offset
, uint64_t size
, unsigned value
);
542 void si_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
,
543 struct r600_resource
*dst
, struct r600_resource
*src
);
544 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_winsys_cs
*cs
,
545 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
546 void si_clear_saved_cs(struct radeon_saved_cs
*saved
);
547 bool si_check_device_reset(struct r600_common_context
*rctx
);
548 void si_flush_dma_cs(void *ctx
, unsigned flags
, struct pipe_fence_handle
**fence
);
550 /* r600_gpu_load.c */
551 void si_gpu_load_kill_thread(struct si_screen
*sscreen
);
552 uint64_t si_begin_counter(struct si_screen
*sscreen
, unsigned type
);
553 unsigned si_end_counter(struct si_screen
*sscreen
, unsigned type
,
556 /* r600_perfcounters.c */
557 void si_perfcounters_destroy(struct si_screen
*sscreen
);
560 void si_init_screen_query_functions(struct si_screen
*sscreen
);
561 void si_init_query_functions(struct r600_common_context
*rctx
);
562 void si_suspend_queries(struct r600_common_context
*ctx
);
563 void si_resume_queries(struct r600_common_context
*ctx
);
566 bool si_prepare_for_dma_blit(struct r600_common_context
*rctx
,
567 struct r600_texture
*rdst
,
568 unsigned dst_level
, unsigned dstx
,
569 unsigned dsty
, unsigned dstz
,
570 struct r600_texture
*rsrc
,
572 const struct pipe_box
*src_box
);
573 void si_texture_get_fmask_info(struct si_screen
*sscreen
,
574 struct r600_texture
*rtex
,
576 struct r600_fmask_info
*out
);
577 void si_texture_get_cmask_info(struct si_screen
*sscreen
,
578 struct r600_texture
*rtex
,
579 struct r600_cmask_info
*out
);
580 void si_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
581 struct r600_texture
*rtex
);
582 void si_texture_discard_cmask(struct si_screen
*sscreen
,
583 struct r600_texture
*rtex
);
584 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
585 struct pipe_resource
*texture
,
586 struct r600_texture
**staging
);
587 void si_print_texture_info(struct si_screen
*sscreen
,
588 struct r600_texture
*rtex
, struct u_log_context
*log
);
589 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
590 const struct pipe_resource
*templ
);
591 bool vi_dcc_formats_compatible(enum pipe_format format1
,
592 enum pipe_format format2
);
593 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
595 enum pipe_format view_format
);
596 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
597 struct pipe_resource
*tex
,
599 enum pipe_format view_format
);
600 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
601 struct pipe_resource
*texture
,
602 const struct pipe_surface
*templ
,
603 unsigned width0
, unsigned height0
,
604 unsigned width
, unsigned height
);
605 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
606 void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
607 struct r600_texture
*tex
);
608 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
609 struct r600_texture
*tex
);
610 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
611 struct r600_texture
*tex
);
612 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
613 struct r600_texture
*tex
);
614 bool si_texture_disable_dcc(struct r600_common_context
*rctx
,
615 struct r600_texture
*rtex
);
616 void si_init_screen_texture_functions(struct si_screen
*sscreen
);
617 void si_init_context_texture_functions(struct r600_common_context
*rctx
);
620 /* Inline helpers. */
622 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
624 return (struct r600_resource
*)r
;
628 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
630 pipe_resource_reference((struct pipe_resource
**)ptr
,
631 (struct pipe_resource
*)res
);
635 r600_texture_reference(struct r600_texture
**ptr
, struct r600_texture
*res
)
637 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->resource
.b
.b
);
641 vi_dcc_enabled(struct r600_texture
*tex
, unsigned level
)
643 return tex
->dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
646 #define R600_ERR(fmt, args...) \
647 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)