2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * This file contains common screen and context structures and functions
26 * for r600g and radeonsi.
29 #ifndef R600_PIPE_COMMON_H
30 #define R600_PIPE_COMMON_H
34 #include "amd/common/ac_binary.h"
36 #include "radeon/radeon_winsys.h"
38 #include "util/disk_cache.h"
39 #include "util/u_blitter.h"
40 #include "util/list.h"
41 #include "util/u_range.h"
42 #include "util/slab.h"
43 #include "util/u_suballoc.h"
44 #include "util/u_transfer.h"
45 #include "util/u_threaded_context.h"
49 #define ATI_VENDOR_ID 0x1002
51 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
52 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
53 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
54 #define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
55 #define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
57 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
58 /* Pipeline & streamout query controls. */
59 #define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
60 #define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
61 #define R600_CONTEXT_FLUSH_FOR_RENDER_COND (1u << 3)
62 #define R600_CONTEXT_PRIVATE_FLAG (1u << 4)
64 /* special primitive types */
65 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
67 #define R600_NOT_QUERY 0xffffffff
71 /* Shader logging options: */
72 DBG_VS
= PIPE_SHADER_VERTEX
,
73 DBG_PS
= PIPE_SHADER_FRAGMENT
,
74 DBG_GS
= PIPE_SHADER_GEOMETRY
,
75 DBG_TCS
= PIPE_SHADER_TESS_CTRL
,
76 DBG_TES
= PIPE_SHADER_TESS_EVAL
,
77 DBG_CS
= PIPE_SHADER_COMPUTE
,
83 /* Shader compiler options the shader cache should be aware of: */
84 DBG_FS_CORRECT_DERIVS_AFTER_KILL
,
88 /* Shader compiler options (with no effect on the shader cache): */
92 DBG_MONOLITHIC_SHADERS
,
95 /* Information logging options: */
101 /* Driver options: */
108 /* 3D engine options: */
126 DBG_TEST_VMFAULT_SDMA
,
127 DBG_TEST_VMFAULT_SHADER
,
130 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
131 #define DBG(name) (1ull << DBG_##name)
133 #define R600_MAP_BUFFER_ALIGNMENT 64
135 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
137 enum r600_coherency
{
138 R600_COHERENCY_NONE
, /* no cache flushes needed */
139 R600_COHERENCY_SHADER
,
140 R600_COHERENCY_CB_META
,
143 #ifdef PIPE_ARCH_BIG_ENDIAN
144 #define R600_BIG_ENDIAN 1
146 #define R600_BIG_ENDIAN 0
149 struct r600_common_context
;
150 struct r600_perfcounters
;
151 struct tgsi_shader_info
;
152 struct r600_qbo_state
;
154 void si_radeon_shader_binary_init(struct ac_shader_binary
*b
);
155 void si_radeon_shader_binary_clean(struct ac_shader_binary
*b
);
157 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
160 struct r600_resource
{
161 struct threaded_resource b
;
163 /* Winsys objects. */
164 struct pb_buffer
*buf
;
165 uint64_t gpu_address
;
166 /* Memory usage if the buffer placement is optimal. */
170 /* Resource properties. */
172 unsigned bo_alignment
;
173 enum radeon_bo_domain domains
;
174 enum radeon_bo_flag flags
;
175 unsigned bind_history
;
176 int max_forced_staging_uploads
;
178 /* The buffer range which is initialized (with a write transfer,
179 * streamout, DMA, or as a random access target). The rest of
180 * the buffer is considered invalid and can be mapped unsynchronized.
182 * This allows unsychronized mapping of a buffer range which hasn't
183 * been used yet. It's for applications which forget to use
184 * the unsynchronized map flag and expect the driver to figure it out.
186 struct util_range valid_buffer_range
;
188 /* For buffers only. This indicates that a write operation has been
189 * performed by TC L2, but the cache hasn't been flushed.
190 * Any hw block which doesn't use or bypasses TC L2 should check this
191 * flag and flush the cache before using the buffer.
193 * For example, TC L2 must be flushed if a buffer which has been
194 * modified by a shader store instruction is about to be used as
195 * an index buffer. The reason is that VGT DMA index fetching doesn't
200 /* Whether the resource has been exported via resource_get_handle. */
201 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
203 /* Whether this resource is referenced by bindless handles. */
204 bool texture_handle_allocated
;
205 bool image_handle_allocated
;
208 struct r600_transfer
{
209 struct threaded_transfer b
;
210 struct r600_resource
*staging
;
214 struct r600_fmask_info
{
218 unsigned pitch_in_pixels
;
219 unsigned bank_height
;
220 unsigned slice_tile_max
;
221 unsigned tile_mode_index
;
222 unsigned tile_swizzle
;
225 struct r600_cmask_info
{
229 unsigned slice_tile_max
;
230 uint64_t base_address_reg
;
233 struct r600_texture
{
234 struct r600_resource resource
;
236 struct radeon_surf surface
;
238 struct r600_texture
*flushed_depth_texture
;
240 /* Colorbuffer compression and fast clear. */
241 struct r600_fmask_info fmask
;
242 struct r600_cmask_info cmask
;
243 struct r600_resource
*cmask_buffer
;
244 uint64_t dcc_offset
; /* 0 = disabled */
245 unsigned cb_color_info
; /* fast clear enable bit */
246 unsigned color_clear_value
[2];
247 unsigned last_msaa_resolve_target_micro_mode
;
248 unsigned num_level0_transfers
;
250 /* Depth buffer compression and fast clear. */
251 uint64_t htile_offset
;
252 float depth_clear_value
;
253 uint16_t dirty_level_mask
; /* each bit says if that mipmap is compressed */
254 uint16_t stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
255 enum pipe_format db_render_format
:16;
256 uint8_t stencil_clear_value
;
257 bool tc_compatible_htile
:1;
258 bool depth_cleared
:1; /* if it was cleared at least once */
259 bool stencil_cleared
:1; /* if it was cleared at least once */
260 bool upgraded_depth
:1; /* upgraded from unorm to Z32_FLOAT */
262 bool db_compatible
:1;
266 /* We need to track DCC dirtiness, because st/dri usually calls
267 * flush_resource twice per frame (not a bug) and we don't wanna
268 * decompress DCC twice. Also, the dirty tracking must be done even
269 * if DCC isn't used, because it's required by the DCC usage analysis
270 * for a possible future enablement.
272 bool separate_dcc_dirty
:1;
273 /* Statistics gathering for the DCC enablement heuristic. */
274 bool dcc_gather_statistics
:1;
275 /* Counter that should be non-zero if the texture is bound to a
278 unsigned framebuffers_bound
;
279 /* Whether the texture is a displayable back buffer and needs DCC
280 * decompression, which is expensive. Therefore, it's enabled only
281 * if statistics suggest that it will pay off and it's allocated
282 * separately. It can't be bound as a sampler by apps. Limited to
283 * target == 2D and last_level == 0. If enabled, dcc_offset contains
284 * the absolute GPUVM address, not the relative one.
286 struct r600_resource
*dcc_separate_buffer
;
287 /* When DCC is temporarily disabled, the separate buffer is here. */
288 struct r600_resource
*last_dcc_separate_buffer
;
289 /* Estimate of how much this color buffer is written to in units of
290 * full-screen draws: ps_invocations / (width * height)
291 * Shader kills, late Z, and blending with trivial discards make it
292 * inaccurate (we need to count CB updates, not PS invocations).
294 unsigned ps_draw_ratio
;
295 /* The number of clears since the last DCC usage analysis. */
296 unsigned num_slow_clears
;
299 struct r600_surface
{
300 struct pipe_surface base
;
302 /* These can vary with block-compressed textures. */
306 bool color_initialized
:1;
307 bool depth_initialized
:1;
309 /* Misc. color flags. */
310 bool color_is_int8
:1;
311 bool color_is_int10
:1;
312 bool dcc_incompatible
:1;
314 /* Color registers. */
315 unsigned cb_color_info
;
316 unsigned cb_color_view
;
317 unsigned cb_color_attrib
;
318 unsigned cb_color_attrib2
; /* GFX9 and later */
319 unsigned cb_dcc_control
; /* VI and later */
320 unsigned spi_shader_col_format
:8; /* no blending, no alpha-to-coverage. */
321 unsigned spi_shader_col_format_alpha
:8; /* alpha-to-coverage */
322 unsigned spi_shader_col_format_blend
:8; /* blending without alpha. */
323 unsigned spi_shader_col_format_blend_alpha
:8; /* blending with alpha. */
326 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE */
327 uint64_t db_stencil_base
;
328 uint64_t db_htile_data_base
;
329 unsigned db_depth_info
;
331 unsigned db_z_info2
; /* GFX9+ */
332 unsigned db_depth_view
;
333 unsigned db_depth_size
;
334 unsigned db_depth_slice
;
335 unsigned db_stencil_info
;
336 unsigned db_stencil_info2
; /* GFX9+ */
337 unsigned db_htile_surface
;
340 struct r600_mmio_counter
{
345 union r600_mmio_counters
{
347 /* For global GPU load including SDMA. */
348 struct r600_mmio_counter gpu
;
351 struct r600_mmio_counter spi
;
352 struct r600_mmio_counter gui
;
353 struct r600_mmio_counter ta
;
354 struct r600_mmio_counter gds
;
355 struct r600_mmio_counter vgt
;
356 struct r600_mmio_counter ia
;
357 struct r600_mmio_counter sx
;
358 struct r600_mmio_counter wd
;
359 struct r600_mmio_counter bci
;
360 struct r600_mmio_counter sc
;
361 struct r600_mmio_counter pa
;
362 struct r600_mmio_counter db
;
363 struct r600_mmio_counter cp
;
364 struct r600_mmio_counter cb
;
367 struct r600_mmio_counter sdma
;
370 struct r600_mmio_counter pfp
;
371 struct r600_mmio_counter meq
;
372 struct r600_mmio_counter me
;
373 struct r600_mmio_counter surf_sync
;
374 struct r600_mmio_counter cp_dma
;
375 struct r600_mmio_counter scratch_ram
;
380 struct r600_memory_object
{
381 struct pipe_memory_object b
;
382 struct pb_buffer
*buf
;
387 struct r600_common_screen
{
388 struct pipe_screen b
;
389 struct radeon_winsys
*ws
;
390 enum radeon_family family
;
391 enum chip_class chip_class
;
392 struct radeon_info info
;
393 uint64_t debug_flags
;
394 bool has_rbplus
; /* if RB+ registers exist */
395 bool rbplus_allowed
; /* if RB+ is allowed */
397 struct disk_cache
*disk_shader_cache
;
399 struct slab_parent_pool pool_transfers
;
401 /* Texture filter settings. */
402 int force_aniso
; /* -1 = disabled */
404 /* Auxiliary context. Mainly used to initialize resources.
405 * It must be locked prior to using and flushed before unlocking. */
406 struct pipe_context
*aux_context
;
407 mtx_t aux_context_lock
;
409 /* This must be in the screen, because UE4 uses one context for
410 * compilation and another one for rendering.
412 unsigned num_compilations
;
413 /* Along with ST_DEBUG=precompile, this should show if applications
414 * are loading shaders on demand. This is a monotonic counter.
416 unsigned num_shaders_created
;
417 unsigned num_shader_cache_hits
;
419 /* GPU load thread. */
420 mtx_t gpu_load_mutex
;
421 thrd_t gpu_load_thread
;
422 union r600_mmio_counters mmio_counters
;
423 volatile unsigned gpu_load_stop_thread
; /* bool */
425 char renderer_string
[100];
427 /* Performance counters. */
428 struct r600_perfcounters
*perfcounters
;
430 /* If pipe_screen wants to recompute and re-emit the framebuffer,
431 * sampler, and image states of all contexts, it should atomically
434 * Each context will compare this with its own last known value of
435 * the counter before drawing and re-emit the states accordingly.
437 unsigned dirty_tex_counter
;
439 /* Atomically increment this counter when an existing texture's
440 * metadata is enabled or disabled in a way that requires changing
441 * contexts' compressed texture binding masks.
443 unsigned compressed_colortex_counter
;
446 /* Context flags to set so that all writes from earlier jobs
447 * in the CP are seen by L2 clients.
451 /* Context flags to set so that all writes from earlier jobs
452 * that end in L2 are seen by CP.
456 /* Context flags to set so that all writes from earlier
457 * compute jobs are seen by L2 clients.
459 unsigned compute_to_L2
;
462 void (*query_opaque_metadata
)(struct r600_common_screen
*rscreen
,
463 struct r600_texture
*rtex
,
464 struct radeon_bo_metadata
*md
);
466 void (*apply_opaque_metadata
)(struct r600_common_screen
*rscreen
,
467 struct r600_texture
*rtex
,
468 struct radeon_bo_metadata
*md
);
471 /* This encapsulates a state or an operation which can emitted into the GPU
474 void (*emit
)(struct r600_common_context
*ctx
, struct r600_atom
*state
);
479 struct radeon_winsys_cs
*cs
;
480 void (*flush
)(void *ctx
, unsigned flags
,
481 struct pipe_fence_handle
**fence
);
484 /* Saved CS data for debugging features. */
485 struct radeon_saved_cs
{
489 struct radeon_bo_list_item
*bo_list
;
493 struct r600_common_context
{
494 struct pipe_context b
; /* base class */
496 struct r600_common_screen
*screen
;
497 struct radeon_winsys
*ws
;
498 struct radeon_winsys_ctx
*ctx
;
499 enum radeon_family family
;
500 enum chip_class chip_class
;
501 struct r600_ring gfx
;
502 struct r600_ring dma
;
503 struct pipe_fence_handle
*last_gfx_fence
;
504 struct pipe_fence_handle
*last_sdma_fence
;
505 struct r600_resource
*eop_bug_scratch
;
506 unsigned num_gfx_cs_flushes
;
507 unsigned initial_gfx_cs_size
;
508 unsigned gpu_reset_counter
;
509 unsigned last_dirty_tex_counter
;
510 unsigned last_compressed_colortex_counter
;
511 unsigned last_num_draw_calls
;
513 struct threaded_context
*tc
;
514 struct u_suballocator
*allocator_zeroed_memory
;
515 struct slab_child_pool pool_transfers
;
516 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
518 /* Current unaccounted memory usage. */
522 /* Additional context states. */
523 unsigned flags
; /* flush flags */
526 /* Maintain the list of active queries for pausing between IBs. */
527 int num_occlusion_queries
;
528 int num_perfect_occlusion_queries
;
529 struct list_head active_queries
;
530 unsigned num_cs_dw_queries_suspend
;
532 unsigned num_draw_calls
;
533 unsigned num_decompress_calls
;
534 unsigned num_mrt_draw_calls
;
535 unsigned num_prim_restart_calls
;
536 unsigned num_spill_draw_calls
;
537 unsigned num_compute_calls
;
538 unsigned num_spill_compute_calls
;
539 unsigned num_dma_calls
;
540 unsigned num_cp_dma_calls
;
541 unsigned num_vs_flushes
;
542 unsigned num_ps_flushes
;
543 unsigned num_cs_flushes
;
544 unsigned num_cb_cache_flushes
;
545 unsigned num_db_cache_flushes
;
546 unsigned num_L2_invalidates
;
547 unsigned num_L2_writebacks
;
548 unsigned num_resident_handles
;
549 uint64_t num_alloc_tex_transfer_bytes
;
550 unsigned last_tex_ps_draw_ratio
; /* for query */
552 /* Render condition. */
553 struct r600_atom render_cond_atom
;
554 struct pipe_query
*render_cond
;
555 unsigned render_cond_mode
;
556 bool render_cond_invert
;
557 bool render_cond_force_off
; /* for u_blitter */
559 /* Statistics gathering for the DCC enablement heuristic. It can't be
560 * in r600_texture because r600_texture can be shared by multiple
561 * contexts. This is for back buffers only. We shouldn't get too many
564 * X11 DRI3 rotates among a finite set of back buffers. They should
565 * all fit in this array. If they don't, separate DCC might never be
566 * enabled by DCC stat gathering.
569 struct r600_texture
*tex
;
570 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
571 struct pipe_query
*ps_stats
[3];
572 /* If all slots are used and another slot is needed,
573 * the least recently used slot is evicted based on this. */
574 int64_t last_use_timestamp
;
578 struct pipe_device_reset_callback device_reset_callback
;
579 struct u_log_context
*log
;
581 void *query_result_shader
;
583 /* Copy one resource to another using async DMA. */
584 void (*dma_copy
)(struct pipe_context
*ctx
,
585 struct pipe_resource
*dst
,
587 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
588 struct pipe_resource
*src
,
590 const struct pipe_box
*src_box
);
592 void (*dma_clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
593 uint64_t offset
, uint64_t size
, unsigned value
);
595 void (*clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
596 uint64_t offset
, uint64_t size
, unsigned value
,
597 enum r600_coherency coher
);
599 void (*blit_decompress_depth
)(struct pipe_context
*ctx
,
600 struct r600_texture
*texture
,
601 struct r600_texture
*staging
,
602 unsigned first_level
, unsigned last_level
,
603 unsigned first_layer
, unsigned last_layer
,
604 unsigned first_sample
, unsigned last_sample
);
606 void (*decompress_dcc
)(struct pipe_context
*ctx
,
607 struct r600_texture
*rtex
);
609 /* Reallocate the buffer and update all resource bindings where
610 * the buffer is bound, including all resource descriptors. */
611 void (*invalidate_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
);
613 /* Update all resource bindings where the buffer is bound, including
614 * all resource descriptors. This is invalidate_buffer without
615 * the invalidation. */
616 void (*rebind_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
617 uint64_t old_gpu_address
);
619 /* Enable or disable occlusion queries. */
620 void (*set_occlusion_query_state
)(struct pipe_context
*ctx
,
622 bool old_perfect_enable
);
624 void (*save_qbo_state
)(struct pipe_context
*ctx
, struct r600_qbo_state
*st
);
626 /* This ensures there is enough space in the command stream. */
627 void (*need_gfx_cs_space
)(struct pipe_context
*ctx
, unsigned num_dw
,
628 bool include_draw_vbo
);
630 void (*set_atom_dirty
)(struct r600_common_context
*ctx
,
631 struct r600_atom
*atom
, bool dirty
);
633 void (*check_vm_faults
)(struct r600_common_context
*ctx
,
634 struct radeon_saved_cs
*saved
,
635 enum ring_type ring
);
638 /* r600_buffer_common.c */
639 bool si_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
640 struct pb_buffer
*buf
,
641 enum radeon_bo_usage usage
);
642 void *si_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
643 struct r600_resource
*resource
,
645 void si_buffer_subdata(struct pipe_context
*ctx
,
646 struct pipe_resource
*buffer
,
647 unsigned usage
, unsigned offset
,
648 unsigned size
, const void *data
);
649 void si_init_resource_fields(struct r600_common_screen
*rscreen
,
650 struct r600_resource
*res
,
651 uint64_t size
, unsigned alignment
);
652 bool si_alloc_resource(struct r600_common_screen
*rscreen
,
653 struct r600_resource
*res
);
654 struct pipe_resource
*si_buffer_create(struct pipe_screen
*screen
,
655 const struct pipe_resource
*templ
,
657 struct pipe_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
662 struct pipe_resource
*
663 si_buffer_from_user_memory(struct pipe_screen
*screen
,
664 const struct pipe_resource
*templ
,
666 void si_invalidate_resource(struct pipe_context
*ctx
,
667 struct pipe_resource
*resource
);
668 void si_replace_buffer_storage(struct pipe_context
*ctx
,
669 struct pipe_resource
*dst
,
670 struct pipe_resource
*src
);
672 /* r600_common_pipe.c */
673 void si_gfx_write_event_eop(struct r600_common_context
*ctx
,
674 unsigned event
, unsigned event_flags
,
676 struct r600_resource
*buf
, uint64_t va
,
677 uint32_t new_fence
, unsigned query_type
);
678 unsigned si_gfx_write_fence_dwords(struct r600_common_screen
*screen
);
679 void si_gfx_wait_fence(struct r600_common_context
*ctx
,
680 uint64_t va
, uint32_t ref
, uint32_t mask
);
681 bool si_common_screen_init(struct r600_common_screen
*rscreen
,
682 struct radeon_winsys
*ws
);
683 void si_destroy_common_screen(struct r600_common_screen
*rscreen
);
684 void si_preflush_suspend_features(struct r600_common_context
*ctx
);
685 void si_postflush_resume_features(struct r600_common_context
*ctx
);
686 bool si_common_context_init(struct r600_common_context
*rctx
,
687 struct r600_common_screen
*rscreen
,
688 unsigned context_flags
);
689 void si_common_context_cleanup(struct r600_common_context
*rctx
);
690 bool si_can_dump_shader(struct r600_common_screen
*rscreen
,
692 bool si_extra_shader_checks(struct r600_common_screen
*rscreen
,
694 void si_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
695 uint64_t offset
, uint64_t size
, unsigned value
);
696 struct pipe_resource
*si_resource_create_common(struct pipe_screen
*screen
,
697 const struct pipe_resource
*templ
);
698 void si_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
,
699 struct r600_resource
*dst
, struct r600_resource
*src
);
700 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_winsys_cs
*cs
,
701 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
702 void si_clear_saved_cs(struct radeon_saved_cs
*saved
);
703 bool si_check_device_reset(struct r600_common_context
*rctx
);
705 /* r600_gpu_load.c */
706 void si_gpu_load_kill_thread(struct r600_common_screen
*rscreen
);
707 uint64_t si_begin_counter(struct r600_common_screen
*rscreen
, unsigned type
);
708 unsigned si_end_counter(struct r600_common_screen
*rscreen
, unsigned type
,
711 /* r600_perfcounters.c */
712 void si_perfcounters_destroy(struct r600_common_screen
*rscreen
);
715 void si_init_screen_query_functions(struct r600_common_screen
*rscreen
);
716 void si_init_query_functions(struct r600_common_context
*rctx
);
717 void si_suspend_queries(struct r600_common_context
*ctx
);
718 void si_resume_queries(struct r600_common_context
*ctx
);
720 /* r600_test_dma.c */
721 void si_test_dma(struct r600_common_screen
*rscreen
);
724 bool si_prepare_for_dma_blit(struct r600_common_context
*rctx
,
725 struct r600_texture
*rdst
,
726 unsigned dst_level
, unsigned dstx
,
727 unsigned dsty
, unsigned dstz
,
728 struct r600_texture
*rsrc
,
730 const struct pipe_box
*src_box
);
731 void si_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
732 struct r600_texture
*rtex
,
734 struct r600_fmask_info
*out
);
735 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
736 struct pipe_resource
*texture
,
737 struct r600_texture
**staging
);
738 void si_print_texture_info(struct r600_common_screen
*rscreen
,
739 struct r600_texture
*rtex
, struct u_log_context
*log
);
740 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
741 const struct pipe_resource
*templ
);
742 bool vi_dcc_formats_compatible(enum pipe_format format1
,
743 enum pipe_format format2
);
744 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
746 enum pipe_format view_format
);
747 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
748 struct pipe_resource
*tex
,
750 enum pipe_format view_format
);
751 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
752 struct pipe_resource
*texture
,
753 const struct pipe_surface
*templ
,
754 unsigned width0
, unsigned height0
,
755 unsigned width
, unsigned height
);
756 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
757 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
758 struct r600_texture
*tex
);
759 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
760 struct r600_texture
*tex
);
761 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
762 struct r600_texture
*tex
);
763 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
764 struct r600_texture
*rtex
,
765 unsigned level
, unsigned clear_value
);
766 void si_do_fast_color_clear(struct r600_common_context
*rctx
,
767 struct pipe_framebuffer_state
*fb
,
768 struct r600_atom
*fb_state
,
769 unsigned *buffers
, ubyte
*dirty_cbufs
,
770 const union pipe_color_union
*color
);
771 bool si_texture_disable_dcc(struct r600_common_context
*rctx
,
772 struct r600_texture
*rtex
);
773 void si_init_screen_texture_functions(struct r600_common_screen
*rscreen
);
774 void si_init_context_texture_functions(struct r600_common_context
*rctx
);
777 /* Inline helpers. */
779 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
781 return (struct r600_resource
*)r
;
785 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
787 pipe_resource_reference((struct pipe_resource
**)ptr
,
788 (struct pipe_resource
*)res
);
792 r600_texture_reference(struct r600_texture
**ptr
, struct r600_texture
*res
)
794 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->resource
.b
.b
);
798 r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
800 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
801 struct r600_resource
*res
= (struct r600_resource
*)r
;
804 /* Add memory usage for need_gfx_cs_space */
805 rctx
->vram
+= res
->vram_usage
;
806 rctx
->gtt
+= res
->gart_usage
;
810 #define SQ_TEX_XY_FILTER_POINT 0x00
811 #define SQ_TEX_XY_FILTER_BILINEAR 0x01
812 #define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
813 #define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03
815 static inline unsigned eg_tex_filter(unsigned filter
, unsigned max_aniso
)
817 if (filter
== PIPE_TEX_FILTER_LINEAR
)
818 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
819 : SQ_TEX_XY_FILTER_BILINEAR
;
821 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
822 : SQ_TEX_XY_FILTER_POINT
;
825 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
838 static inline enum radeon_bo_priority
839 r600_get_sampler_view_priority(struct r600_resource
*res
)
841 if (res
->b
.b
.target
== PIPE_BUFFER
)
842 return RADEON_PRIO_SAMPLER_BUFFER
;
844 if (res
->b
.b
.nr_samples
> 1)
845 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
847 return RADEON_PRIO_SAMPLER_TEXTURE
;
851 r600_can_sample_zs(struct r600_texture
*tex
, bool stencil_sampler
)
853 return (stencil_sampler
&& tex
->can_sample_s
) ||
854 (!stencil_sampler
&& tex
->can_sample_z
);
858 vi_dcc_enabled(struct r600_texture
*tex
, unsigned level
)
860 return tex
->dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
864 r600_htile_enabled(struct r600_texture
*tex
, unsigned level
)
866 return tex
->htile_offset
&& level
== 0;
870 vi_tc_compat_htile_enabled(struct r600_texture
*tex
, unsigned level
)
872 assert(!tex
->tc_compatible_htile
|| tex
->htile_offset
);
873 return tex
->tc_compatible_htile
&& level
== 0;
876 #define COMPUTE_DBG(rscreen, fmt, args...) \
878 if ((rscreen->b.debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
881 #define R600_ERR(fmt, args...) \
882 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
884 static inline int S_FIXED(float value
, unsigned frac_bits
)
886 return value
* (1 << frac_bits
);