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[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.h
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 /**
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
30 */
31
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
34
35 #include <stdio.h>
36
37 #include "amd/common/ac_binary.h"
38
39 #include "radeon/radeon_winsys.h"
40
41 #include "util/disk_cache.h"
42 #include "util/u_blitter.h"
43 #include "util/list.h"
44 #include "util/u_range.h"
45 #include "util/slab.h"
46 #include "util/u_suballoc.h"
47 #include "util/u_transfer.h"
48 #include "util/u_threaded_context.h"
49
50 struct u_log_context;
51
52 #define ATI_VENDOR_ID 0x1002
53
54 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
55 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
56 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
57 #define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
58 #define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
59
60 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
61 /* Pipeline & streamout query controls. */
62 #define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
63 #define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
64 #define R600_CONTEXT_PRIVATE_FLAG (1u << 3)
65
66 /* special primitive types */
67 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
68
69 /* Debug flags. */
70 /* logging and features */
71 #define DBG_TEX (1 << 0)
72 #define DBG_NIR (1 << 1)
73 #define DBG_COMPUTE (1 << 2)
74 #define DBG_VM (1 << 3)
75 #define DBG_CE (1 << 4)
76 /* shader logging */
77 #define DBG_FS (1 << 5)
78 #define DBG_VS (1 << 6)
79 #define DBG_GS (1 << 7)
80 #define DBG_PS (1 << 8)
81 #define DBG_CS (1 << 9)
82 #define DBG_TCS (1 << 10)
83 #define DBG_TES (1 << 11)
84 #define DBG_NO_IR (1 << 12)
85 #define DBG_NO_TGSI (1 << 13)
86 #define DBG_NO_ASM (1 << 14)
87 #define DBG_PREOPT_IR (1 << 15)
88 #define DBG_CHECK_IR (1 << 16)
89 #define DBG_NO_OPT_VARIANT (1 << 17)
90 #define DBG_FS_CORRECT_DERIVS_AFTER_KILL (1 << 18)
91 /* gaps */
92 #define DBG_TEST_DMA (1 << 20)
93 /* Bits 21-31 are reserved for the r600g driver. */
94 /* features */
95 #define DBG_NO_ASYNC_DMA (1ull << 32)
96 #define DBG_NO_HYPERZ (1ull << 33)
97 #define DBG_NO_DISCARD_RANGE (1ull << 34)
98 #define DBG_NO_2D_TILING (1ull << 35)
99 #define DBG_NO_TILING (1ull << 36)
100 #define DBG_SWITCH_ON_EOP (1ull << 37)
101 #define DBG_FORCE_DMA (1ull << 38)
102 #define DBG_PRECOMPILE (1ull << 39)
103 #define DBG_INFO (1ull << 40)
104 #define DBG_NO_WC (1ull << 41)
105 #define DBG_CHECK_VM (1ull << 42)
106 #define DBG_NO_DCC (1ull << 43)
107 #define DBG_NO_DCC_CLEAR (1ull << 44)
108 #define DBG_NO_RB_PLUS (1ull << 45)
109 #define DBG_SI_SCHED (1ull << 46)
110 #define DBG_MONOLITHIC_SHADERS (1ull << 47)
111 #define DBG_NO_CE (1ull << 48)
112 #define DBG_UNSAFE_MATH (1ull << 49)
113 #define DBG_NO_DCC_FB (1ull << 50)
114 #define DBG_TEST_VMFAULT_CP (1ull << 51)
115 #define DBG_TEST_VMFAULT_SDMA (1ull << 52)
116 #define DBG_TEST_VMFAULT_SHADER (1ull << 53)
117
118 #define R600_MAP_BUFFER_ALIGNMENT 64
119 #define R600_MAX_VIEWPORTS 16
120
121 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
122
123 enum r600_coherency {
124 R600_COHERENCY_NONE, /* no cache flushes needed */
125 R600_COHERENCY_SHADER,
126 R600_COHERENCY_CB_META,
127 };
128
129 #ifdef PIPE_ARCH_BIG_ENDIAN
130 #define R600_BIG_ENDIAN 1
131 #else
132 #define R600_BIG_ENDIAN 0
133 #endif
134
135 struct r600_common_context;
136 struct r600_perfcounters;
137 struct tgsi_shader_info;
138 struct r600_qbo_state;
139
140 void radeon_shader_binary_init(struct ac_shader_binary *b);
141 void radeon_shader_binary_clean(struct ac_shader_binary *b);
142
143 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
144 * at the moment.
145 */
146 struct r600_resource {
147 struct threaded_resource b;
148
149 /* Winsys objects. */
150 struct pb_buffer *buf;
151 uint64_t gpu_address;
152 /* Memory usage if the buffer placement is optimal. */
153 uint64_t vram_usage;
154 uint64_t gart_usage;
155
156 /* Resource properties. */
157 uint64_t bo_size;
158 unsigned bo_alignment;
159 enum radeon_bo_domain domains;
160 enum radeon_bo_flag flags;
161 unsigned bind_history;
162
163 /* The buffer range which is initialized (with a write transfer,
164 * streamout, DMA, or as a random access target). The rest of
165 * the buffer is considered invalid and can be mapped unsynchronized.
166 *
167 * This allows unsychronized mapping of a buffer range which hasn't
168 * been used yet. It's for applications which forget to use
169 * the unsynchronized map flag and expect the driver to figure it out.
170 */
171 struct util_range valid_buffer_range;
172
173 /* For buffers only. This indicates that a write operation has been
174 * performed by TC L2, but the cache hasn't been flushed.
175 * Any hw block which doesn't use or bypasses TC L2 should check this
176 * flag and flush the cache before using the buffer.
177 *
178 * For example, TC L2 must be flushed if a buffer which has been
179 * modified by a shader store instruction is about to be used as
180 * an index buffer. The reason is that VGT DMA index fetching doesn't
181 * use TC L2.
182 */
183 bool TC_L2_dirty;
184
185 /* Whether the resource has been exported via resource_get_handle. */
186 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
187
188 /* Whether this resource is referenced by bindless handles. */
189 bool texture_handle_allocated;
190 bool image_handle_allocated;
191 };
192
193 struct r600_transfer {
194 struct threaded_transfer b;
195 struct r600_resource *staging;
196 unsigned offset;
197 };
198
199 struct r600_fmask_info {
200 uint64_t offset;
201 uint64_t size;
202 unsigned alignment;
203 unsigned pitch_in_pixels;
204 unsigned bank_height;
205 unsigned slice_tile_max;
206 unsigned tile_mode_index;
207 unsigned tile_swizzle;
208 };
209
210 struct r600_cmask_info {
211 uint64_t offset;
212 uint64_t size;
213 unsigned alignment;
214 unsigned slice_tile_max;
215 uint64_t base_address_reg;
216 };
217
218 struct r600_texture {
219 struct r600_resource resource;
220
221 uint64_t size;
222 unsigned num_level0_transfers;
223 enum pipe_format db_render_format;
224 bool is_depth;
225 bool db_compatible;
226 bool can_sample_z;
227 bool can_sample_s;
228 unsigned dirty_level_mask; /* each bit says if that mipmap is compressed */
229 unsigned stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
230 struct r600_texture *flushed_depth_texture;
231 struct radeon_surf surface;
232
233 /* Colorbuffer compression and fast clear. */
234 struct r600_fmask_info fmask;
235 struct r600_cmask_info cmask;
236 struct r600_resource *cmask_buffer;
237 uint64_t dcc_offset; /* 0 = disabled */
238 unsigned cb_color_info; /* fast clear enable bit */
239 unsigned color_clear_value[2];
240 unsigned last_msaa_resolve_target_micro_mode;
241
242 /* Depth buffer compression and fast clear. */
243 uint64_t htile_offset;
244 bool tc_compatible_htile;
245 bool depth_cleared; /* if it was cleared at least once */
246 float depth_clear_value;
247 bool stencil_cleared; /* if it was cleared at least once */
248 uint8_t stencil_clear_value;
249
250 bool non_disp_tiling; /* R600-Cayman only */
251
252 /* Whether the texture is a displayable back buffer and needs DCC
253 * decompression, which is expensive. Therefore, it's enabled only
254 * if statistics suggest that it will pay off and it's allocated
255 * separately. It can't be bound as a sampler by apps. Limited to
256 * target == 2D and last_level == 0. If enabled, dcc_offset contains
257 * the absolute GPUVM address, not the relative one.
258 */
259 struct r600_resource *dcc_separate_buffer;
260 /* When DCC is temporarily disabled, the separate buffer is here. */
261 struct r600_resource *last_dcc_separate_buffer;
262 /* We need to track DCC dirtiness, because st/dri usually calls
263 * flush_resource twice per frame (not a bug) and we don't wanna
264 * decompress DCC twice. Also, the dirty tracking must be done even
265 * if DCC isn't used, because it's required by the DCC usage analysis
266 * for a possible future enablement.
267 */
268 bool separate_dcc_dirty;
269 /* Statistics gathering for the DCC enablement heuristic. */
270 bool dcc_gather_statistics;
271 /* Estimate of how much this color buffer is written to in units of
272 * full-screen draws: ps_invocations / (width * height)
273 * Shader kills, late Z, and blending with trivial discards make it
274 * inaccurate (we need to count CB updates, not PS invocations).
275 */
276 unsigned ps_draw_ratio;
277 /* The number of clears since the last DCC usage analysis. */
278 unsigned num_slow_clears;
279
280 /* Counter that should be non-zero if the texture is bound to a
281 * framebuffer. Implemented in radeonsi only.
282 */
283 uint32_t framebuffers_bound;
284 };
285
286 struct r600_surface {
287 struct pipe_surface base;
288
289 /* These can vary with block-compressed textures. */
290 unsigned width0;
291 unsigned height0;
292
293 bool color_initialized;
294 bool depth_initialized;
295
296 /* Misc. color flags. */
297 bool alphatest_bypass;
298 bool export_16bpc;
299 bool color_is_int8;
300 bool color_is_int10;
301 bool dcc_incompatible;
302
303 /* Color registers. */
304 unsigned cb_color_info;
305 unsigned cb_color_base;
306 unsigned cb_color_view;
307 unsigned cb_color_size; /* R600 only */
308 unsigned cb_color_dim; /* EG only */
309 unsigned cb_color_pitch; /* EG and later */
310 unsigned cb_color_slice; /* EG and later */
311 unsigned cb_color_attrib; /* EG and later */
312 unsigned cb_color_attrib2; /* GFX9 and later */
313 unsigned cb_dcc_control; /* VI and later */
314 unsigned cb_color_fmask; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
315 unsigned cb_color_fmask_slice; /* EG and later */
316 unsigned cb_color_cmask; /* CB_COLORn_TILE (r600 only) */
317 unsigned cb_color_mask; /* R600 only */
318 unsigned spi_shader_col_format; /* SI+, no blending, no alpha-to-coverage. */
319 unsigned spi_shader_col_format_alpha; /* SI+, alpha-to-coverage */
320 unsigned spi_shader_col_format_blend; /* SI+, blending without alpha. */
321 unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
322 struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
323 struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
324
325 /* DB registers. */
326 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
327 uint64_t db_stencil_base; /* EG and later */
328 uint64_t db_htile_data_base;
329 unsigned db_depth_info; /* R600 only, then SI and later */
330 unsigned db_z_info; /* EG and later */
331 unsigned db_z_info2; /* GFX9+ */
332 unsigned db_depth_view;
333 unsigned db_depth_size;
334 unsigned db_depth_slice; /* EG and later */
335 unsigned db_stencil_info; /* EG and later */
336 unsigned db_stencil_info2; /* GFX9+ */
337 unsigned db_prefetch_limit; /* R600 only */
338 unsigned db_htile_surface;
339 unsigned db_preload_control; /* EG and later */
340 };
341
342 struct r600_mmio_counter {
343 unsigned busy;
344 unsigned idle;
345 };
346
347 union r600_mmio_counters {
348 struct {
349 /* For global GPU load including SDMA. */
350 struct r600_mmio_counter gpu;
351
352 /* GRBM_STATUS */
353 struct r600_mmio_counter spi;
354 struct r600_mmio_counter gui;
355 struct r600_mmio_counter ta;
356 struct r600_mmio_counter gds;
357 struct r600_mmio_counter vgt;
358 struct r600_mmio_counter ia;
359 struct r600_mmio_counter sx;
360 struct r600_mmio_counter wd;
361 struct r600_mmio_counter bci;
362 struct r600_mmio_counter sc;
363 struct r600_mmio_counter pa;
364 struct r600_mmio_counter db;
365 struct r600_mmio_counter cp;
366 struct r600_mmio_counter cb;
367
368 /* SRBM_STATUS2 */
369 struct r600_mmio_counter sdma;
370
371 /* CP_STAT */
372 struct r600_mmio_counter pfp;
373 struct r600_mmio_counter meq;
374 struct r600_mmio_counter me;
375 struct r600_mmio_counter surf_sync;
376 struct r600_mmio_counter cp_dma;
377 struct r600_mmio_counter scratch_ram;
378 struct r600_mmio_counter ce;
379 } named;
380 unsigned array[0];
381 };
382
383 struct r600_memory_object {
384 struct pipe_memory_object b;
385 struct pb_buffer *buf;
386 uint32_t stride;
387 uint32_t offset;
388 };
389
390 struct r600_common_screen {
391 struct pipe_screen b;
392 struct radeon_winsys *ws;
393 enum radeon_family family;
394 enum chip_class chip_class;
395 struct radeon_info info;
396 uint64_t debug_flags;
397 bool has_cp_dma;
398 bool has_streamout;
399 bool has_rbplus; /* if RB+ registers exist */
400 bool rbplus_allowed; /* if RB+ is allowed */
401
402 struct disk_cache *disk_shader_cache;
403
404 struct slab_parent_pool pool_transfers;
405
406 /* Texture filter settings. */
407 int force_aniso; /* -1 = disabled */
408
409 /* Auxiliary context. Mainly used to initialize resources.
410 * It must be locked prior to using and flushed before unlocking. */
411 struct pipe_context *aux_context;
412 mtx_t aux_context_lock;
413
414 /* This must be in the screen, because UE4 uses one context for
415 * compilation and another one for rendering.
416 */
417 unsigned num_compilations;
418 /* Along with ST_DEBUG=precompile, this should show if applications
419 * are loading shaders on demand. This is a monotonic counter.
420 */
421 unsigned num_shaders_created;
422 unsigned num_shader_cache_hits;
423
424 /* GPU load thread. */
425 mtx_t gpu_load_mutex;
426 thrd_t gpu_load_thread;
427 union r600_mmio_counters mmio_counters;
428 volatile unsigned gpu_load_stop_thread; /* bool */
429
430 char renderer_string[100];
431
432 /* Performance counters. */
433 struct r600_perfcounters *perfcounters;
434
435 /* If pipe_screen wants to recompute and re-emit the framebuffer,
436 * sampler, and image states of all contexts, it should atomically
437 * increment this.
438 *
439 * Each context will compare this with its own last known value of
440 * the counter before drawing and re-emit the states accordingly.
441 */
442 unsigned dirty_tex_counter;
443
444 /* Atomically increment this counter when an existing texture's
445 * metadata is enabled or disabled in a way that requires changing
446 * contexts' compressed texture binding masks.
447 */
448 unsigned compressed_colortex_counter;
449
450 struct {
451 /* Context flags to set so that all writes from earlier jobs
452 * in the CP are seen by L2 clients.
453 */
454 unsigned cp_to_L2;
455
456 /* Context flags to set so that all writes from earlier
457 * compute jobs are seen by L2 clients.
458 */
459 unsigned compute_to_L2;
460 } barrier_flags;
461
462 void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
463 struct r600_texture *rtex,
464 struct radeon_bo_metadata *md);
465
466 void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
467 struct r600_texture *rtex,
468 struct radeon_bo_metadata *md);
469 };
470
471 /* This encapsulates a state or an operation which can emitted into the GPU
472 * command stream. */
473 struct r600_atom {
474 void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
475 unsigned num_dw;
476 unsigned short id;
477 };
478
479 struct r600_so_target {
480 struct pipe_stream_output_target b;
481
482 /* The buffer where BUFFER_FILLED_SIZE is stored. */
483 struct r600_resource *buf_filled_size;
484 unsigned buf_filled_size_offset;
485 bool buf_filled_size_valid;
486
487 unsigned stride_in_dw;
488 };
489
490 struct r600_streamout {
491 struct r600_atom begin_atom;
492 bool begin_emitted;
493 unsigned num_dw_for_end;
494
495 unsigned enabled_mask;
496 unsigned num_targets;
497 struct r600_so_target *targets[PIPE_MAX_SO_BUFFERS];
498
499 unsigned append_bitmask;
500 bool suspended;
501
502 /* External state which comes from the vertex shader,
503 * it must be set explicitly when binding a shader. */
504 uint16_t *stride_in_dw;
505 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
506
507 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
508 unsigned hw_enabled_mask;
509
510 /* The state of VGT_STRMOUT_(CONFIG|EN). */
511 struct r600_atom enable_atom;
512 bool streamout_enabled;
513 bool prims_gen_query_enabled;
514 int num_prims_gen_queries;
515 };
516
517 struct r600_signed_scissor {
518 int minx;
519 int miny;
520 int maxx;
521 int maxy;
522 };
523
524 struct r600_scissors {
525 struct r600_atom atom;
526 unsigned dirty_mask;
527 struct pipe_scissor_state states[R600_MAX_VIEWPORTS];
528 };
529
530 struct r600_viewports {
531 struct r600_atom atom;
532 unsigned dirty_mask;
533 unsigned depth_range_dirty_mask;
534 struct pipe_viewport_state states[R600_MAX_VIEWPORTS];
535 struct r600_signed_scissor as_scissor[R600_MAX_VIEWPORTS];
536 };
537
538 struct r600_ring {
539 struct radeon_winsys_cs *cs;
540 void (*flush)(void *ctx, unsigned flags,
541 struct pipe_fence_handle **fence);
542 };
543
544 /* Saved CS data for debugging features. */
545 struct radeon_saved_cs {
546 uint32_t *ib;
547 unsigned num_dw;
548
549 struct radeon_bo_list_item *bo_list;
550 unsigned bo_count;
551 };
552
553 struct r600_common_context {
554 struct pipe_context b; /* base class */
555
556 struct r600_common_screen *screen;
557 struct radeon_winsys *ws;
558 struct radeon_winsys_ctx *ctx;
559 enum radeon_family family;
560 enum chip_class chip_class;
561 struct r600_ring gfx;
562 struct r600_ring dma;
563 struct pipe_fence_handle *last_gfx_fence;
564 struct pipe_fence_handle *last_sdma_fence;
565 struct r600_resource *eop_bug_scratch;
566 unsigned num_gfx_cs_flushes;
567 unsigned initial_gfx_cs_size;
568 unsigned gpu_reset_counter;
569 unsigned last_dirty_tex_counter;
570 unsigned last_compressed_colortex_counter;
571
572 struct threaded_context *tc;
573 struct u_suballocator *allocator_zeroed_memory;
574 struct slab_child_pool pool_transfers;
575 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
576
577 /* Current unaccounted memory usage. */
578 uint64_t vram;
579 uint64_t gtt;
580
581 /* States. */
582 struct r600_streamout streamout;
583 struct r600_scissors scissors;
584 struct r600_viewports viewports;
585 bool scissor_enabled;
586 bool clip_halfz;
587 bool vs_writes_viewport_index;
588 bool vs_disables_clipping_viewport;
589
590 /* Additional context states. */
591 unsigned flags; /* flush flags */
592
593 /* Queries. */
594 /* Maintain the list of active queries for pausing between IBs. */
595 int num_occlusion_queries;
596 int num_perfect_occlusion_queries;
597 struct list_head active_queries;
598 unsigned num_cs_dw_queries_suspend;
599 /* Misc stats. */
600 unsigned num_draw_calls;
601 unsigned num_decompress_calls;
602 unsigned num_mrt_draw_calls;
603 unsigned num_prim_restart_calls;
604 unsigned num_spill_draw_calls;
605 unsigned num_compute_calls;
606 unsigned num_spill_compute_calls;
607 unsigned num_dma_calls;
608 unsigned num_cp_dma_calls;
609 unsigned num_vs_flushes;
610 unsigned num_ps_flushes;
611 unsigned num_cs_flushes;
612 unsigned num_cb_cache_flushes;
613 unsigned num_db_cache_flushes;
614 unsigned num_L2_invalidates;
615 unsigned num_L2_writebacks;
616 unsigned num_resident_handles;
617 uint64_t num_alloc_tex_transfer_bytes;
618 unsigned last_tex_ps_draw_ratio; /* for query */
619
620 /* Render condition. */
621 struct r600_atom render_cond_atom;
622 struct pipe_query *render_cond;
623 unsigned render_cond_mode;
624 bool render_cond_invert;
625 bool render_cond_force_off; /* for u_blitter */
626
627 /* MSAA sample locations.
628 * The first index is the sample index.
629 * The second index is the coordinate: X, Y. */
630 float sample_locations_1x[1][2];
631 float sample_locations_2x[2][2];
632 float sample_locations_4x[4][2];
633 float sample_locations_8x[8][2];
634 float sample_locations_16x[16][2];
635
636 /* Statistics gathering for the DCC enablement heuristic. It can't be
637 * in r600_texture because r600_texture can be shared by multiple
638 * contexts. This is for back buffers only. We shouldn't get too many
639 * of those.
640 *
641 * X11 DRI3 rotates among a finite set of back buffers. They should
642 * all fit in this array. If they don't, separate DCC might never be
643 * enabled by DCC stat gathering.
644 */
645 struct {
646 struct r600_texture *tex;
647 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
648 struct pipe_query *ps_stats[3];
649 /* If all slots are used and another slot is needed,
650 * the least recently used slot is evicted based on this. */
651 int64_t last_use_timestamp;
652 bool query_active;
653 } dcc_stats[5];
654
655 struct pipe_debug_callback debug;
656 struct pipe_device_reset_callback device_reset_callback;
657 struct u_log_context *log;
658
659 void *query_result_shader;
660
661 /* Copy one resource to another using async DMA. */
662 void (*dma_copy)(struct pipe_context *ctx,
663 struct pipe_resource *dst,
664 unsigned dst_level,
665 unsigned dst_x, unsigned dst_y, unsigned dst_z,
666 struct pipe_resource *src,
667 unsigned src_level,
668 const struct pipe_box *src_box);
669
670 void (*dma_clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
671 uint64_t offset, uint64_t size, unsigned value);
672
673 void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
674 uint64_t offset, uint64_t size, unsigned value,
675 enum r600_coherency coher);
676
677 void (*blit_decompress_depth)(struct pipe_context *ctx,
678 struct r600_texture *texture,
679 struct r600_texture *staging,
680 unsigned first_level, unsigned last_level,
681 unsigned first_layer, unsigned last_layer,
682 unsigned first_sample, unsigned last_sample);
683
684 void (*decompress_dcc)(struct pipe_context *ctx,
685 struct r600_texture *rtex);
686
687 /* Reallocate the buffer and update all resource bindings where
688 * the buffer is bound, including all resource descriptors. */
689 void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
690
691 /* Update all resource bindings where the buffer is bound, including
692 * all resource descriptors. This is invalidate_buffer without
693 * the invalidation. */
694 void (*rebind_buffer)(struct pipe_context *ctx, struct pipe_resource *buf,
695 uint64_t old_gpu_address);
696
697 /* Enable or disable occlusion queries. */
698 void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
699
700 void (*save_qbo_state)(struct pipe_context *ctx, struct r600_qbo_state *st);
701
702 /* This ensures there is enough space in the command stream. */
703 void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
704 bool include_draw_vbo);
705
706 void (*set_atom_dirty)(struct r600_common_context *ctx,
707 struct r600_atom *atom, bool dirty);
708
709 void (*check_vm_faults)(struct r600_common_context *ctx,
710 struct radeon_saved_cs *saved,
711 enum ring_type ring);
712 };
713
714 /* r600_buffer_common.c */
715 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
716 struct pb_buffer *buf,
717 enum radeon_bo_usage usage);
718 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
719 struct r600_resource *resource,
720 unsigned usage);
721 void r600_buffer_subdata(struct pipe_context *ctx,
722 struct pipe_resource *buffer,
723 unsigned usage, unsigned offset,
724 unsigned size, const void *data);
725 void r600_init_resource_fields(struct r600_common_screen *rscreen,
726 struct r600_resource *res,
727 uint64_t size, unsigned alignment);
728 bool r600_alloc_resource(struct r600_common_screen *rscreen,
729 struct r600_resource *res);
730 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
731 const struct pipe_resource *templ,
732 unsigned alignment);
733 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
734 unsigned flags,
735 unsigned usage,
736 unsigned size,
737 unsigned alignment);
738 struct pipe_resource *
739 r600_buffer_from_user_memory(struct pipe_screen *screen,
740 const struct pipe_resource *templ,
741 void *user_memory);
742 void
743 r600_invalidate_resource(struct pipe_context *ctx,
744 struct pipe_resource *resource);
745 void r600_replace_buffer_storage(struct pipe_context *ctx,
746 struct pipe_resource *dst,
747 struct pipe_resource *src);
748
749 /* r600_common_pipe.c */
750 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
751 unsigned event, unsigned event_flags,
752 unsigned data_sel,
753 struct r600_resource *buf, uint64_t va,
754 uint32_t new_fence, unsigned query_type);
755 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen);
756 void r600_gfx_wait_fence(struct r600_common_context *ctx,
757 uint64_t va, uint32_t ref, uint32_t mask);
758 void r600_draw_rectangle(struct blitter_context *blitter,
759 int x1, int y1, int x2, int y2, float depth,
760 enum blitter_attrib_type type,
761 const union pipe_color_union *attrib);
762 bool r600_common_screen_init(struct r600_common_screen *rscreen,
763 struct radeon_winsys *ws);
764 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
765 void r600_preflush_suspend_features(struct r600_common_context *ctx);
766 void r600_postflush_resume_features(struct r600_common_context *ctx);
767 bool r600_common_context_init(struct r600_common_context *rctx,
768 struct r600_common_screen *rscreen,
769 unsigned context_flags);
770 void r600_common_context_cleanup(struct r600_common_context *rctx);
771 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
772 unsigned processor);
773 bool r600_extra_shader_checks(struct r600_common_screen *rscreen,
774 unsigned processor);
775 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
776 uint64_t offset, uint64_t size, unsigned value);
777 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
778 const struct pipe_resource *templ);
779 const char *r600_get_llvm_processor_name(enum radeon_family family);
780 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
781 struct r600_resource *dst, struct r600_resource *src);
782 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
783 struct radeon_saved_cs *saved, bool get_buffer_list);
784 void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
785 bool r600_check_device_reset(struct r600_common_context *rctx);
786
787 /* r600_gpu_load.c */
788 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
789 uint64_t r600_begin_counter(struct r600_common_screen *rscreen, unsigned type);
790 unsigned r600_end_counter(struct r600_common_screen *rscreen, unsigned type,
791 uint64_t begin);
792
793 /* r600_perfcounters.c */
794 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
795
796 /* r600_query.c */
797 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
798 void r600_query_init(struct r600_common_context *rctx);
799 void r600_suspend_queries(struct r600_common_context *ctx);
800 void r600_resume_queries(struct r600_common_context *ctx);
801 void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen);
802
803 /* r600_streamout.c */
804 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
805 void r600_set_streamout_targets(struct pipe_context *ctx,
806 unsigned num_targets,
807 struct pipe_stream_output_target **targets,
808 const unsigned *offset);
809 void r600_emit_streamout_end(struct r600_common_context *rctx);
810 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
811 unsigned type, int diff);
812 void r600_streamout_init(struct r600_common_context *rctx);
813
814 /* r600_test_dma.c */
815 void r600_test_dma(struct r600_common_screen *rscreen);
816
817 /* r600_texture.c */
818 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
819 struct r600_texture *rdst,
820 unsigned dst_level, unsigned dstx,
821 unsigned dsty, unsigned dstz,
822 struct r600_texture *rsrc,
823 unsigned src_level,
824 const struct pipe_box *src_box);
825 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
826 struct r600_texture *rtex,
827 unsigned nr_samples,
828 struct r600_fmask_info *out);
829 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
830 struct r600_texture *rtex,
831 struct r600_cmask_info *out);
832 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
833 struct pipe_resource *texture,
834 struct r600_texture **staging);
835 void r600_print_texture_info(struct r600_common_screen *rscreen,
836 struct r600_texture *rtex, FILE *f);
837 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
838 const struct pipe_resource *templ);
839 bool vi_dcc_formats_compatible(enum pipe_format format1,
840 enum pipe_format format2);
841 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
842 unsigned level,
843 enum pipe_format view_format);
844 void vi_disable_dcc_if_incompatible_format(struct r600_common_context *rctx,
845 struct pipe_resource *tex,
846 unsigned level,
847 enum pipe_format view_format);
848 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
849 struct pipe_resource *texture,
850 const struct pipe_surface *templ,
851 unsigned width0, unsigned height0,
852 unsigned width, unsigned height);
853 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
854 void vi_separate_dcc_start_query(struct pipe_context *ctx,
855 struct r600_texture *tex);
856 void vi_separate_dcc_stop_query(struct pipe_context *ctx,
857 struct r600_texture *tex);
858 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
859 struct r600_texture *tex);
860 void vi_dcc_clear_level(struct r600_common_context *rctx,
861 struct r600_texture *rtex,
862 unsigned level, unsigned clear_value);
863 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
864 struct pipe_framebuffer_state *fb,
865 struct r600_atom *fb_state,
866 unsigned *buffers, ubyte *dirty_cbufs,
867 const union pipe_color_union *color);
868 bool r600_texture_disable_dcc(struct r600_common_context *rctx,
869 struct r600_texture *rtex);
870 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
871 void r600_init_context_texture_functions(struct r600_common_context *rctx);
872
873 /* r600_viewport.c */
874 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
875 struct pipe_scissor_state *scissor);
876 void r600_viewport_set_rast_deps(struct r600_common_context *rctx,
877 bool scissor_enable, bool clip_halfz);
878 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
879 struct tgsi_shader_info *info);
880 void r600_init_viewport_functions(struct r600_common_context *rctx);
881
882 /* cayman_msaa.c */
883 extern const uint32_t eg_sample_locs_2x[4];
884 extern const unsigned eg_max_dist_2x;
885 extern const uint32_t eg_sample_locs_4x[4];
886 extern const unsigned eg_max_dist_4x;
887 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
888 unsigned sample_index, float *out_value);
889 void cayman_init_msaa(struct pipe_context *ctx);
890 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
891 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
892 int ps_iter_samples, int overrast_samples,
893 unsigned sc_mode_cntl_1);
894
895
896 /* Inline helpers. */
897
898 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
899 {
900 return (struct r600_resource*)r;
901 }
902
903 static inline void
904 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
905 {
906 pipe_resource_reference((struct pipe_resource **)ptr,
907 (struct pipe_resource *)res);
908 }
909
910 static inline void
911 r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
912 {
913 pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
914 }
915
916 static inline void
917 r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
918 {
919 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
920 struct r600_resource *res = (struct r600_resource *)r;
921
922 if (res) {
923 /* Add memory usage for need_gfx_cs_space */
924 rctx->vram += res->vram_usage;
925 rctx->gtt += res->gart_usage;
926 }
927 }
928
929 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
930 {
931 return rctx->streamout.streamout_enabled ||
932 rctx->streamout.prims_gen_query_enabled;
933 }
934
935 #define SQ_TEX_XY_FILTER_POINT 0x00
936 #define SQ_TEX_XY_FILTER_BILINEAR 0x01
937 #define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
938 #define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03
939
940 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
941 {
942 if (filter == PIPE_TEX_FILTER_LINEAR)
943 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
944 : SQ_TEX_XY_FILTER_BILINEAR;
945 else
946 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
947 : SQ_TEX_XY_FILTER_POINT;
948 }
949
950 static inline unsigned r600_tex_aniso_filter(unsigned filter)
951 {
952 if (filter < 2)
953 return 0;
954 if (filter < 4)
955 return 1;
956 if (filter < 8)
957 return 2;
958 if (filter < 16)
959 return 3;
960 return 4;
961 }
962
963 static inline unsigned r600_wavefront_size(enum radeon_family family)
964 {
965 switch (family) {
966 case CHIP_RV610:
967 case CHIP_RS780:
968 case CHIP_RV620:
969 case CHIP_RS880:
970 return 16;
971 case CHIP_RV630:
972 case CHIP_RV635:
973 case CHIP_RV730:
974 case CHIP_RV710:
975 case CHIP_PALM:
976 case CHIP_CEDAR:
977 return 32;
978 default:
979 return 64;
980 }
981 }
982
983 static inline enum radeon_bo_priority
984 r600_get_sampler_view_priority(struct r600_resource *res)
985 {
986 if (res->b.b.target == PIPE_BUFFER)
987 return RADEON_PRIO_SAMPLER_BUFFER;
988
989 if (res->b.b.nr_samples > 1)
990 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
991
992 return RADEON_PRIO_SAMPLER_TEXTURE;
993 }
994
995 static inline bool
996 r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
997 {
998 return (stencil_sampler && tex->can_sample_s) ||
999 (!stencil_sampler && tex->can_sample_z);
1000 }
1001
1002 static inline bool
1003 vi_dcc_enabled(struct r600_texture *tex, unsigned level)
1004 {
1005 return tex->dcc_offset && level < tex->surface.num_dcc_levels;
1006 }
1007
1008 #define COMPUTE_DBG(rscreen, fmt, args...) \
1009 do { \
1010 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
1011 } while (0);
1012
1013 #define R600_ERR(fmt, args...) \
1014 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1015
1016 /* For MSAA sample positions. */
1017 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1018 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1019 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1020 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1021 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1022
1023 static inline int S_FIXED(float value, unsigned frac_bits)
1024 {
1025 return value * (1 << frac_bits);
1026 }
1027
1028 #endif