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[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.h
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 /**
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
30 */
31
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
34
35 #include <stdio.h>
36
37 #include "radeon/radeon_winsys.h"
38
39 #include "util/u_blitter.h"
40 #include "util/list.h"
41 #include "util/u_range.h"
42 #include "util/u_slab.h"
43 #include "util/u_suballoc.h"
44 #include "util/u_transfer.h"
45
46 #define ATI_VENDOR_ID 0x1002
47
48 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
49 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
50 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
51 #define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
52
53 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
54 /* Pipeline & streamout query controls. */
55 #define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
56 #define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
57 #define R600_CONTEXT_PRIVATE_FLAG (1u << 3)
58
59 /* special primitive types */
60 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
61
62 /* Debug flags. */
63 /* logging */
64 #define DBG_TEX (1 << 0)
65 /* gap - reuse */
66 #define DBG_COMPUTE (1 << 2)
67 #define DBG_VM (1 << 3)
68 /* gap - reuse */
69 /* shader logging */
70 #define DBG_FS (1 << 5)
71 #define DBG_VS (1 << 6)
72 #define DBG_GS (1 << 7)
73 #define DBG_PS (1 << 8)
74 #define DBG_CS (1 << 9)
75 #define DBG_TCS (1 << 10)
76 #define DBG_TES (1 << 11)
77 #define DBG_NO_IR (1 << 12)
78 #define DBG_NO_TGSI (1 << 13)
79 #define DBG_NO_ASM (1 << 14)
80 #define DBG_PREOPT_IR (1 << 15)
81 /* gaps */
82 #define DBG_TEST_DMA (1 << 20)
83 /* Bits 21-31 are reserved for the r600g driver. */
84 /* features */
85 #define DBG_NO_ASYNC_DMA (1llu << 32)
86 #define DBG_NO_HYPERZ (1llu << 33)
87 #define DBG_NO_DISCARD_RANGE (1llu << 34)
88 #define DBG_NO_2D_TILING (1llu << 35)
89 #define DBG_NO_TILING (1llu << 36)
90 #define DBG_SWITCH_ON_EOP (1llu << 37)
91 #define DBG_FORCE_DMA (1llu << 38)
92 #define DBG_PRECOMPILE (1llu << 39)
93 #define DBG_INFO (1llu << 40)
94 #define DBG_NO_WC (1llu << 41)
95 #define DBG_CHECK_VM (1llu << 42)
96 #define DBG_NO_DCC (1llu << 43)
97 #define DBG_NO_DCC_CLEAR (1llu << 44)
98 #define DBG_NO_RB_PLUS (1llu << 45)
99 #define DBG_SI_SCHED (1llu << 46)
100 #define DBG_MONOLITHIC_SHADERS (1llu << 47)
101 #define DBG_NO_CE (1llu << 48)
102 #define DBG_UNSAFE_MATH (1llu << 49)
103
104 #define R600_MAP_BUFFER_ALIGNMENT 64
105 #define R600_MAX_VIEWPORTS 16
106
107 enum r600_coherency {
108 R600_COHERENCY_NONE, /* no cache flushes needed */
109 R600_COHERENCY_SHADER,
110 R600_COHERENCY_CB_META,
111 };
112
113 #ifdef PIPE_ARCH_BIG_ENDIAN
114 #define R600_BIG_ENDIAN 1
115 #else
116 #define R600_BIG_ENDIAN 0
117 #endif
118
119 struct r600_common_context;
120 struct r600_perfcounters;
121 struct tgsi_shader_info;
122
123 struct radeon_shader_reloc {
124 char name[32];
125 uint64_t offset;
126 };
127
128 struct radeon_shader_binary {
129 /** Shader code */
130 unsigned char *code;
131 unsigned code_size;
132
133 /** Config/Context register state that accompanies this shader.
134 * This is a stream of dword pairs. First dword contains the
135 * register address, the second dword contains the value.*/
136 unsigned char *config;
137 unsigned config_size;
138
139 /** The number of bytes of config information for each global symbol.
140 */
141 unsigned config_size_per_symbol;
142
143 /** Constant data accessed by the shader. This will be uploaded
144 * into a constant buffer. */
145 unsigned char *rodata;
146 unsigned rodata_size;
147
148 /** List of symbol offsets for the shader */
149 uint64_t *global_symbol_offsets;
150 unsigned global_symbol_count;
151
152 struct radeon_shader_reloc *relocs;
153 unsigned reloc_count;
154
155 /** Disassembled shader in a string. */
156 char *disasm_string;
157 };
158
159 void radeon_shader_binary_init(struct radeon_shader_binary *b);
160 void radeon_shader_binary_clean(struct radeon_shader_binary *b);
161
162 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
163 * at the moment.
164 */
165 struct r600_resource {
166 struct u_resource b;
167
168 /* Winsys objects. */
169 struct pb_buffer *buf;
170 uint64_t gpu_address;
171
172 /* Resource state. */
173 enum radeon_bo_domain domains;
174
175 /* The buffer range which is initialized (with a write transfer,
176 * streamout, DMA, or as a random access target). The rest of
177 * the buffer is considered invalid and can be mapped unsynchronized.
178 *
179 * This allows unsychronized mapping of a buffer range which hasn't
180 * been used yet. It's for applications which forget to use
181 * the unsynchronized map flag and expect the driver to figure it out.
182 */
183 struct util_range valid_buffer_range;
184
185 /* For buffers only. This indicates that a write operation has been
186 * performed by TC L2, but the cache hasn't been flushed.
187 * Any hw block which doesn't use or bypasses TC L2 should check this
188 * flag and flush the cache before using the buffer.
189 *
190 * For example, TC L2 must be flushed if a buffer which has been
191 * modified by a shader store instruction is about to be used as
192 * an index buffer. The reason is that VGT DMA index fetching doesn't
193 * use TC L2.
194 */
195 bool TC_L2_dirty;
196
197 /* Whether the resource has been exported via resource_get_handle. */
198 bool is_shared;
199 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
200 };
201
202 struct r600_transfer {
203 struct pipe_transfer transfer;
204 struct r600_resource *staging;
205 unsigned offset;
206 };
207
208 struct r600_fmask_info {
209 uint64_t offset;
210 uint64_t size;
211 unsigned alignment;
212 unsigned pitch_in_pixels;
213 unsigned bank_height;
214 unsigned slice_tile_max;
215 unsigned tile_mode_index;
216 };
217
218 struct r600_cmask_info {
219 uint64_t offset;
220 uint64_t size;
221 unsigned alignment;
222 unsigned pitch;
223 unsigned height;
224 unsigned xalign;
225 unsigned yalign;
226 unsigned slice_tile_max;
227 unsigned base_address_reg;
228 };
229
230 struct r600_htile_info {
231 unsigned pitch;
232 unsigned height;
233 unsigned xalign;
234 unsigned yalign;
235 };
236
237 struct r600_texture {
238 struct r600_resource resource;
239
240 uint64_t size;
241 unsigned num_level0_transfers;
242 bool is_depth;
243 unsigned dirty_level_mask; /* each bit says if that mipmap is compressed */
244 unsigned stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
245 struct r600_texture *flushed_depth_texture;
246 bool is_flushing_texture;
247 struct radeon_surf surface;
248
249 /* Colorbuffer compression and fast clear. */
250 struct r600_fmask_info fmask;
251 struct r600_cmask_info cmask;
252 struct r600_resource *cmask_buffer;
253 uint64_t dcc_offset; /* 0 = disabled */
254 unsigned cb_color_info; /* fast clear enable bit */
255 unsigned color_clear_value[2];
256 unsigned last_msaa_resolve_target_micro_mode;
257
258 /* Depth buffer compression and fast clear. */
259 struct r600_htile_info htile;
260 struct r600_resource *htile_buffer;
261 bool depth_cleared; /* if it was cleared at least once */
262 float depth_clear_value;
263 bool stencil_cleared; /* if it was cleared at least once */
264 uint8_t stencil_clear_value;
265
266 bool non_disp_tiling; /* R600-Cayman only */
267
268 /* Whether the texture is a displayable back buffer and needs DCC
269 * decompression, which is expensive. Therefore, it's enabled only
270 * if statistics suggest that it will pay off and it's allocated
271 * separately. Limited to target == 2D and last_level == 0. If enabled,
272 * dcc_offset contains the absolute GPUVM address, not the relative one.
273 */
274 struct r600_resource *dcc_separate_buffer;
275
276 /* Counter that should be non-zero if the texture is bound to a
277 * framebuffer. Implemented in radeonsi only.
278 */
279 uint32_t framebuffers_bound;
280 };
281
282 struct r600_surface {
283 struct pipe_surface base;
284 const struct radeon_surf_level *level_info;
285
286 bool color_initialized;
287 bool depth_initialized;
288
289 /* Misc. color flags. */
290 bool alphatest_bypass;
291 bool export_16bpc;
292 bool color_is_int8;
293
294 /* Color registers. */
295 unsigned cb_color_info;
296 unsigned cb_color_base;
297 unsigned cb_color_view;
298 unsigned cb_color_size; /* R600 only */
299 unsigned cb_color_dim; /* EG only */
300 unsigned cb_color_pitch; /* EG and later */
301 unsigned cb_color_slice; /* EG and later */
302 unsigned cb_color_attrib; /* EG and later */
303 unsigned cb_dcc_control; /* VI and later */
304 unsigned cb_color_fmask; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
305 unsigned cb_color_fmask_slice; /* EG and later */
306 unsigned cb_color_cmask; /* CB_COLORn_TILE (r600 only) */
307 unsigned cb_color_mask; /* R600 only */
308 unsigned spi_shader_col_format; /* SI+, no blending, no alpha-to-coverage. */
309 unsigned spi_shader_col_format_alpha; /* SI+, alpha-to-coverage */
310 unsigned spi_shader_col_format_blend; /* SI+, blending without alpha. */
311 unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
312 struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
313 struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
314
315 /* DB registers. */
316 unsigned db_depth_info; /* R600 only, then SI and later */
317 unsigned db_z_info; /* EG and later */
318 unsigned db_depth_base; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
319 unsigned db_depth_view;
320 unsigned db_depth_size;
321 unsigned db_depth_slice; /* EG and later */
322 unsigned db_stencil_base; /* EG and later */
323 unsigned db_stencil_info; /* EG and later */
324 unsigned db_prefetch_limit; /* R600 only */
325 unsigned db_htile_surface;
326 unsigned db_htile_data_base;
327 unsigned db_preload_control; /* EG and later */
328 };
329
330 struct r600_common_screen {
331 struct pipe_screen b;
332 struct radeon_winsys *ws;
333 enum radeon_family family;
334 enum chip_class chip_class;
335 struct radeon_info info;
336 uint64_t debug_flags;
337 bool has_cp_dma;
338 bool has_streamout;
339
340 /* Texture filter settings. */
341 int force_aniso; /* -1 = disabled */
342
343 /* Auxiliary context. Mainly used to initialize resources.
344 * It must be locked prior to using and flushed before unlocking. */
345 struct pipe_context *aux_context;
346 pipe_mutex aux_context_lock;
347
348 /* This must be in the screen, because UE4 uses one context for
349 * compilation and another one for rendering.
350 */
351 unsigned num_compilations;
352 /* Along with ST_DEBUG=precompile, this should show if applications
353 * are loading shaders on demand. This is a monotonic counter.
354 */
355 unsigned num_shaders_created;
356
357 /* GPU load thread. */
358 pipe_mutex gpu_load_mutex;
359 pipe_thread gpu_load_thread;
360 unsigned gpu_load_counter_busy;
361 unsigned gpu_load_counter_idle;
362 volatile unsigned gpu_load_stop_thread; /* bool */
363
364 char renderer_string[64];
365
366 /* Performance counters. */
367 struct r600_perfcounters *perfcounters;
368
369 /* If pipe_screen wants to re-emit the framebuffer state of all
370 * contexts, it should atomically increment this. Each context will
371 * compare this with its own last known value of the counter before
372 * drawing and re-emit the framebuffer state accordingly.
373 */
374 unsigned dirty_fb_counter;
375
376 /* Atomically increment this counter when an existing texture's
377 * metadata is enabled or disabled in a way that requires changing
378 * contexts' compressed texture binding masks.
379 */
380 unsigned compressed_colortex_counter;
381
382 /* Atomically increment this counter when an existing texture's
383 * backing buffer or tile mode parameters have changed that requires
384 * recomputation of shader descriptors.
385 */
386 unsigned dirty_tex_descriptor_counter;
387
388 void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
389 struct r600_texture *rtex,
390 struct radeon_bo_metadata *md);
391
392 void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
393 struct r600_texture *rtex,
394 struct radeon_bo_metadata *md);
395 };
396
397 /* This encapsulates a state or an operation which can emitted into the GPU
398 * command stream. */
399 struct r600_atom {
400 void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
401 unsigned num_dw;
402 unsigned short id;
403 };
404
405 struct r600_so_target {
406 struct pipe_stream_output_target b;
407
408 /* The buffer where BUFFER_FILLED_SIZE is stored. */
409 struct r600_resource *buf_filled_size;
410 unsigned buf_filled_size_offset;
411 bool buf_filled_size_valid;
412
413 unsigned stride_in_dw;
414 };
415
416 struct r600_streamout {
417 struct r600_atom begin_atom;
418 bool begin_emitted;
419 unsigned num_dw_for_end;
420
421 unsigned enabled_mask;
422 unsigned num_targets;
423 struct r600_so_target *targets[PIPE_MAX_SO_BUFFERS];
424
425 unsigned append_bitmask;
426 bool suspended;
427
428 /* External state which comes from the vertex shader,
429 * it must be set explicitly when binding a shader. */
430 unsigned *stride_in_dw;
431 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
432
433 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
434 unsigned hw_enabled_mask;
435
436 /* The state of VGT_STRMOUT_(CONFIG|EN). */
437 struct r600_atom enable_atom;
438 bool streamout_enabled;
439 bool prims_gen_query_enabled;
440 int num_prims_gen_queries;
441 };
442
443 struct r600_signed_scissor {
444 int minx;
445 int miny;
446 int maxx;
447 int maxy;
448 };
449
450 struct r600_scissors {
451 struct r600_atom atom;
452 unsigned dirty_mask;
453 struct pipe_scissor_state states[R600_MAX_VIEWPORTS];
454 };
455
456 struct r600_viewports {
457 struct r600_atom atom;
458 unsigned dirty_mask;
459 struct pipe_viewport_state states[R600_MAX_VIEWPORTS];
460 struct r600_signed_scissor as_scissor[R600_MAX_VIEWPORTS];
461 };
462
463 struct r600_ring {
464 struct radeon_winsys_cs *cs;
465 void (*flush)(void *ctx, unsigned flags,
466 struct pipe_fence_handle **fence);
467 };
468
469 /* Saved CS data for debugging features. */
470 struct radeon_saved_cs {
471 uint32_t *ib;
472 unsigned num_dw;
473
474 struct radeon_bo_list_item *bo_list;
475 unsigned bo_count;
476 };
477
478 struct r600_common_context {
479 struct pipe_context b; /* base class */
480
481 struct r600_common_screen *screen;
482 struct radeon_winsys *ws;
483 struct radeon_winsys_ctx *ctx;
484 enum radeon_family family;
485 enum chip_class chip_class;
486 struct r600_ring gfx;
487 struct r600_ring dma;
488 struct pipe_fence_handle *last_sdma_fence;
489 unsigned initial_gfx_cs_size;
490 unsigned gpu_reset_counter;
491 unsigned last_dirty_fb_counter;
492 unsigned last_compressed_colortex_counter;
493 unsigned last_dirty_tex_descriptor_counter;
494
495 struct u_upload_mgr *uploader;
496 struct u_suballocator *allocator_zeroed_memory;
497 struct util_slab_mempool pool_transfers;
498
499 /* Current unaccounted memory usage. */
500 uint64_t vram;
501 uint64_t gtt;
502
503 /* States. */
504 struct r600_streamout streamout;
505 struct r600_scissors scissors;
506 struct r600_viewports viewports;
507 bool scissor_enabled;
508 bool vs_writes_viewport_index;
509 bool vs_disables_clipping_viewport;
510
511 /* Additional context states. */
512 unsigned flags; /* flush flags */
513
514 /* Queries. */
515 /* Maintain the list of active queries for pausing between IBs. */
516 int num_occlusion_queries;
517 int num_perfect_occlusion_queries;
518 struct list_head active_queries;
519 unsigned num_cs_dw_queries_suspend;
520 /* Additional hardware info. */
521 unsigned backend_mask;
522 unsigned max_db; /* for OQ */
523 /* Misc stats. */
524 unsigned num_draw_calls;
525 unsigned num_spill_draw_calls;
526 unsigned num_compute_calls;
527 unsigned num_spill_compute_calls;
528 unsigned num_dma_calls;
529 uint64_t num_alloc_tex_transfer_bytes;
530
531 /* Render condition. */
532 struct r600_atom render_cond_atom;
533 struct pipe_query *render_cond;
534 unsigned render_cond_mode;
535 bool render_cond_invert;
536 bool render_cond_force_off; /* for u_blitter */
537
538 /* MSAA sample locations.
539 * The first index is the sample index.
540 * The second index is the coordinate: X, Y. */
541 float sample_locations_1x[1][2];
542 float sample_locations_2x[2][2];
543 float sample_locations_4x[4][2];
544 float sample_locations_8x[8][2];
545 float sample_locations_16x[16][2];
546
547 /* The list of all texture buffer objects in this context.
548 * This list is walked when a buffer is invalidated/reallocated and
549 * the GPU addresses are updated. */
550 struct list_head texture_buffers;
551
552 struct pipe_debug_callback debug;
553
554 /* Copy one resource to another using async DMA. */
555 void (*dma_copy)(struct pipe_context *ctx,
556 struct pipe_resource *dst,
557 unsigned dst_level,
558 unsigned dst_x, unsigned dst_y, unsigned dst_z,
559 struct pipe_resource *src,
560 unsigned src_level,
561 const struct pipe_box *src_box);
562
563 void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
564 uint64_t offset, uint64_t size, unsigned value,
565 enum r600_coherency coher);
566
567 void (*blit_decompress_depth)(struct pipe_context *ctx,
568 struct r600_texture *texture,
569 struct r600_texture *staging,
570 unsigned first_level, unsigned last_level,
571 unsigned first_layer, unsigned last_layer,
572 unsigned first_sample, unsigned last_sample);
573
574 void (*decompress_dcc)(struct pipe_context *ctx,
575 struct r600_texture *rtex);
576
577 /* Reallocate the buffer and update all resource bindings where
578 * the buffer is bound, including all resource descriptors. */
579 void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
580
581 /* Enable or disable occlusion queries. */
582 void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
583
584 /* This ensures there is enough space in the command stream. */
585 void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
586 bool include_draw_vbo);
587
588 void (*set_atom_dirty)(struct r600_common_context *ctx,
589 struct r600_atom *atom, bool dirty);
590
591 void (*check_vm_faults)(struct r600_common_context *ctx,
592 struct radeon_saved_cs *saved,
593 enum ring_type ring);
594 };
595
596 /* r600_buffer.c */
597 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
598 struct pb_buffer *buf,
599 enum radeon_bo_usage usage);
600 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
601 struct r600_resource *resource,
602 unsigned usage);
603 bool r600_init_resource(struct r600_common_screen *rscreen,
604 struct r600_resource *res,
605 uint64_t size, unsigned alignment);
606 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
607 const struct pipe_resource *templ,
608 unsigned alignment);
609 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
610 unsigned bind,
611 unsigned usage,
612 unsigned size,
613 unsigned alignment);
614 struct pipe_resource *
615 r600_buffer_from_user_memory(struct pipe_screen *screen,
616 const struct pipe_resource *templ,
617 void *user_memory);
618 void
619 r600_invalidate_resource(struct pipe_context *ctx,
620 struct pipe_resource *resource);
621
622 /* r600_common_pipe.c */
623 void r600_draw_rectangle(struct blitter_context *blitter,
624 int x1, int y1, int x2, int y2, float depth,
625 enum blitter_attrib_type type,
626 const union pipe_color_union *attrib);
627 bool r600_common_screen_init(struct r600_common_screen *rscreen,
628 struct radeon_winsys *ws);
629 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
630 void r600_preflush_suspend_features(struct r600_common_context *ctx);
631 void r600_postflush_resume_features(struct r600_common_context *ctx);
632 bool r600_common_context_init(struct r600_common_context *rctx,
633 struct r600_common_screen *rscreen);
634 void r600_common_context_cleanup(struct r600_common_context *rctx);
635 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
636 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
637 unsigned processor);
638 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
639 uint64_t offset, uint64_t size, unsigned value,
640 enum r600_coherency coher);
641 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
642 const struct pipe_resource *templ);
643 const char *r600_get_llvm_processor_name(enum radeon_family family);
644 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
645 struct r600_resource *dst, struct r600_resource *src);
646 void r600_dma_emit_wait_idle(struct r600_common_context *rctx);
647 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
648 struct radeon_saved_cs *saved);
649 void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
650
651 /* r600_gpu_load.c */
652 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
653 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
654 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
655
656 /* r600_perfcounters.c */
657 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
658
659 /* r600_query.c */
660 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
661 void r600_query_init(struct r600_common_context *rctx);
662 void r600_suspend_queries(struct r600_common_context *ctx);
663 void r600_resume_queries(struct r600_common_context *ctx);
664 void r600_query_init_backend_mask(struct r600_common_context *ctx);
665
666 /* r600_streamout.c */
667 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
668 void r600_set_streamout_targets(struct pipe_context *ctx,
669 unsigned num_targets,
670 struct pipe_stream_output_target **targets,
671 const unsigned *offset);
672 void r600_emit_streamout_end(struct r600_common_context *rctx);
673 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
674 unsigned type, int diff);
675 void r600_streamout_init(struct r600_common_context *rctx);
676
677 /* r600_test_dma.c */
678 void r600_test_dma(struct r600_common_screen *rscreen);
679
680 /* r600_texture.c */
681 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
682 struct r600_texture *rdst,
683 unsigned dst_level, unsigned dstx,
684 unsigned dsty, unsigned dstz,
685 struct r600_texture *rsrc,
686 unsigned src_level,
687 const struct pipe_box *src_box);
688 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
689 struct r600_texture *rtex,
690 unsigned nr_samples,
691 struct r600_fmask_info *out);
692 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
693 struct r600_texture *rtex,
694 struct r600_cmask_info *out);
695 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
696 struct pipe_resource *texture,
697 struct r600_texture **staging);
698 void r600_print_texture_info(struct r600_texture *rtex, FILE *f);
699 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
700 const struct pipe_resource *templ);
701 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
702 struct pipe_resource *texture,
703 const struct pipe_surface *templ,
704 unsigned width, unsigned height);
705 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
706 void vi_dcc_clear_level(struct r600_common_context *rctx,
707 struct r600_texture *rtex,
708 unsigned level, unsigned clear_value);
709 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
710 struct pipe_framebuffer_state *fb,
711 struct r600_atom *fb_state,
712 unsigned *buffers, unsigned *dirty_cbufs,
713 const union pipe_color_union *color);
714 bool r600_texture_disable_dcc(struct r600_common_screen *rscreen,
715 struct r600_texture *rtex);
716 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
717 void r600_init_context_texture_functions(struct r600_common_context *rctx);
718
719 /* r600_viewport.c */
720 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
721 struct pipe_scissor_state *scissor);
722 void r600_set_scissor_enable(struct r600_common_context *rctx, bool enable);
723 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
724 struct tgsi_shader_info *info);
725 void r600_init_viewport_functions(struct r600_common_context *rctx);
726
727 /* cayman_msaa.c */
728 extern const uint32_t eg_sample_locs_2x[4];
729 extern const unsigned eg_max_dist_2x;
730 extern const uint32_t eg_sample_locs_4x[4];
731 extern const unsigned eg_max_dist_4x;
732 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
733 unsigned sample_index, float *out_value);
734 void cayman_init_msaa(struct pipe_context *ctx);
735 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
736 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
737 int ps_iter_samples, int overrast_samples,
738 unsigned sc_mode_cntl_1);
739
740
741 /* Inline helpers. */
742
743 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
744 {
745 return (struct r600_resource*)r;
746 }
747
748 static inline void
749 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
750 {
751 pipe_resource_reference((struct pipe_resource **)ptr,
752 (struct pipe_resource *)res);
753 }
754
755 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
756 {
757 return rctx->streamout.streamout_enabled ||
758 rctx->streamout.prims_gen_query_enabled;
759 }
760
761 #define SQ_TEX_XY_FILTER_POINT 0x00
762 #define SQ_TEX_XY_FILTER_BILINEAR 0x01
763 #define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
764 #define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03
765
766 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
767 {
768 if (filter == PIPE_TEX_FILTER_LINEAR)
769 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
770 : SQ_TEX_XY_FILTER_BILINEAR;
771 else
772 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
773 : SQ_TEX_XY_FILTER_POINT;
774 }
775
776 static inline unsigned r600_tex_aniso_filter(unsigned filter)
777 {
778 if (filter < 2)
779 return 0;
780 if (filter < 4)
781 return 1;
782 if (filter < 8)
783 return 2;
784 if (filter < 16)
785 return 3;
786 return 4;
787 }
788
789 static inline unsigned r600_wavefront_size(enum radeon_family family)
790 {
791 switch (family) {
792 case CHIP_RV610:
793 case CHIP_RS780:
794 case CHIP_RV620:
795 case CHIP_RS880:
796 return 16;
797 case CHIP_RV630:
798 case CHIP_RV635:
799 case CHIP_RV730:
800 case CHIP_RV710:
801 case CHIP_PALM:
802 case CHIP_CEDAR:
803 return 32;
804 default:
805 return 64;
806 }
807 }
808
809 static inline enum radeon_bo_priority
810 r600_get_sampler_view_priority(struct r600_resource *res)
811 {
812 if (res->b.b.target == PIPE_BUFFER)
813 return RADEON_PRIO_SAMPLER_BUFFER;
814
815 if (res->b.b.nr_samples > 1)
816 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
817
818 return RADEON_PRIO_SAMPLER_TEXTURE;
819 }
820
821 #define COMPUTE_DBG(rscreen, fmt, args...) \
822 do { \
823 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
824 } while (0);
825
826 #define R600_ERR(fmt, args...) \
827 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
828
829 /* For MSAA sample positions. */
830 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
831 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
832 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
833 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
834 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
835
836 #endif