src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "amd/common/ac_binary.h"
  38
  39 #include "radeon/radeon_winsys.h"
  40
  41 #include "util/disk_cache.h"
  42 #include "util/u_blitter.h"
  43 #include "util/list.h"
  44 #include "util/u_range.h"
  45 #include "util/slab.h"
  46 #include "util/u_suballoc.h"
  47 #include "util/u_transfer.h"
  48 #include "util/u_threaded_context.h"
  49
  50 struct u_log_context;
  51
  52 #define ATI_VENDOR_ID 0x1002
  53
  54 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  55 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  56 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  57 #define R600_RESOURCE_FLAG_DISABLE_DCC          (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
  58 #define R600_RESOURCE_FLAG_UNMAPPABLE           (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
  59
  60 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  61 /* Pipeline & streamout query controls. */
  62 #define R600_CONTEXT_START_PIPELINE_STATS       (1u << 1)
  63 #define R600_CONTEXT_STOP_PIPELINE_STATS        (1u << 2)
  64 #define R600_CONTEXT_FLUSH_FOR_RENDER_COND      (1u << 3)
  65 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 4)
  66
  67 /* special primitive types */
  68 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  69
  70 #define R600_NOT_QUERY          0xffffffff
  71
  72 /* Debug flags. */
  73 enum {
  74         /* Shader logging options: */
  75         DBG_VS = PIPE_SHADER_VERTEX,
  76         DBG_PS = PIPE_SHADER_FRAGMENT,
  77         DBG_GS = PIPE_SHADER_GEOMETRY,
  78         DBG_TCS = PIPE_SHADER_TESS_CTRL,
  79         DBG_TES = PIPE_SHADER_TESS_EVAL,
  80         DBG_CS = PIPE_SHADER_COMPUTE,
  81         DBG_NO_IR,
  82         DBG_NO_TGSI,
  83         DBG_NO_ASM,
  84         DBG_PREOPT_IR,
  85
  86         /* Shader compiler options the shader cache should be aware of: */
  87         DBG_FS_CORRECT_DERIVS_AFTER_KILL,
  88         DBG_UNSAFE_MATH,
  89         DBG_SI_SCHED,
  90
  91         /* Shader compiler options (with no effect on the shader cache): */
  92         DBG_CHECK_IR,
  93         DBG_PRECOMPILE,
  94         DBG_NIR,
  95         DBG_MONOLITHIC_SHADERS,
  96         DBG_NO_OPT_VARIANT,
  97
  98         /* Information logging options: */
  99         DBG_INFO,
 100         DBG_TEX,
 101         DBG_COMPUTE,
 102         DBG_VM,
 103
 104         /* Driver options: */
 105         DBG_FORCE_DMA,
 106         DBG_NO_ASYNC_DMA,
 107         DBG_NO_DISCARD_RANGE,
 108         DBG_NO_WC,
 109         DBG_CHECK_VM,
 110
 111         /* 3D engine options: */
 112         DBG_SWITCH_ON_EOP,
 113         DBG_NO_OUT_OF_ORDER,
 114         DBG_NO_DPBB,
 115         DBG_NO_DFSM,
 116         DBG_DPBB,
 117         DBG_DFSM,
 118         DBG_NO_HYPERZ,
 119         DBG_NO_RB_PLUS,
 120         DBG_NO_2D_TILING,
 121         DBG_NO_TILING,
 122         DBG_NO_DCC,
 123         DBG_NO_DCC_CLEAR,
 124         DBG_NO_DCC_FB,
 125
 126         /* Tests: */
 127         DBG_TEST_DMA,
 128         DBG_TEST_VMFAULT_CP,
 129         DBG_TEST_VMFAULT_SDMA,
 130         DBG_TEST_VMFAULT_SHADER,
 131 };
 132
 133 #define DBG_ALL_SHADERS         (((1 << (DBG_CS + 1)) - 1))
 134 #define DBG(name)               (1ull << DBG_##name)
 135
 136 #define R600_MAP_BUFFER_ALIGNMENT 64
 137
 138 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
 139
 140 enum r600_coherency {
 141         R600_COHERENCY_NONE, /* no cache flushes needed */
 142         R600_COHERENCY_SHADER,
 143         R600_COHERENCY_CB_META,
 144 };
 145
 146 #ifdef PIPE_ARCH_BIG_ENDIAN
 147 #define R600_BIG_ENDIAN 1
 148 #else
 149 #define R600_BIG_ENDIAN 0
 150 #endif
 151
 152 struct r600_common_context;
 153 struct r600_perfcounters;
 154 struct tgsi_shader_info;
 155 struct r600_qbo_state;
 156
 157 void si_radeon_shader_binary_init(struct ac_shader_binary *b);
 158 void si_radeon_shader_binary_clean(struct ac_shader_binary *b);
 159
 160 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
 161  * at the moment.
 162  */
 163 struct r600_resource {
 164         struct threaded_resource        b;
 165
 166         /* Winsys objects. */
 167         struct pb_buffer                *buf;
 168         uint64_t                        gpu_address;
 169         /* Memory usage if the buffer placement is optimal. */
 170         uint64_t                        vram_usage;
 171         uint64_t                        gart_usage;
 172
 173         /* Resource properties. */
 174         uint64_t                        bo_size;
 175         unsigned                        bo_alignment;
 176         enum radeon_bo_domain           domains;
 177         enum radeon_bo_flag             flags;
 178         unsigned                        bind_history;
 179
 180         /* The buffer range which is initialized (with a write transfer,
 181          * streamout, DMA, or as a random access target). The rest of
 182          * the buffer is considered invalid and can be mapped unsynchronized.
 183          *
 184          * This allows unsychronized mapping of a buffer range which hasn't
 185          * been used yet. It's for applications which forget to use
 186          * the unsynchronized map flag and expect the driver to figure it out.
 187          */
 188         struct util_range               valid_buffer_range;
 189
 190         /* For buffers only. This indicates that a write operation has been
 191          * performed by TC L2, but the cache hasn't been flushed.
 192          * Any hw block which doesn't use or bypasses TC L2 should check this
 193          * flag and flush the cache before using the buffer.
 194          *
 195          * For example, TC L2 must be flushed if a buffer which has been
 196          * modified by a shader store instruction is about to be used as
 197          * an index buffer. The reason is that VGT DMA index fetching doesn't
 198          * use TC L2.
 199          */
 200         bool                            TC_L2_dirty;
 201
 202         /* Whether the resource has been exported via resource_get_handle. */
 203         unsigned                        external_usage; /* PIPE_HANDLE_USAGE_* */
 204
 205         /* Whether this resource is referenced by bindless handles. */
 206         bool                            texture_handle_allocated;
 207         bool                            image_handle_allocated;
 208 };
 209
 210 struct r600_transfer {
 211         struct threaded_transfer        b;
 212         struct r600_resource            *staging;
 213         unsigned                        offset;
 214 };
 215
 216 struct r600_fmask_info {
 217         uint64_t offset;
 218         uint64_t size;
 219         unsigned alignment;
 220         unsigned pitch_in_pixels;
 221         unsigned bank_height;
 222         unsigned slice_tile_max;
 223         unsigned tile_mode_index;
 224         unsigned tile_swizzle;
 225 };
 226
 227 struct r600_cmask_info {
 228         uint64_t offset;
 229         uint64_t size;
 230         unsigned alignment;
 231         unsigned slice_tile_max;
 232         uint64_t base_address_reg;
 233 };
 234
 235 struct r600_texture {
 236         struct r600_resource            resource;
 237
 238         uint64_t                        size;
 239         unsigned                        num_level0_transfers;
 240         enum pipe_format                db_render_format;
 241         bool                            is_depth;
 242         bool                            db_compatible;
 243         bool                            can_sample_z;
 244         bool                            can_sample_s;
 245         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 246         unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 247         struct r600_texture             *flushed_depth_texture;
 248         struct radeon_surf              surface;
 249
 250         /* Colorbuffer compression and fast clear. */
 251         struct r600_fmask_info          fmask;
 252         struct r600_cmask_info          cmask;
 253         struct r600_resource            *cmask_buffer;
 254         uint64_t                        dcc_offset; /* 0 = disabled */
 255         unsigned                        cb_color_info; /* fast clear enable bit */
 256         unsigned                        color_clear_value[2];
 257         unsigned                        last_msaa_resolve_target_micro_mode;
 258
 259         /* Depth buffer compression and fast clear. */
 260         uint64_t                        htile_offset;
 261         bool                            tc_compatible_htile;
 262         bool                            depth_cleared; /* if it was cleared at least once */
 263         float                           depth_clear_value;
 264         bool                            stencil_cleared; /* if it was cleared at least once */
 265         uint8_t                         stencil_clear_value;
 266         bool                            upgraded_depth; /* upgraded from unorm to Z32_FLOAT */
 267
 268         bool                            non_disp_tiling; /* R600-Cayman only */
 269
 270         /* Whether the texture is a displayable back buffer and needs DCC
 271          * decompression, which is expensive. Therefore, it's enabled only
 272          * if statistics suggest that it will pay off and it's allocated
 273          * separately. It can't be bound as a sampler by apps. Limited to
 274          * target == 2D and last_level == 0. If enabled, dcc_offset contains
 275          * the absolute GPUVM address, not the relative one.
 276          */
 277         struct r600_resource            *dcc_separate_buffer;
 278         /* When DCC is temporarily disabled, the separate buffer is here. */
 279         struct r600_resource            *last_dcc_separate_buffer;
 280         /* We need to track DCC dirtiness, because st/dri usually calls
 281          * flush_resource twice per frame (not a bug) and we don't wanna
 282          * decompress DCC twice. Also, the dirty tracking must be done even
 283          * if DCC isn't used, because it's required by the DCC usage analysis
 284          * for a possible future enablement.
 285          */
 286         bool                            separate_dcc_dirty;
 287         /* Statistics gathering for the DCC enablement heuristic. */
 288         bool                            dcc_gather_statistics;
 289         /* Estimate of how much this color buffer is written to in units of
 290          * full-screen draws: ps_invocations / (width * height)
 291          * Shader kills, late Z, and blending with trivial discards make it
 292          * inaccurate (we need to count CB updates, not PS invocations).
 293          */
 294         unsigned                        ps_draw_ratio;
 295         /* The number of clears since the last DCC usage analysis. */
 296         unsigned                        num_slow_clears;
 297
 298         /* Counter that should be non-zero if the texture is bound to a
 299          * framebuffer. Implemented in radeonsi only.
 300          */
 301         uint32_t                        framebuffers_bound;
 302 };
 303
 304 struct r600_surface {
 305         struct pipe_surface             base;
 306
 307         /* These can vary with block-compressed textures. */
 308         unsigned width0;
 309         unsigned height0;
 310
 311         bool color_initialized;
 312         bool depth_initialized;
 313
 314         /* Misc. color flags. */
 315         bool alphatest_bypass;
 316         bool export_16bpc;
 317         bool color_is_int8;
 318         bool color_is_int10;
 319         bool dcc_incompatible;
 320
 321         /* Color registers. */
 322         unsigned cb_color_info;
 323         unsigned cb_color_base;
 324         unsigned cb_color_view;
 325         unsigned cb_color_size;         /* R600 only */
 326         unsigned cb_color_dim;          /* EG only */
 327         unsigned cb_color_pitch;        /* EG and later */
 328         unsigned cb_color_slice;        /* EG and later */
 329         unsigned cb_color_attrib;       /* EG and later */
 330         unsigned cb_color_attrib2;      /* GFX9 and later */
 331         unsigned cb_dcc_control;        /* VI and later */
 332         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 333         unsigned cb_color_fmask_slice;  /* EG and later */
 334         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 335         unsigned cb_color_mask;         /* R600 only */
 336         unsigned spi_shader_col_format;         /* SI+, no blending, no alpha-to-coverage. */
 337         unsigned spi_shader_col_format_alpha;   /* SI+, alpha-to-coverage */
 338         unsigned spi_shader_col_format_blend;   /* SI+, blending without alpha. */
 339         unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
 340         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 341         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 342
 343         /* DB registers. */
 344         uint64_t db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 345         uint64_t db_stencil_base;       /* EG and later */
 346         uint64_t db_htile_data_base;
 347         unsigned db_depth_info;         /* R600 only, then SI and later */
 348         unsigned db_z_info;             /* EG and later */
 349         unsigned db_z_info2;            /* GFX9+ */
 350         unsigned db_depth_view;
 351         unsigned db_depth_size;
 352         unsigned db_depth_slice;        /* EG and later */
 353         unsigned db_stencil_info;       /* EG and later */
 354         unsigned db_stencil_info2;      /* GFX9+ */
 355         unsigned db_prefetch_limit;     /* R600 only */
 356         unsigned db_htile_surface;
 357         unsigned db_preload_control;    /* EG and later */
 358 };
 359
 360 struct r600_mmio_counter {
 361         unsigned busy;
 362         unsigned idle;
 363 };
 364
 365 union r600_mmio_counters {
 366         struct {
 367                 /* For global GPU load including SDMA. */
 368                 struct r600_mmio_counter gpu;
 369
 370                 /* GRBM_STATUS */
 371                 struct r600_mmio_counter spi;
 372                 struct r600_mmio_counter gui;
 373                 struct r600_mmio_counter ta;
 374                 struct r600_mmio_counter gds;
 375                 struct r600_mmio_counter vgt;
 376                 struct r600_mmio_counter ia;
 377                 struct r600_mmio_counter sx;
 378                 struct r600_mmio_counter wd;
 379                 struct r600_mmio_counter bci;
 380                 struct r600_mmio_counter sc;
 381                 struct r600_mmio_counter pa;
 382                 struct r600_mmio_counter db;
 383                 struct r600_mmio_counter cp;
 384                 struct r600_mmio_counter cb;
 385
 386                 /* SRBM_STATUS2 */
 387                 struct r600_mmio_counter sdma;
 388
 389                 /* CP_STAT */
 390                 struct r600_mmio_counter pfp;
 391                 struct r600_mmio_counter meq;
 392                 struct r600_mmio_counter me;
 393                 struct r600_mmio_counter surf_sync;
 394                 struct r600_mmio_counter cp_dma;
 395                 struct r600_mmio_counter scratch_ram;
 396         } named;
 397         unsigned array[0];
 398 };
 399
 400 struct r600_memory_object {
 401         struct pipe_memory_object       b;
 402         struct pb_buffer                *buf;
 403         uint32_t                        stride;
 404         uint32_t                        offset;
 405 };
 406
 407 struct r600_common_screen {
 408         struct pipe_screen              b;
 409         struct radeon_winsys            *ws;
 410         enum radeon_family              family;
 411         enum chip_class                 chip_class;
 412         struct radeon_info              info;
 413         uint64_t                        debug_flags;
 414         bool                            has_cp_dma;
 415         bool                            has_streamout;
 416         bool                            has_rbplus;     /* if RB+ registers exist */
 417         bool                            rbplus_allowed; /* if RB+ is allowed */
 418
 419         struct disk_cache               *disk_shader_cache;
 420
 421         struct slab_parent_pool         pool_transfers;
 422
 423         /* Texture filter settings. */
 424         int                             force_aniso; /* -1 = disabled */
 425
 426         /* Auxiliary context. Mainly used to initialize resources.
 427          * It must be locked prior to using and flushed before unlocking. */
 428         struct pipe_context             *aux_context;
 429         mtx_t                           aux_context_lock;
 430
 431         /* This must be in the screen, because UE4 uses one context for
 432          * compilation and another one for rendering.
 433          */
 434         unsigned                        num_compilations;
 435         /* Along with ST_DEBUG=precompile, this should show if applications
 436          * are loading shaders on demand. This is a monotonic counter.
 437          */
 438         unsigned                        num_shaders_created;
 439         unsigned                        num_shader_cache_hits;
 440
 441         /* GPU load thread. */
 442         mtx_t                           gpu_load_mutex;
 443         thrd_t                          gpu_load_thread;
 444         union r600_mmio_counters        mmio_counters;
 445         volatile unsigned               gpu_load_stop_thread; /* bool */
 446
 447         char                            renderer_string[100];
 448
 449         /* Performance counters. */
 450         struct r600_perfcounters        *perfcounters;
 451
 452         /* If pipe_screen wants to recompute and re-emit the framebuffer,
 453          * sampler, and image states of all contexts, it should atomically
 454          * increment this.
 455          *
 456          * Each context will compare this with its own last known value of
 457          * the counter before drawing and re-emit the states accordingly.
 458          */
 459         unsigned                        dirty_tex_counter;
 460
 461         /* Atomically increment this counter when an existing texture's
 462          * metadata is enabled or disabled in a way that requires changing
 463          * contexts' compressed texture binding masks.
 464          */
 465         unsigned                        compressed_colortex_counter;
 466
 467         struct {
 468                 /* Context flags to set so that all writes from earlier jobs
 469                  * in the CP are seen by L2 clients.
 470                  */
 471                 unsigned cp_to_L2;
 472
 473                 /* Context flags to set so that all writes from earlier jobs
 474                  * that end in L2 are seen by CP.
 475                  */
 476                 unsigned L2_to_cp;
 477
 478                 /* Context flags to set so that all writes from earlier
 479                  * compute jobs are seen by L2 clients.
 480                  */
 481                 unsigned compute_to_L2;
 482         } barrier_flags;
 483
 484         void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
 485                                       struct r600_texture *rtex,
 486                                       struct radeon_bo_metadata *md);
 487
 488         void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
 489                                     struct r600_texture *rtex,
 490                                     struct radeon_bo_metadata *md);
 491 };
 492
 493 /* This encapsulates a state or an operation which can emitted into the GPU
 494  * command stream. */
 495 struct r600_atom {
 496         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 497         unsigned short          id;
 498 };
 499
 500 struct r600_ring {
 501         struct radeon_winsys_cs         *cs;
 502         void (*flush)(void *ctx, unsigned flags,
 503                       struct pipe_fence_handle **fence);
 504 };
 505
 506 /* Saved CS data for debugging features. */
 507 struct radeon_saved_cs {
 508         uint32_t                        *ib;
 509         unsigned                        num_dw;
 510
 511         struct radeon_bo_list_item      *bo_list;
 512         unsigned                        bo_count;
 513 };
 514
 515 struct r600_common_context {
 516         struct pipe_context b; /* base class */
 517
 518         struct r600_common_screen       *screen;
 519         struct radeon_winsys            *ws;
 520         struct radeon_winsys_ctx        *ctx;
 521         enum radeon_family              family;
 522         enum chip_class                 chip_class;
 523         struct r600_ring                gfx;
 524         struct r600_ring                dma;
 525         struct pipe_fence_handle        *last_gfx_fence;
 526         struct pipe_fence_handle        *last_sdma_fence;
 527         struct r600_resource            *eop_bug_scratch;
 528         unsigned                        num_gfx_cs_flushes;
 529         unsigned                        initial_gfx_cs_size;
 530         unsigned                        gpu_reset_counter;
 531         unsigned                        last_dirty_tex_counter;
 532         unsigned                        last_compressed_colortex_counter;
 533         unsigned                        last_num_draw_calls;
 534
 535         struct threaded_context         *tc;
 536         struct u_suballocator           *allocator_zeroed_memory;
 537         struct slab_child_pool          pool_transfers;
 538         struct slab_child_pool          pool_transfers_unsync; /* for threaded_context */
 539
 540         /* Current unaccounted memory usage. */
 541         uint64_t                        vram;
 542         uint64_t                        gtt;
 543
 544         /* Additional context states. */
 545         unsigned flags; /* flush flags */
 546
 547         /* Queries. */
 548         /* Maintain the list of active queries for pausing between IBs. */
 549         int                             num_occlusion_queries;
 550         int                             num_perfect_occlusion_queries;
 551         struct list_head                active_queries;
 552         unsigned                        num_cs_dw_queries_suspend;
 553         /* Misc stats. */
 554         unsigned                        num_draw_calls;
 555         unsigned                        num_decompress_calls;
 556         unsigned                        num_mrt_draw_calls;
 557         unsigned                        num_prim_restart_calls;
 558         unsigned                        num_spill_draw_calls;
 559         unsigned                        num_compute_calls;
 560         unsigned                        num_spill_compute_calls;
 561         unsigned                        num_dma_calls;
 562         unsigned                        num_cp_dma_calls;
 563         unsigned                        num_vs_flushes;
 564         unsigned                        num_ps_flushes;
 565         unsigned                        num_cs_flushes;
 566         unsigned                        num_cb_cache_flushes;
 567         unsigned                        num_db_cache_flushes;
 568         unsigned                        num_L2_invalidates;
 569         unsigned                        num_L2_writebacks;
 570         unsigned                        num_resident_handles;
 571         uint64_t                        num_alloc_tex_transfer_bytes;
 572         unsigned                        last_tex_ps_draw_ratio; /* for query */
 573
 574         /* Render condition. */
 575         struct r600_atom                render_cond_atom;
 576         struct pipe_query               *render_cond;
 577         unsigned                        render_cond_mode;
 578         bool                            render_cond_invert;
 579         bool                            render_cond_force_off; /* for u_blitter */
 580
 581         /* MSAA sample locations.
 582          * The first index is the sample index.
 583          * The second index is the coordinate: X, Y. */
 584         float                           sample_locations_1x[1][2];
 585         float                           sample_locations_2x[2][2];
 586         float                           sample_locations_4x[4][2];
 587         float                           sample_locations_8x[8][2];
 588         float                           sample_locations_16x[16][2];
 589
 590         /* Statistics gathering for the DCC enablement heuristic. It can't be
 591          * in r600_texture because r600_texture can be shared by multiple
 592          * contexts. This is for back buffers only. We shouldn't get too many
 593          * of those.
 594          *
 595          * X11 DRI3 rotates among a finite set of back buffers. They should
 596          * all fit in this array. If they don't, separate DCC might never be
 597          * enabled by DCC stat gathering.
 598          */
 599         struct {
 600                 struct r600_texture             *tex;
 601                 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
 602                 struct pipe_query               *ps_stats[3];
 603                 /* If all slots are used and another slot is needed,
 604                  * the least recently used slot is evicted based on this. */
 605                 int64_t                         last_use_timestamp;
 606                 bool                            query_active;
 607         } dcc_stats[5];
 608
 609         struct pipe_debug_callback      debug;
 610         struct pipe_device_reset_callback device_reset_callback;
 611         struct u_log_context            *log;
 612
 613         void                            *query_result_shader;
 614
 615         /* Copy one resource to another using async DMA. */
 616         void (*dma_copy)(struct pipe_context *ctx,
 617                          struct pipe_resource *dst,
 618                          unsigned dst_level,
 619                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 620                          struct pipe_resource *src,
 621                          unsigned src_level,
 622                          const struct pipe_box *src_box);
 623
 624         void (*dma_clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 625                                  uint64_t offset, uint64_t size, unsigned value);
 626
 627         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 628                              uint64_t offset, uint64_t size, unsigned value,
 629                              enum r600_coherency coher);
 630
 631         void (*blit_decompress_depth)(struct pipe_context *ctx,
 632                                       struct r600_texture *texture,
 633                                       struct r600_texture *staging,
 634                                       unsigned first_level, unsigned last_level,
 635                                       unsigned first_layer, unsigned last_layer,
 636                                       unsigned first_sample, unsigned last_sample);
 637
 638         void (*decompress_dcc)(struct pipe_context *ctx,
 639                                struct r600_texture *rtex);
 640
 641         /* Reallocate the buffer and update all resource bindings where
 642          * the buffer is bound, including all resource descriptors. */
 643         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 644
 645         /* Update all resource bindings where the buffer is bound, including
 646          * all resource descriptors. This is invalidate_buffer without
 647          * the invalidation. */
 648         void (*rebind_buffer)(struct pipe_context *ctx, struct pipe_resource *buf,
 649                               uint64_t old_gpu_address);
 650
 651         /* Enable or disable occlusion queries. */
 652         void (*set_occlusion_query_state)(struct pipe_context *ctx,
 653                                           bool old_enable,
 654                                           bool old_perfect_enable);
 655
 656         void (*save_qbo_state)(struct pipe_context *ctx, struct r600_qbo_state *st);
 657
 658         /* This ensures there is enough space in the command stream. */
 659         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 660                                   bool include_draw_vbo);
 661
 662         void (*set_atom_dirty)(struct r600_common_context *ctx,
 663                                struct r600_atom *atom, bool dirty);
 664
 665         void (*check_vm_faults)(struct r600_common_context *ctx,
 666                                 struct radeon_saved_cs *saved,
 667                                 enum ring_type ring);
 668 };
 669
 670 /* r600_buffer_common.c */
 671 bool si_rings_is_buffer_referenced(struct r600_common_context *ctx,
 672                                    struct pb_buffer *buf,
 673                                    enum radeon_bo_usage usage);
 674 void *si_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 675                                     struct r600_resource *resource,
 676                                     unsigned usage);
 677 void si_buffer_subdata(struct pipe_context *ctx,
 678                        struct pipe_resource *buffer,
 679                        unsigned usage, unsigned offset,
 680                        unsigned size, const void *data);
 681 void si_init_resource_fields(struct r600_common_screen *rscreen,
 682                              struct r600_resource *res,
 683                              uint64_t size, unsigned alignment);
 684 bool si_alloc_resource(struct r600_common_screen *rscreen,
 685                        struct r600_resource *res);
 686 struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
 687                                        const struct pipe_resource *templ,
 688                                        unsigned alignment);
 689 struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
 690                                                unsigned flags,
 691                                                unsigned usage,
 692                                                unsigned size,
 693                                                unsigned alignment);
 694 struct pipe_resource *
 695 si_buffer_from_user_memory(struct pipe_screen *screen,
 696                            const struct pipe_resource *templ,
 697                            void *user_memory);
 698 void si_invalidate_resource(struct pipe_context *ctx,
 699                             struct pipe_resource *resource);
 700 void si_replace_buffer_storage(struct pipe_context *ctx,
 701                                struct pipe_resource *dst,
 702                                struct pipe_resource *src);
 703
 704 /* r600_common_pipe.c */
 705 void si_gfx_write_event_eop(struct r600_common_context *ctx,
 706                             unsigned event, unsigned event_flags,
 707                             unsigned data_sel,
 708                             struct r600_resource *buf, uint64_t va,
 709                             uint32_t new_fence, unsigned query_type);
 710 unsigned si_gfx_write_fence_dwords(struct r600_common_screen *screen);
 711 void si_gfx_wait_fence(struct r600_common_context *ctx,
 712                        uint64_t va, uint32_t ref, uint32_t mask);
 713 bool si_common_screen_init(struct r600_common_screen *rscreen,
 714                            struct radeon_winsys *ws);
 715 void si_destroy_common_screen(struct r600_common_screen *rscreen);
 716 void si_preflush_suspend_features(struct r600_common_context *ctx);
 717 void si_postflush_resume_features(struct r600_common_context *ctx);
 718 bool si_common_context_init(struct r600_common_context *rctx,
 719                             struct r600_common_screen *rscreen,
 720                             unsigned context_flags);
 721 void si_common_context_cleanup(struct r600_common_context *rctx);
 722 bool si_can_dump_shader(struct r600_common_screen *rscreen,
 723                         unsigned processor);
 724 bool si_extra_shader_checks(struct r600_common_screen *rscreen,
 725                             unsigned processor);
 726 void si_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 727                             uint64_t offset, uint64_t size, unsigned value);
 728 struct pipe_resource *si_resource_create_common(struct pipe_screen *screen,
 729                                                 const struct pipe_resource *templ);
 730 const char *si_get_llvm_processor_name(enum radeon_family family);
 731 void si_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
 732                        struct r600_resource *dst, struct r600_resource *src);
 733 void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
 734                 struct radeon_saved_cs *saved, bool get_buffer_list);
 735 void si_clear_saved_cs(struct radeon_saved_cs *saved);
 736 bool si_check_device_reset(struct r600_common_context *rctx);
 737
 738 /* r600_gpu_load.c */
 739 void si_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 740 uint64_t si_begin_counter(struct r600_common_screen *rscreen, unsigned type);
 741 unsigned si_end_counter(struct r600_common_screen *rscreen, unsigned type,
 742                         uint64_t begin);
 743
 744 /* r600_perfcounters.c */
 745 void si_perfcounters_destroy(struct r600_common_screen *rscreen);
 746
 747 /* r600_query.c */
 748 void si_init_screen_query_functions(struct r600_common_screen *rscreen);
 749 void si_init_query_functions(struct r600_common_context *rctx);
 750 void si_suspend_queries(struct r600_common_context *ctx);
 751 void si_resume_queries(struct r600_common_context *ctx);
 752
 753 /* r600_test_dma.c */
 754 void si_test_dma(struct r600_common_screen *rscreen);
 755
 756 /* r600_texture.c */
 757 bool si_prepare_for_dma_blit(struct r600_common_context *rctx,
 758                              struct r600_texture *rdst,
 759                              unsigned dst_level, unsigned dstx,
 760                              unsigned dsty, unsigned dstz,
 761                              struct r600_texture *rsrc,
 762                              unsigned src_level,
 763                              const struct pipe_box *src_box);
 764 void si_texture_get_fmask_info(struct r600_common_screen *rscreen,
 765                                struct r600_texture *rtex,
 766                                unsigned nr_samples,
 767                                struct r600_fmask_info *out);
 768 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
 769                                    struct pipe_resource *texture,
 770                                    struct r600_texture **staging);
 771 void si_print_texture_info(struct r600_common_screen *rscreen,
 772                            struct r600_texture *rtex, struct u_log_context *log);
 773 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
 774                                         const struct pipe_resource *templ);
 775 bool vi_dcc_formats_compatible(enum pipe_format format1,
 776                                enum pipe_format format2);
 777 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
 778                                      unsigned level,
 779                                      enum pipe_format view_format);
 780 void vi_disable_dcc_if_incompatible_format(struct r600_common_context *rctx,
 781                                            struct pipe_resource *tex,
 782                                            unsigned level,
 783                                            enum pipe_format view_format);
 784 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
 785                                               struct pipe_resource *texture,
 786                                               const struct pipe_surface *templ,
 787                                               unsigned width0, unsigned height0,
 788                                               unsigned width, unsigned height);
 789 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
 790 void vi_separate_dcc_start_query(struct pipe_context *ctx,
 791                                  struct r600_texture *tex);
 792 void vi_separate_dcc_stop_query(struct pipe_context *ctx,
 793                                 struct r600_texture *tex);
 794 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
 795                                              struct r600_texture *tex);
 796 void vi_dcc_clear_level(struct r600_common_context *rctx,
 797                         struct r600_texture *rtex,
 798                         unsigned level, unsigned clear_value);
 799 void si_do_fast_color_clear(struct r600_common_context *rctx,
 800                             struct pipe_framebuffer_state *fb,
 801                             struct r600_atom *fb_state,
 802                             unsigned *buffers, ubyte *dirty_cbufs,
 803                             const union pipe_color_union *color);
 804 bool si_texture_disable_dcc(struct r600_common_context *rctx,
 805                             struct r600_texture *rtex);
 806 void si_init_screen_texture_functions(struct r600_common_screen *rscreen);
 807 void si_init_context_texture_functions(struct r600_common_context *rctx);
 808
 809 /* cayman_msaa.c */
 810 void si_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 811                             unsigned sample_index, float *out_value);
 812 void si_init_msaa(struct pipe_context *ctx);
 813 void si_common_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 814 void si_common_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 815                                 int ps_iter_samples, int overrast_samples,
 816                                 unsigned sc_mode_cntl_1);
 817
 818
 819 /* Inline helpers. */
 820
 821 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 822 {
 823         return (struct r600_resource*)r;
 824 }
 825
 826 static inline void
 827 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 828 {
 829         pipe_resource_reference((struct pipe_resource **)ptr,
 830                                 (struct pipe_resource *)res);
 831 }
 832
 833 static inline void
 834 r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
 835 {
 836         pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
 837 }
 838
 839 static inline void
 840 r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 841 {
 842         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 843         struct r600_resource *res = (struct r600_resource *)r;
 844
 845         if (res) {
 846                 /* Add memory usage for need_gfx_cs_space */
 847                 rctx->vram += res->vram_usage;
 848                 rctx->gtt += res->gart_usage;
 849         }
 850 }
 851
 852 #define     SQ_TEX_XY_FILTER_POINT                         0x00
 853 #define     SQ_TEX_XY_FILTER_BILINEAR                      0x01
 854 #define     SQ_TEX_XY_FILTER_ANISO_POINT                   0x02
 855 #define     SQ_TEX_XY_FILTER_ANISO_BILINEAR                0x03
 856
 857 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
 858 {
 859         if (filter == PIPE_TEX_FILTER_LINEAR)
 860                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
 861                                      : SQ_TEX_XY_FILTER_BILINEAR;
 862         else
 863                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
 864                                      : SQ_TEX_XY_FILTER_POINT;
 865 }
 866
 867 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 868 {
 869         if (filter < 2)
 870                 return 0;
 871         if (filter < 4)
 872                 return 1;
 873         if (filter < 8)
 874                 return 2;
 875         if (filter < 16)
 876                 return 3;
 877         return 4;
 878 }
 879
 880 static inline enum radeon_bo_priority
 881 r600_get_sampler_view_priority(struct r600_resource *res)
 882 {
 883         if (res->b.b.target == PIPE_BUFFER)
 884                 return RADEON_PRIO_SAMPLER_BUFFER;
 885
 886         if (res->b.b.nr_samples > 1)
 887                 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
 888
 889         return RADEON_PRIO_SAMPLER_TEXTURE;
 890 }
 891
 892 static inline bool
 893 r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
 894 {
 895         return (stencil_sampler && tex->can_sample_s) ||
 896                (!stencil_sampler && tex->can_sample_z);
 897 }
 898
 899 static inline bool
 900 vi_dcc_enabled(struct r600_texture *tex, unsigned level)
 901 {
 902         return tex->dcc_offset && level < tex->surface.num_dcc_levels;
 903 }
 904
 905 static inline bool
 906 r600_htile_enabled(struct r600_texture *tex, unsigned level)
 907 {
 908         return tex->htile_offset && level == 0;
 909 }
 910
 911 static inline bool
 912 vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
 913 {
 914         assert(!tex->tc_compatible_htile || tex->htile_offset);
 915         return tex->tc_compatible_htile && level == 0;
 916 }
 917
 918 #define COMPUTE_DBG(rscreen, fmt, args...) \
 919         do { \
 920                 if ((rscreen->b.debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
 921         } while (0);
 922
 923 #define R600_ERR(fmt, args...) \
 924         fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
 925
 926 /* For MSAA sample positions. */
 927 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 928         (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) |                  \
 929         (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) |         \
 930         (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) |        \
 931          (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
 932
 933 static inline int S_FIXED(float value, unsigned frac_bits)
 934 {
 935         return value * (1 << frac_bits);
 936 }
 937
 938 #endif