src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/u_slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  47 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  48 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  49
  50 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  51 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 1)
  52
  53 /* special primitive types */
  54 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  55
  56 /* Debug flags. */
  57 /* logging */
  58 #define DBG_TEX                 (1 << 0)
  59 /* gap - reuse */
  60 #define DBG_COMPUTE             (1 << 2)
  61 #define DBG_VM                  (1 << 3)
  62 #define DBG_TRACE_CS            (1 << 4)
  63 /* shader logging */
  64 #define DBG_FS                  (1 << 5)
  65 #define DBG_VS                  (1 << 6)
  66 #define DBG_GS                  (1 << 7)
  67 #define DBG_PS                  (1 << 8)
  68 #define DBG_CS                  (1 << 9)
  69 #define DBG_TCS                 (1 << 10)
  70 #define DBG_TES                 (1 << 11)
  71 #define DBG_NO_IR               (1 << 12)
  72 #define DBG_NO_TGSI             (1 << 13)
  73 #define DBG_NO_ASM              (1 << 14)
  74 #define DBG_PREOPT_IR           (1 << 15)
  75 /* Bits 21-31 are reserved for the r600g driver. */
  76 /* features */
  77 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  78 #define DBG_NO_HYPERZ           (1llu << 33)
  79 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  80 #define DBG_NO_2D_TILING        (1llu << 35)
  81 #define DBG_NO_TILING           (1llu << 36)
  82 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  83 #define DBG_FORCE_DMA           (1llu << 38)
  84 #define DBG_PRECOMPILE          (1llu << 39)
  85 #define DBG_INFO                (1llu << 40)
  86 #define DBG_NO_WC               (1llu << 41)
  87 #define DBG_CHECK_VM            (1llu << 42)
  88 #define DBG_NO_DCC              (1llu << 43)
  89 #define DBG_NO_DCC_CLEAR        (1llu << 44)
  90 #define DBG_NO_RB_PLUS          (1llu << 45)
  91 #define DBG_SI_SCHED            (1llu << 46)
  92 #define DBG_MONOLITHIC_SHADERS  (1llu << 47)
  93
  94 #define R600_MAP_BUFFER_ALIGNMENT 64
  95
  96 struct r600_common_context;
  97 struct r600_perfcounters;
  98
  99 struct radeon_shader_reloc {
 100         char name[32];
 101         uint64_t offset;
 102 };
 103
 104 struct radeon_shader_binary {
 105         /** Shader code */
 106         unsigned char *code;
 107         unsigned code_size;
 108
 109         /** Config/Context register state that accompanies this shader.
 110          * This is a stream of dword pairs.  First dword contains the
 111          * register address, the second dword contains the value.*/
 112         unsigned char *config;
 113         unsigned config_size;
 114
 115         /** The number of bytes of config information for each global symbol.
 116          */
 117         unsigned config_size_per_symbol;
 118
 119         /** Constant data accessed by the shader.  This will be uploaded
 120          * into a constant buffer. */
 121         unsigned char *rodata;
 122         unsigned rodata_size;
 123
 124         /** List of symbol offsets for the shader */
 125         uint64_t *global_symbol_offsets;
 126         unsigned global_symbol_count;
 127
 128         struct radeon_shader_reloc *relocs;
 129         unsigned reloc_count;
 130
 131         /** Disassembled shader in a string. */
 132         char *disasm_string;
 133 };
 134
 135 void radeon_shader_binary_init(struct radeon_shader_binary *b);
 136 void radeon_shader_binary_clean(struct radeon_shader_binary *b);
 137
 138 struct r600_resource {
 139         struct u_resource               b;
 140
 141         /* Winsys objects. */
 142         struct pb_buffer                *buf;
 143         uint64_t                        gpu_address;
 144
 145         /* Resource state. */
 146         enum radeon_bo_domain           domains;
 147
 148         /* The buffer range which is initialized (with a write transfer,
 149          * streamout, DMA, or as a random access target). The rest of
 150          * the buffer is considered invalid and can be mapped unsynchronized.
 151          *
 152          * This allows unsychronized mapping of a buffer range which hasn't
 153          * been used yet. It's for applications which forget to use
 154          * the unsynchronized map flag and expect the driver to figure it out.
 155          */
 156         struct util_range               valid_buffer_range;
 157
 158         /* For buffers only. This indicates that a write operation has been
 159          * performed by TC L2, but the cache hasn't been flushed.
 160          * Any hw block which doesn't use or bypasses TC L2 should check this
 161          * flag and flush the cache before using the buffer.
 162          *
 163          * For example, TC L2 must be flushed if a buffer which has been
 164          * modified by a shader store instruction is about to be used as
 165          * an index buffer. The reason is that VGT DMA index fetching doesn't
 166          * use TC L2.
 167          */
 168         bool                            TC_L2_dirty;
 169 };
 170
 171 struct r600_transfer {
 172         struct pipe_transfer            transfer;
 173         struct r600_resource            *staging;
 174         unsigned                        offset;
 175 };
 176
 177 struct r600_fmask_info {
 178         unsigned offset;
 179         unsigned size;
 180         unsigned alignment;
 181         unsigned pitch_in_pixels;
 182         unsigned bank_height;
 183         unsigned slice_tile_max;
 184         unsigned tile_mode_index;
 185 };
 186
 187 struct r600_cmask_info {
 188         unsigned offset;
 189         unsigned size;
 190         unsigned alignment;
 191         unsigned pitch;
 192         unsigned height;
 193         unsigned xalign;
 194         unsigned yalign;
 195         unsigned slice_tile_max;
 196         unsigned base_address_reg;
 197 };
 198
 199 struct r600_htile_info {
 200         unsigned pitch;
 201         unsigned height;
 202         unsigned xalign;
 203         unsigned yalign;
 204 };
 205
 206 struct r600_texture {
 207         struct r600_resource            resource;
 208
 209         unsigned                        size;
 210         bool                            is_depth;
 211         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 212         unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 213         struct r600_texture             *flushed_depth_texture;
 214         boolean                         is_flushing_texture;
 215         struct radeon_surf              surface;
 216
 217         /* Colorbuffer compression and fast clear. */
 218         struct r600_fmask_info          fmask;
 219         struct r600_cmask_info          cmask;
 220         struct r600_resource            *cmask_buffer;
 221         struct r600_resource            *dcc_buffer;
 222         unsigned                        cb_color_info; /* fast clear enable bit */
 223         unsigned                        color_clear_value[2];
 224
 225         /* Depth buffer compression and fast clear. */
 226         struct r600_htile_info          htile;
 227         struct r600_resource            *htile_buffer;
 228         bool                            depth_cleared; /* if it was cleared at least once */
 229         float                           depth_clear_value;
 230         bool                            stencil_cleared; /* if it was cleared at least once */
 231         uint8_t                         stencil_clear_value;
 232
 233         bool                            non_disp_tiling; /* R600-Cayman only */
 234 };
 235
 236 struct r600_surface {
 237         struct pipe_surface             base;
 238
 239         bool color_initialized;
 240         bool depth_initialized;
 241
 242         /* Misc. color flags. */
 243         bool alphatest_bypass;
 244         bool export_16bpc;
 245         bool color_is_int8;
 246
 247         /* Color registers. */
 248         unsigned cb_color_info;
 249         unsigned cb_color_base;
 250         unsigned cb_color_view;
 251         unsigned cb_color_size;         /* R600 only */
 252         unsigned cb_color_dim;          /* EG only */
 253         unsigned cb_color_pitch;        /* EG and later */
 254         unsigned cb_color_slice;        /* EG and later */
 255         unsigned cb_dcc_base;           /* VI and later */
 256         unsigned cb_color_attrib;       /* EG and later */
 257         unsigned cb_dcc_control;        /* VI and later */
 258         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 259         unsigned cb_color_fmask_slice;  /* EG and later */
 260         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 261         unsigned cb_color_mask;         /* R600 only */
 262         unsigned spi_shader_col_format;         /* SI+, no blending, no alpha-to-coverage. */
 263         unsigned spi_shader_col_format_alpha;   /* SI+, alpha-to-coverage */
 264         unsigned spi_shader_col_format_blend;   /* SI+, blending without alpha. */
 265         unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
 266         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 267         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 268
 269         /* DB registers. */
 270         unsigned db_depth_info;         /* R600 only, then SI and later */
 271         unsigned db_z_info;             /* EG and later */
 272         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 273         unsigned db_depth_view;
 274         unsigned db_depth_size;
 275         unsigned db_depth_slice;        /* EG and later */
 276         unsigned db_stencil_base;       /* EG and later */
 277         unsigned db_stencil_info;       /* EG and later */
 278         unsigned db_prefetch_limit;     /* R600 only */
 279         unsigned db_htile_surface;
 280         unsigned db_htile_data_base;
 281         unsigned db_preload_control;    /* EG and later */
 282         unsigned pa_su_poly_offset_db_fmt_cntl;
 283 };
 284
 285 struct r600_common_screen {
 286         struct pipe_screen              b;
 287         struct radeon_winsys            *ws;
 288         enum radeon_family              family;
 289         enum chip_class                 chip_class;
 290         struct radeon_info              info;
 291         uint64_t                        debug_flags;
 292         bool                            has_cp_dma;
 293         bool                            has_streamout;
 294
 295         /* Auxiliary context. Mainly used to initialize resources.
 296          * It must be locked prior to using and flushed before unlocking. */
 297         struct pipe_context             *aux_context;
 298         pipe_mutex                      aux_context_lock;
 299
 300         struct r600_resource            *trace_bo;
 301         uint32_t                        *trace_ptr;
 302         unsigned                        cs_count;
 303
 304         /* This must be in the screen, because UE4 uses one context for
 305          * compilation and another one for rendering.
 306          */
 307         unsigned                        num_compilations;
 308         /* Along with ST_DEBUG=precompile, this should show if applications
 309          * are loading shaders on demand. This is a monotonic counter.
 310          */
 311         unsigned                        num_shaders_created;
 312
 313         /* GPU load thread. */
 314         pipe_mutex                      gpu_load_mutex;
 315         pipe_thread                     gpu_load_thread;
 316         unsigned                        gpu_load_counter_busy;
 317         unsigned                        gpu_load_counter_idle;
 318         volatile unsigned               gpu_load_stop_thread; /* bool */
 319
 320         char                            renderer_string[64];
 321
 322         /* Performance counters. */
 323         struct r600_perfcounters        *perfcounters;
 324 };
 325
 326 /* This encapsulates a state or an operation which can emitted into the GPU
 327  * command stream. */
 328 struct r600_atom {
 329         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 330         unsigned                num_dw;
 331         unsigned short          id;
 332 };
 333
 334 struct r600_so_target {
 335         struct pipe_stream_output_target b;
 336
 337         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 338         struct r600_resource    *buf_filled_size;
 339         unsigned                buf_filled_size_offset;
 340         bool                    buf_filled_size_valid;
 341
 342         unsigned                stride_in_dw;
 343 };
 344
 345 struct r600_streamout {
 346         struct r600_atom                begin_atom;
 347         bool                            begin_emitted;
 348         unsigned                        num_dw_for_end;
 349
 350         unsigned                        enabled_mask;
 351         unsigned                        num_targets;
 352         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 353
 354         unsigned                        append_bitmask;
 355         bool                            suspended;
 356
 357         /* External state which comes from the vertex shader,
 358          * it must be set explicitly when binding a shader. */
 359         unsigned                        *stride_in_dw;
 360         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 361
 362         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 363         unsigned                        hw_enabled_mask;
 364
 365         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 366         struct r600_atom                enable_atom;
 367         bool                            streamout_enabled;
 368         bool                            prims_gen_query_enabled;
 369         int                             num_prims_gen_queries;
 370 };
 371
 372 struct r600_ring {
 373         struct radeon_winsys_cs         *cs;
 374         void (*flush)(void *ctx, unsigned flags,
 375                       struct pipe_fence_handle **fence);
 376 };
 377
 378 struct r600_common_context {
 379         struct pipe_context b; /* base class */
 380
 381         struct r600_common_screen       *screen;
 382         struct radeon_winsys            *ws;
 383         struct radeon_winsys_ctx        *ctx;
 384         enum radeon_family              family;
 385         enum chip_class                 chip_class;
 386         struct r600_ring                gfx;
 387         struct r600_ring                dma;
 388         struct pipe_fence_handle        *last_sdma_fence;
 389         unsigned                        initial_gfx_cs_size;
 390         unsigned                        gpu_reset_counter;
 391
 392         struct u_upload_mgr             *uploader;
 393         struct u_suballocator           *allocator_so_filled_size;
 394         struct util_slab_mempool        pool_transfers;
 395
 396         /* Current unaccounted memory usage. */
 397         uint64_t                        vram;
 398         uint64_t                        gtt;
 399
 400         /* States. */
 401         struct r600_streamout           streamout;
 402
 403         /* Additional context states. */
 404         unsigned flags; /* flush flags */
 405
 406         /* Queries. */
 407         /* The list of active queries. Only one query of each type can be active. */
 408         int                             num_occlusion_queries;
 409         /* Keep track of non-timer queries, because they should be suspended
 410          * during context flushing.
 411          * The timer queries (TIME_ELAPSED) shouldn't be suspended for blits,
 412          * but they should be suspended between IBs. */
 413         struct list_head                active_nontimer_queries;
 414         struct list_head                active_timer_queries;
 415         unsigned                        num_cs_dw_nontimer_queries_suspend;
 416         bool                            nontimer_queries_suspended_by_flush;
 417         unsigned                        num_cs_dw_timer_queries_suspend;
 418         /* Additional hardware info. */
 419         unsigned                        backend_mask;
 420         unsigned                        max_db; /* for OQ */
 421         /* Misc stats. */
 422         unsigned                        num_draw_calls;
 423
 424         /* Render condition. */
 425         struct r600_atom                render_cond_atom;
 426         struct pipe_query               *render_cond;
 427         unsigned                        render_cond_mode;
 428         boolean                         render_cond_invert;
 429         bool                            render_cond_force_off; /* for u_blitter */
 430
 431         /* MSAA sample locations.
 432          * The first index is the sample index.
 433          * The second index is the coordinate: X, Y. */
 434         float                           sample_locations_1x[1][2];
 435         float                           sample_locations_2x[2][2];
 436         float                           sample_locations_4x[4][2];
 437         float                           sample_locations_8x[8][2];
 438         float                           sample_locations_16x[16][2];
 439
 440         /* The list of all texture buffer objects in this context.
 441          * This list is walked when a buffer is invalidated/reallocated and
 442          * the GPU addresses are updated. */
 443         struct list_head                texture_buffers;
 444
 445         struct pipe_debug_callback      debug;
 446
 447         /* Copy one resource to another using async DMA. */
 448         void (*dma_copy)(struct pipe_context *ctx,
 449                          struct pipe_resource *dst,
 450                          unsigned dst_level,
 451                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 452                          struct pipe_resource *src,
 453                          unsigned src_level,
 454                          const struct pipe_box *src_box);
 455
 456         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 457                              unsigned offset, unsigned size, unsigned value,
 458                              bool is_framebuffer);
 459
 460         void (*blit_decompress_depth)(struct pipe_context *ctx,
 461                                       struct r600_texture *texture,
 462                                       struct r600_texture *staging,
 463                                       unsigned first_level, unsigned last_level,
 464                                       unsigned first_layer, unsigned last_layer,
 465                                       unsigned first_sample, unsigned last_sample);
 466
 467         /* Reallocate the buffer and update all resource bindings where
 468          * the buffer is bound, including all resource descriptors. */
 469         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 470
 471         /* Enable or disable occlusion queries. */
 472         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 473
 474         /* This ensures there is enough space in the command stream. */
 475         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 476                                   bool include_draw_vbo);
 477
 478         void (*set_atom_dirty)(struct r600_common_context *ctx,
 479                                struct r600_atom *atom, bool dirty);
 480 };
 481
 482 /* r600_buffer.c */
 483 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 484                                         struct pb_buffer *buf,
 485                                         enum radeon_bo_usage usage);
 486 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 487                                       struct r600_resource *resource,
 488                                       unsigned usage);
 489 bool r600_init_resource(struct r600_common_screen *rscreen,
 490                         struct r600_resource *res,
 491                         unsigned size, unsigned alignment,
 492                         bool use_reusable_pool);
 493 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 494                                          const struct pipe_resource *templ,
 495                                          unsigned alignment);
 496 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
 497                                                   unsigned bind,
 498                                                   unsigned usage,
 499                                                   unsigned size,
 500                                                   unsigned alignment);
 501 struct pipe_resource *
 502 r600_buffer_from_user_memory(struct pipe_screen *screen,
 503                              const struct pipe_resource *templ,
 504                              void *user_memory);
 505 void
 506 r600_invalidate_resource(struct pipe_context *ctx,
 507                          struct pipe_resource *resource);
 508
 509 /* r600_common_pipe.c */
 510 void r600_draw_rectangle(struct blitter_context *blitter,
 511                          int x1, int y1, int x2, int y2, float depth,
 512                          enum blitter_attrib_type type,
 513                          const union pipe_color_union *attrib);
 514 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 515                              struct radeon_winsys *ws);
 516 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 517 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 518 void r600_postflush_resume_features(struct r600_common_context *ctx);
 519 bool r600_common_context_init(struct r600_common_context *rctx,
 520                               struct r600_common_screen *rscreen);
 521 void r600_common_context_cleanup(struct r600_common_context *rctx);
 522 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 523 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 524                           unsigned processor);
 525 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 526                               unsigned offset, unsigned size, unsigned value,
 527                               bool is_framebuffer);
 528 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 529                                                   const struct pipe_resource *templ);
 530 const char *r600_get_llvm_processor_name(enum radeon_family family);
 531 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw);
 532
 533 /* r600_gpu_load.c */
 534 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 535 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
 536 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 537
 538 /* r600_perfcounters.c */
 539 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
 540
 541 /* r600_query.c */
 542 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
 543 void r600_query_init(struct r600_common_context *rctx);
 544 void r600_suspend_nontimer_queries(struct r600_common_context *ctx);
 545 void r600_resume_nontimer_queries(struct r600_common_context *ctx);
 546 void r600_suspend_timer_queries(struct r600_common_context *ctx);
 547 void r600_resume_timer_queries(struct r600_common_context *ctx);
 548 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 549
 550 /* r600_streamout.c */
 551 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 552 void r600_set_streamout_targets(struct pipe_context *ctx,
 553                                 unsigned num_targets,
 554                                 struct pipe_stream_output_target **targets,
 555                                 const unsigned *offset);
 556 void r600_emit_streamout_end(struct r600_common_context *rctx);
 557 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 558                                              unsigned type, int diff);
 559 void r600_streamout_init(struct r600_common_context *rctx);
 560
 561 /* r600_texture.c */
 562 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 563                                  struct r600_texture *rtex,
 564                                  unsigned nr_samples,
 565                                  struct r600_fmask_info *out);
 566 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 567                                  struct r600_texture *rtex,
 568                                  struct r600_cmask_info *out);
 569 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 570                                      struct pipe_resource *texture,
 571                                      struct r600_texture **staging);
 572 void r600_print_texture_info(struct r600_texture *rtex, FILE *f);
 573 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 574                                         const struct pipe_resource *templ);
 575 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 576                                                 struct pipe_resource *texture,
 577                                                 const struct pipe_surface *templ,
 578                                                 unsigned width, unsigned height);
 579 unsigned r600_translate_colorswap(enum pipe_format format);
 580 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 581                                    struct pipe_framebuffer_state *fb,
 582                                    struct r600_atom *fb_state,
 583                                    unsigned *buffers, unsigned *dirty_cbufs,
 584                                    const union pipe_color_union *color);
 585 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 586 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 587
 588 /* cayman_msaa.c */
 589 extern const uint32_t eg_sample_locs_2x[4];
 590 extern const unsigned eg_max_dist_2x;
 591 extern const uint32_t eg_sample_locs_4x[4];
 592 extern const unsigned eg_max_dist_4x;
 593 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 594                                 unsigned sample_index, float *out_value);
 595 void cayman_init_msaa(struct pipe_context *ctx);
 596 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 597 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 598                              int ps_iter_samples, int overrast_samples);
 599
 600
 601 /* Inline helpers. */
 602
 603 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 604 {
 605         return (struct r600_resource*)r;
 606 }
 607
 608 static inline void
 609 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 610 {
 611         pipe_resource_reference((struct pipe_resource **)ptr,
 612                                 (struct pipe_resource *)res);
 613 }
 614
 615 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 616 {
 617         if (filter <= 1)   return 0;
 618         if (filter <= 2)   return 1;
 619         if (filter <= 4)   return 2;
 620         if (filter <= 8)   return 3;
 621          /* else */        return 4;
 622 }
 623
 624 static inline unsigned r600_wavefront_size(enum radeon_family family)
 625 {
 626         switch (family) {
 627         case CHIP_RV610:
 628         case CHIP_RS780:
 629         case CHIP_RV620:
 630         case CHIP_RS880:
 631                 return 16;
 632         case CHIP_RV630:
 633         case CHIP_RV635:
 634         case CHIP_RV730:
 635         case CHIP_RV710:
 636         case CHIP_PALM:
 637         case CHIP_CEDAR:
 638                 return 32;
 639         default:
 640                 return 64;
 641         }
 642 }
 643
 644 static inline enum radeon_bo_priority
 645 r600_get_sampler_view_priority(struct r600_resource *res)
 646 {
 647         if (res->b.b.target == PIPE_BUFFER)
 648                 return RADEON_PRIO_SAMPLER_BUFFER;
 649
 650         if (res->b.b.nr_samples > 1)
 651                 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
 652
 653         return RADEON_PRIO_SAMPLER_TEXTURE;
 654 }
 655
 656 #define COMPUTE_DBG(rscreen, fmt, args...) \
 657         do { \
 658                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 659         } while (0);
 660
 661 #define R600_ERR(fmt, args...) \
 662         fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
 663
 664 /* For MSAA sample positions. */
 665 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 666         (((s0x) & 0xf) | (((s0y) & 0xf) << 4) |            \
 667         (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |     \
 668         (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |    \
 669          (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
 670
 671 #endif