src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "../../winsys/radeon/drm/radeon_winsys.h"
  38
  39 #include "util/u_double_list.h"
  40 #include "util/u_range.h"
  41 #include "util/u_slab.h"
  42 #include "util/u_suballoc.h"
  43 #include "util/u_transfer.h"
  44
  45 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  46 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  47 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  48
  49 #define R600_QUERY_DRAW_CALLS           (PIPE_QUERY_DRIVER_SPECIFIC + 0)
  50 #define R600_QUERY_REQUESTED_VRAM       (PIPE_QUERY_DRIVER_SPECIFIC + 1)
  51 #define R600_QUERY_REQUESTED_GTT        (PIPE_QUERY_DRIVER_SPECIFIC + 2)
  52 #define R600_QUERY_BUFFER_WAIT_TIME     (PIPE_QUERY_DRIVER_SPECIFIC + 3)
  53 #define R600_QUERY_NUM_CS_FLUSHES       (PIPE_QUERY_DRIVER_SPECIFIC + 4)
  54 #define R600_QUERY_NUM_BYTES_MOVED      (PIPE_QUERY_DRIVER_SPECIFIC + 5)
  55 #define R600_QUERY_VRAM_USAGE           (PIPE_QUERY_DRIVER_SPECIFIC + 6)
  56 #define R600_QUERY_GTT_USAGE            (PIPE_QUERY_DRIVER_SPECIFIC + 7)
  57
  58 /* read caches */
  59 #define R600_CONTEXT_INV_VERTEX_CACHE           (1 << 0)
  60 #define R600_CONTEXT_INV_TEX_CACHE              (1 << 1)
  61 #define R600_CONTEXT_INV_CONST_CACHE            (1 << 2)
  62 #define R600_CONTEXT_INV_SHADER_CACHE           (1 << 3)
  63 /* read-write caches */
  64 #define R600_CONTEXT_STREAMOUT_FLUSH            (1 << 8)
  65 #define R600_CONTEXT_FLUSH_AND_INV              (1 << 9)
  66 #define R600_CONTEXT_FLUSH_AND_INV_CB_META      (1 << 10)
  67 #define R600_CONTEXT_FLUSH_AND_INV_DB_META      (1 << 11)
  68 #define R600_CONTEXT_FLUSH_AND_INV_DB           (1 << 12)
  69 #define R600_CONTEXT_FLUSH_AND_INV_CB           (1 << 13)
  70 /* engine synchronization */
  71 #define R600_CONTEXT_PS_PARTIAL_FLUSH           (1 << 16)
  72 #define R600_CONTEXT_WAIT_3D_IDLE               (1 << 17)
  73 #define R600_CONTEXT_WAIT_CP_DMA_IDLE           (1 << 18)
  74 #define R600_CONTEXT_VGT_FLUSH                  (1 << 19)
  75
  76 /* Debug flags. */
  77 /* logging */
  78 #define DBG_TEX                 (1 << 0)
  79 #define DBG_TEXMIP              (1 << 1)
  80 #define DBG_COMPUTE             (1 << 2)
  81 #define DBG_VM                  (1 << 3)
  82 #define DBG_TRACE_CS            (1 << 4)
  83 /* features */
  84 #define DBG_NO_ASYNC_DMA        (1 << 5)
  85 /* shaders */
  86 #define DBG_FS                  (1 << 8)
  87 #define DBG_VS                  (1 << 9)
  88 #define DBG_GS                  (1 << 10)
  89 #define DBG_PS                  (1 << 11)
  90 #define DBG_CS                  (1 << 12)
  91 /* features */
  92 #define DBG_HYPERZ              (1 << 13)
  93 #define DBG_NO_DISCARD_RANGE    (1 << 14)
  94 /* The maximum allowed bit is 15. */
  95
  96 #define R600_MAP_BUFFER_ALIGNMENT 64
  97
  98 struct r600_common_context;
  99
 100 struct radeon_shader_binary {
 101         /** Shader code */
 102         unsigned char *code;
 103         unsigned code_size;
 104
 105         /** Config/Context register state that accompanies this shader.
 106          * This is a stream of dword pairs.  First dword contains the
 107          * register address, the second dword contains the value.*/
 108         unsigned char *config;
 109         unsigned config_size;
 110
 111         /** Set to 1 if the disassembly for this binary has been dumped to
 112          *  stderr. */
 113         int disassembled;
 114 };
 115
 116 struct r600_resource {
 117         struct u_resource               b;
 118
 119         /* Winsys objects. */
 120         struct pb_buffer                *buf;
 121         struct radeon_winsys_cs_handle  *cs_buf;
 122
 123         /* Resource state. */
 124         enum radeon_bo_domain           domains;
 125
 126         /* The buffer range which is initialized (with a write transfer,
 127          * streamout, DMA, or as a random access target). The rest of
 128          * the buffer is considered invalid and can be mapped unsynchronized.
 129          *
 130          * This allows unsychronized mapping of a buffer range which hasn't
 131          * been used yet. It's for applications which forget to use
 132          * the unsynchronized map flag and expect the driver to figure it out.
 133          */
 134         struct util_range               valid_buffer_range;
 135 };
 136
 137 struct r600_transfer {
 138         struct pipe_transfer            transfer;
 139         struct r600_resource            *staging;
 140         unsigned                        offset;
 141 };
 142
 143 struct r600_fmask_info {
 144         unsigned offset;
 145         unsigned size;
 146         unsigned alignment;
 147         unsigned pitch;
 148         unsigned bank_height;
 149         unsigned slice_tile_max;
 150         unsigned tile_mode_index;
 151 };
 152
 153 struct r600_cmask_info {
 154         unsigned offset;
 155         unsigned size;
 156         unsigned alignment;
 157         unsigned slice_tile_max;
 158         unsigned base_address_reg;
 159 };
 160
 161 struct r600_texture {
 162         struct r600_resource            resource;
 163
 164         unsigned                        size;
 165         unsigned                        pitch_override;
 166         bool                            is_depth;
 167         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 168         struct r600_texture             *flushed_depth_texture;
 169         boolean                         is_flushing_texture;
 170         struct radeon_surface           surface;
 171
 172         /* Colorbuffer compression and fast clear. */
 173         struct r600_fmask_info          fmask;
 174         struct r600_cmask_info          cmask;
 175         struct r600_resource            *cmask_buffer;
 176         unsigned                        cb_color_info; /* fast clear enable bit */
 177         unsigned                        color_clear_value[2];
 178
 179         /* Depth buffer compression and fast clear. */
 180         struct r600_resource            *htile_buffer;
 181         float                           depth_clear_value;
 182
 183         bool                            non_disp_tiling; /* R600-Cayman only */
 184         unsigned                        mipmap_shift;
 185 };
 186
 187 struct r600_surface {
 188         struct pipe_surface             base;
 189
 190         bool color_initialized;
 191         bool depth_initialized;
 192
 193         /* Misc. color flags. */
 194         bool alphatest_bypass;
 195         bool export_16bpc;
 196
 197         /* Color registers. */
 198         unsigned cb_color_info;
 199         unsigned cb_color_base;
 200         unsigned cb_color_view;
 201         unsigned cb_color_size;         /* R600 only */
 202         unsigned cb_color_dim;          /* EG only */
 203         unsigned cb_color_pitch;        /* EG and later */
 204         unsigned cb_color_slice;        /* EG and later */
 205         unsigned cb_color_attrib;       /* EG and later */
 206         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 207         unsigned cb_color_fmask_slice;  /* EG and later */
 208         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 209         unsigned cb_color_mask;         /* R600 only */
 210         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 211         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 212
 213         /* DB registers. */
 214         unsigned db_depth_info;         /* R600 only, then SI and later */
 215         unsigned db_z_info;             /* EG and later */
 216         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 217         unsigned db_depth_view;
 218         unsigned db_depth_size;
 219         unsigned db_depth_slice;        /* EG and later */
 220         unsigned db_stencil_base;       /* EG and later */
 221         unsigned db_stencil_info;       /* EG and later */
 222         unsigned db_prefetch_limit;     /* R600 only */
 223         unsigned db_htile_surface;
 224         unsigned db_htile_data_base;
 225         unsigned db_preload_control;    /* EG and later */
 226         unsigned pa_su_poly_offset_db_fmt_cntl;
 227 };
 228
 229 struct r600_tiling_info {
 230         unsigned num_channels;
 231         unsigned num_banks;
 232         unsigned group_bytes;
 233 };
 234
 235 struct r600_common_screen {
 236         struct pipe_screen              b;
 237         struct radeon_winsys            *ws;
 238         enum radeon_family              family;
 239         enum chip_class                 chip_class;
 240         struct radeon_info              info;
 241         struct r600_tiling_info         tiling_info;
 242         unsigned                        debug_flags;
 243         bool                            has_cp_dma;
 244         bool                            has_streamout;
 245
 246         /* Auxiliary context. Mainly used to initialize resources.
 247          * It must be locked prior to using and flushed before unlocking. */
 248         struct pipe_context             *aux_context;
 249         pipe_mutex                      aux_context_lock;
 250
 251         struct r600_resource            *trace_bo;
 252         uint32_t                        *trace_ptr;
 253         unsigned                        cs_count;
 254 };
 255
 256 /* This encapsulates a state or an operation which can emitted into the GPU
 257  * command stream. */
 258 struct r600_atom {
 259         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 260         unsigned                num_dw;
 261         bool                    dirty;
 262 };
 263
 264 struct r600_so_target {
 265         struct pipe_stream_output_target b;
 266
 267         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 268         struct r600_resource    *buf_filled_size;
 269         unsigned                buf_filled_size_offset;
 270
 271         unsigned                stride_in_dw;
 272 };
 273
 274 struct r600_streamout {
 275         struct r600_atom                begin_atom;
 276         bool                            begin_emitted;
 277         unsigned                        num_dw_for_end;
 278
 279         unsigned                        enabled_mask;
 280         unsigned                        num_targets;
 281         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 282
 283         unsigned                        append_bitmask;
 284         bool                            suspended;
 285
 286         /* External state which comes from the vertex shader,
 287          * it must be set explicitly when binding a shader. */
 288         unsigned                        *stride_in_dw;
 289
 290         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 291         struct r600_atom                enable_atom;
 292         bool                            streamout_enabled;
 293         bool                            prims_gen_query_enabled;
 294         int                             num_prims_gen_queries;
 295 };
 296
 297 struct r600_ring {
 298         struct radeon_winsys_cs         *cs;
 299         bool                            flushing;
 300         void (*flush)(void *ctx, unsigned flags,
 301                       struct pipe_fence_handle **fence);
 302 };
 303
 304 struct r600_rings {
 305         struct r600_ring                gfx;
 306         struct r600_ring                dma;
 307 };
 308
 309 struct r600_common_context {
 310         struct pipe_context b; /* base class */
 311
 312         struct r600_common_screen       *screen;
 313         struct radeon_winsys            *ws;
 314         enum radeon_family              family;
 315         enum chip_class                 chip_class;
 316         struct r600_rings               rings;
 317         unsigned                        initial_gfx_cs_size;
 318
 319         struct u_upload_mgr             *uploader;
 320         struct u_suballocator           *allocator_so_filled_size;
 321         struct util_slab_mempool        pool_transfers;
 322
 323         /* Current unaccounted memory usage. */
 324         uint64_t                        vram;
 325         uint64_t                        gtt;
 326
 327         /* States. */
 328         struct r600_streamout           streamout;
 329
 330         /* Additional context states. */
 331         unsigned flags; /* flush flags */
 332
 333         /* Queries. */
 334         /* The list of active queries. Only one query of each type can be active. */
 335         int                             num_occlusion_queries;
 336         int                             num_pipelinestat_queries;
 337         /* Keep track of non-timer queries, because they should be suspended
 338          * during context flushing.
 339          * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
 340         struct list_head                active_nontimer_queries;
 341         unsigned                        num_cs_dw_nontimer_queries_suspend;
 342         /* If queries have been suspended. */
 343         bool                            nontimer_queries_suspended;
 344         /* Additional hardware info. */
 345         unsigned                        backend_mask;
 346         unsigned                        max_db; /* for OQ */
 347         /* Misc stats. */
 348         unsigned                        num_draw_calls;
 349
 350         /* Render condition. */
 351         struct pipe_query               *current_render_cond;
 352         unsigned                        current_render_cond_mode;
 353         boolean                         current_render_cond_cond;
 354         boolean                         predicate_drawing;
 355         /* For context flushing. */
 356         struct pipe_query               *saved_render_cond;
 357         boolean                         saved_render_cond_cond;
 358         unsigned                        saved_render_cond_mode;
 359
 360         /* Copy one resource to another using async DMA. */
 361         void (*dma_copy)(struct pipe_context *ctx,
 362                          struct pipe_resource *dst,
 363                          unsigned dst_level,
 364                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 365                          struct pipe_resource *src,
 366                          unsigned src_level,
 367                          const struct pipe_box *src_box);
 368
 369         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 370                              unsigned offset, unsigned size, unsigned value);
 371
 372         void (*blit_decompress_depth)(struct pipe_context *ctx,
 373                                       struct r600_texture *texture,
 374                                       struct r600_texture *staging,
 375                                       unsigned first_level, unsigned last_level,
 376                                       unsigned first_layer, unsigned last_layer,
 377                                       unsigned first_sample, unsigned last_sample);
 378
 379         /* Reallocate the buffer and update all resource bindings where
 380          * the buffer is bound, including all resource descriptors. */
 381         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 382
 383         /* Enable or disable occlusion queries. */
 384         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 385
 386         /* This ensures there is enough space in the command stream. */
 387         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 388                                   bool include_draw_vbo);
 389 };
 390
 391 /* r600_buffer.c */
 392 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 393                                         struct radeon_winsys_cs_handle *buf,
 394                                         enum radeon_bo_usage usage);
 395 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 396                                       struct r600_resource *resource,
 397                                       unsigned usage);
 398 bool r600_init_resource(struct r600_common_screen *rscreen,
 399                         struct r600_resource *res,
 400                         unsigned size, unsigned alignment,
 401                         bool use_reusable_pool);
 402 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 403                                          const struct pipe_resource *templ,
 404                                          unsigned alignment);
 405
 406 /* r600_common_pipe.c */
 407 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 408                              struct radeon_winsys *ws);
 409 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 410 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 411 void r600_postflush_resume_features(struct r600_common_context *ctx);
 412 bool r600_common_context_init(struct r600_common_context *rctx,
 413                               struct r600_common_screen *rscreen);
 414 void r600_common_context_cleanup(struct r600_common_context *rctx);
 415 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 416 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 417                           const struct tgsi_token *tokens);
 418 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 419                               unsigned offset, unsigned size, unsigned value);
 420 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 421                                                   const struct pipe_resource *templ);
 422 const char *r600_get_llvm_processor_name(enum radeon_family family);
 423 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw);
 424
 425 /* r600_query.c */
 426 void r600_query_init(struct r600_common_context *rctx);
 427 void r600_suspend_nontimer_queries(struct r600_common_context *ctx);
 428 void r600_resume_nontimer_queries(struct r600_common_context *ctx);
 429 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 430
 431 /* r600_streamout.c */
 432 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 433 void r600_set_streamout_targets(struct pipe_context *ctx,
 434                                 unsigned num_targets,
 435                                 struct pipe_stream_output_target **targets,
 436                                 const unsigned *offset);
 437 void r600_emit_streamout_end(struct r600_common_context *rctx);
 438 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 439                                              unsigned type, int diff);
 440 void r600_streamout_init(struct r600_common_context *rctx);
 441
 442 /* r600_texture.c */
 443 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 444                                  struct r600_texture *rtex,
 445                                  unsigned nr_samples,
 446                                  struct r600_fmask_info *out);
 447 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 448                                  struct r600_texture *rtex,
 449                                  struct r600_cmask_info *out);
 450 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 451                                      struct pipe_resource *texture,
 452                                      struct r600_texture **staging);
 453 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 454                                         const struct pipe_resource *templ);
 455 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 456                                                 struct pipe_resource *texture,
 457                                                 const struct pipe_surface *templ,
 458                                                 unsigned width, unsigned height);
 459 unsigned r600_translate_colorswap(enum pipe_format format);
 460 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 461                                    struct pipe_framebuffer_state *fb,
 462                                    struct r600_atom *fb_state,
 463                                    unsigned *buffers,
 464                                    const union pipe_color_union *color);
 465 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 466 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 467
 468 /* cayman_msaa.c */
 469 extern const uint32_t eg_sample_locs_2x[4];
 470 extern const unsigned eg_max_dist_2x;
 471 extern const uint32_t eg_sample_locs_4x[4];
 472 extern const unsigned eg_max_dist_4x;
 473 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 474                                 unsigned sample_index, float *out_value);
 475 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 476 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 477                              int ps_iter_samples);
 478
 479
 480 /* Inline helpers. */
 481
 482 static INLINE struct r600_resource *r600_resource(struct pipe_resource *r)
 483 {
 484         return (struct r600_resource*)r;
 485 }
 486
 487 static INLINE void
 488 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 489 {
 490         pipe_resource_reference((struct pipe_resource **)ptr,
 491                                 (struct pipe_resource *)res);
 492 }
 493
 494 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 495 {
 496         if (filter <= 1)   return 0;
 497         if (filter <= 2)   return 1;
 498         if (filter <= 4)   return 2;
 499         if (filter <= 8)   return 3;
 500          /* else */        return 4;
 501 }
 502
 503 #define R600_ERR(fmt, args...) \
 504         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
 505
 506 /* For MSAA sample positions. */
 507 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 508         (((s0x) & 0xf) | (((s0y) & 0xf) << 4) |            \
 509         (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |     \
 510         (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |    \
 511          (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
 512
 513 #endif