2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
37 #include "amd/common/ac_binary.h"
39 #include "radeon/radeon_winsys.h"
41 #include "util/disk_cache.h"
42 #include "util/u_blitter.h"
43 #include "util/list.h"
44 #include "util/u_range.h"
45 #include "util/slab.h"
46 #include "util/u_suballoc.h"
47 #include "util/u_transfer.h"
48 #include "util/u_threaded_context.h"
52 #define ATI_VENDOR_ID 0x1002
54 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
55 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
56 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
57 #define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
58 #define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
60 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
61 /* Pipeline & streamout query controls. */
62 #define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
63 #define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
64 #define R600_CONTEXT_PRIVATE_FLAG (1u << 3)
66 /* special primitive types */
67 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
70 /* logging and features */
71 #define DBG_TEX (1 << 0)
72 #define DBG_NIR (1 << 1)
73 #define DBG_COMPUTE (1 << 2)
74 #define DBG_VM (1 << 3)
77 #define DBG_FS (1 << 5)
78 #define DBG_VS (1 << 6)
79 #define DBG_GS (1 << 7)
80 #define DBG_PS (1 << 8)
81 #define DBG_CS (1 << 9)
82 #define DBG_TCS (1 << 10)
83 #define DBG_TES (1 << 11)
84 #define DBG_NO_IR (1 << 12)
85 #define DBG_NO_TGSI (1 << 13)
86 #define DBG_NO_ASM (1 << 14)
87 #define DBG_PREOPT_IR (1 << 15)
88 #define DBG_CHECK_IR (1 << 16)
89 #define DBG_NO_OPT_VARIANT (1 << 17)
90 #define DBG_FS_CORRECT_DERIVS_AFTER_KILL (1 << 18)
92 #define DBG_TEST_DMA (1 << 20)
93 /* Bits 21-31 are reserved for the r600g driver. */
95 #define DBG_NO_ASYNC_DMA (1ull << 32)
96 #define DBG_NO_HYPERZ (1ull << 33)
97 #define DBG_NO_DISCARD_RANGE (1ull << 34)
98 #define DBG_NO_2D_TILING (1ull << 35)
99 #define DBG_NO_TILING (1ull << 36)
100 #define DBG_SWITCH_ON_EOP (1ull << 37)
101 #define DBG_FORCE_DMA (1ull << 38)
102 #define DBG_PRECOMPILE (1ull << 39)
103 #define DBG_INFO (1ull << 40)
104 #define DBG_NO_WC (1ull << 41)
105 #define DBG_CHECK_VM (1ull << 42)
106 #define DBG_NO_DCC (1ull << 43)
107 #define DBG_NO_DCC_CLEAR (1ull << 44)
108 #define DBG_NO_RB_PLUS (1ull << 45)
109 #define DBG_SI_SCHED (1ull << 46)
110 #define DBG_MONOLITHIC_SHADERS (1ull << 47)
112 #define DBG_UNSAFE_MATH (1ull << 49)
113 #define DBG_NO_DCC_FB (1ull << 50)
114 #define DBG_TEST_VMFAULT_CP (1ull << 51)
115 #define DBG_TEST_VMFAULT_SDMA (1ull << 52)
116 #define DBG_TEST_VMFAULT_SHADER (1ull << 53)
118 #define R600_MAP_BUFFER_ALIGNMENT 64
119 #define R600_MAX_VIEWPORTS 16
121 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
123 enum r600_coherency
{
124 R600_COHERENCY_NONE
, /* no cache flushes needed */
125 R600_COHERENCY_SHADER
,
126 R600_COHERENCY_CB_META
,
129 #ifdef PIPE_ARCH_BIG_ENDIAN
130 #define R600_BIG_ENDIAN 1
132 #define R600_BIG_ENDIAN 0
135 struct r600_common_context
;
136 struct r600_perfcounters
;
137 struct tgsi_shader_info
;
138 struct r600_qbo_state
;
140 void radeon_shader_binary_init(struct ac_shader_binary
*b
);
141 void radeon_shader_binary_clean(struct ac_shader_binary
*b
);
143 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
146 struct r600_resource
{
147 struct threaded_resource b
;
149 /* Winsys objects. */
150 struct pb_buffer
*buf
;
151 uint64_t gpu_address
;
152 /* Memory usage if the buffer placement is optimal. */
156 /* Resource properties. */
158 unsigned bo_alignment
;
159 enum radeon_bo_domain domains
;
160 enum radeon_bo_flag flags
;
161 unsigned bind_history
;
163 /* The buffer range which is initialized (with a write transfer,
164 * streamout, DMA, or as a random access target). The rest of
165 * the buffer is considered invalid and can be mapped unsynchronized.
167 * This allows unsychronized mapping of a buffer range which hasn't
168 * been used yet. It's for applications which forget to use
169 * the unsynchronized map flag and expect the driver to figure it out.
171 struct util_range valid_buffer_range
;
173 /* For buffers only. This indicates that a write operation has been
174 * performed by TC L2, but the cache hasn't been flushed.
175 * Any hw block which doesn't use or bypasses TC L2 should check this
176 * flag and flush the cache before using the buffer.
178 * For example, TC L2 must be flushed if a buffer which has been
179 * modified by a shader store instruction is about to be used as
180 * an index buffer. The reason is that VGT DMA index fetching doesn't
185 /* Whether the resource has been exported via resource_get_handle. */
186 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
188 /* Whether this resource is referenced by bindless handles. */
189 bool texture_handle_allocated
;
190 bool image_handle_allocated
;
193 struct r600_transfer
{
194 struct threaded_transfer b
;
195 struct r600_resource
*staging
;
199 struct r600_fmask_info
{
203 unsigned pitch_in_pixels
;
204 unsigned bank_height
;
205 unsigned slice_tile_max
;
206 unsigned tile_mode_index
;
207 unsigned tile_swizzle
;
210 struct r600_cmask_info
{
214 unsigned slice_tile_max
;
215 uint64_t base_address_reg
;
218 struct r600_texture
{
219 struct r600_resource resource
;
222 unsigned num_level0_transfers
;
223 enum pipe_format db_render_format
;
228 unsigned dirty_level_mask
; /* each bit says if that mipmap is compressed */
229 unsigned stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
230 struct r600_texture
*flushed_depth_texture
;
231 struct radeon_surf surface
;
233 /* Colorbuffer compression and fast clear. */
234 struct r600_fmask_info fmask
;
235 struct r600_cmask_info cmask
;
236 struct r600_resource
*cmask_buffer
;
237 uint64_t dcc_offset
; /* 0 = disabled */
238 unsigned cb_color_info
; /* fast clear enable bit */
239 unsigned color_clear_value
[2];
240 unsigned last_msaa_resolve_target_micro_mode
;
242 /* Depth buffer compression and fast clear. */
243 uint64_t htile_offset
;
244 bool tc_compatible_htile
;
245 bool depth_cleared
; /* if it was cleared at least once */
246 float depth_clear_value
;
247 bool stencil_cleared
; /* if it was cleared at least once */
248 uint8_t stencil_clear_value
;
250 bool non_disp_tiling
; /* R600-Cayman only */
252 /* Whether the texture is a displayable back buffer and needs DCC
253 * decompression, which is expensive. Therefore, it's enabled only
254 * if statistics suggest that it will pay off and it's allocated
255 * separately. It can't be bound as a sampler by apps. Limited to
256 * target == 2D and last_level == 0. If enabled, dcc_offset contains
257 * the absolute GPUVM address, not the relative one.
259 struct r600_resource
*dcc_separate_buffer
;
260 /* When DCC is temporarily disabled, the separate buffer is here. */
261 struct r600_resource
*last_dcc_separate_buffer
;
262 /* We need to track DCC dirtiness, because st/dri usually calls
263 * flush_resource twice per frame (not a bug) and we don't wanna
264 * decompress DCC twice. Also, the dirty tracking must be done even
265 * if DCC isn't used, because it's required by the DCC usage analysis
266 * for a possible future enablement.
268 bool separate_dcc_dirty
;
269 /* Statistics gathering for the DCC enablement heuristic. */
270 bool dcc_gather_statistics
;
271 /* Estimate of how much this color buffer is written to in units of
272 * full-screen draws: ps_invocations / (width * height)
273 * Shader kills, late Z, and blending with trivial discards make it
274 * inaccurate (we need to count CB updates, not PS invocations).
276 unsigned ps_draw_ratio
;
277 /* The number of clears since the last DCC usage analysis. */
278 unsigned num_slow_clears
;
280 /* Counter that should be non-zero if the texture is bound to a
281 * framebuffer. Implemented in radeonsi only.
283 uint32_t framebuffers_bound
;
286 struct r600_surface
{
287 struct pipe_surface base
;
289 /* These can vary with block-compressed textures. */
293 bool color_initialized
;
294 bool depth_initialized
;
296 /* Misc. color flags. */
297 bool alphatest_bypass
;
301 bool dcc_incompatible
;
303 /* Color registers. */
304 unsigned cb_color_info
;
305 unsigned cb_color_base
;
306 unsigned cb_color_view
;
307 unsigned cb_color_size
; /* R600 only */
308 unsigned cb_color_dim
; /* EG only */
309 unsigned cb_color_pitch
; /* EG and later */
310 unsigned cb_color_slice
; /* EG and later */
311 unsigned cb_color_attrib
; /* EG and later */
312 unsigned cb_color_attrib2
; /* GFX9 and later */
313 unsigned cb_dcc_control
; /* VI and later */
314 unsigned cb_color_fmask
; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
315 unsigned cb_color_fmask_slice
; /* EG and later */
316 unsigned cb_color_cmask
; /* CB_COLORn_TILE (r600 only) */
317 unsigned cb_color_mask
; /* R600 only */
318 unsigned spi_shader_col_format
; /* SI+, no blending, no alpha-to-coverage. */
319 unsigned spi_shader_col_format_alpha
; /* SI+, alpha-to-coverage */
320 unsigned spi_shader_col_format_blend
; /* SI+, blending without alpha. */
321 unsigned spi_shader_col_format_blend_alpha
; /* SI+, blending with alpha. */
322 struct r600_resource
*cb_buffer_fmask
; /* Used for FMASK relocations. R600 only */
323 struct r600_resource
*cb_buffer_cmask
; /* Used for CMASK relocations. R600 only */
326 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
327 uint64_t db_stencil_base
; /* EG and later */
328 uint64_t db_htile_data_base
;
329 unsigned db_depth_info
; /* R600 only, then SI and later */
330 unsigned db_z_info
; /* EG and later */
331 unsigned db_z_info2
; /* GFX9+ */
332 unsigned db_depth_view
;
333 unsigned db_depth_size
;
334 unsigned db_depth_slice
; /* EG and later */
335 unsigned db_stencil_info
; /* EG and later */
336 unsigned db_stencil_info2
; /* GFX9+ */
337 unsigned db_prefetch_limit
; /* R600 only */
338 unsigned db_htile_surface
;
339 unsigned db_preload_control
; /* EG and later */
342 struct r600_mmio_counter
{
347 union r600_mmio_counters
{
349 /* For global GPU load including SDMA. */
350 struct r600_mmio_counter gpu
;
353 struct r600_mmio_counter spi
;
354 struct r600_mmio_counter gui
;
355 struct r600_mmio_counter ta
;
356 struct r600_mmio_counter gds
;
357 struct r600_mmio_counter vgt
;
358 struct r600_mmio_counter ia
;
359 struct r600_mmio_counter sx
;
360 struct r600_mmio_counter wd
;
361 struct r600_mmio_counter bci
;
362 struct r600_mmio_counter sc
;
363 struct r600_mmio_counter pa
;
364 struct r600_mmio_counter db
;
365 struct r600_mmio_counter cp
;
366 struct r600_mmio_counter cb
;
369 struct r600_mmio_counter sdma
;
372 struct r600_mmio_counter pfp
;
373 struct r600_mmio_counter meq
;
374 struct r600_mmio_counter me
;
375 struct r600_mmio_counter surf_sync
;
376 struct r600_mmio_counter cp_dma
;
377 struct r600_mmio_counter scratch_ram
;
382 struct r600_memory_object
{
383 struct pipe_memory_object b
;
384 struct pb_buffer
*buf
;
389 struct r600_common_screen
{
390 struct pipe_screen b
;
391 struct radeon_winsys
*ws
;
392 enum radeon_family family
;
393 enum chip_class chip_class
;
394 struct radeon_info info
;
395 uint64_t debug_flags
;
398 bool has_rbplus
; /* if RB+ registers exist */
399 bool rbplus_allowed
; /* if RB+ is allowed */
401 struct disk_cache
*disk_shader_cache
;
403 struct slab_parent_pool pool_transfers
;
405 /* Texture filter settings. */
406 int force_aniso
; /* -1 = disabled */
408 /* Auxiliary context. Mainly used to initialize resources.
409 * It must be locked prior to using and flushed before unlocking. */
410 struct pipe_context
*aux_context
;
411 mtx_t aux_context_lock
;
413 /* This must be in the screen, because UE4 uses one context for
414 * compilation and another one for rendering.
416 unsigned num_compilations
;
417 /* Along with ST_DEBUG=precompile, this should show if applications
418 * are loading shaders on demand. This is a monotonic counter.
420 unsigned num_shaders_created
;
421 unsigned num_shader_cache_hits
;
423 /* GPU load thread. */
424 mtx_t gpu_load_mutex
;
425 thrd_t gpu_load_thread
;
426 union r600_mmio_counters mmio_counters
;
427 volatile unsigned gpu_load_stop_thread
; /* bool */
429 char renderer_string
[100];
431 /* Performance counters. */
432 struct r600_perfcounters
*perfcounters
;
434 /* If pipe_screen wants to recompute and re-emit the framebuffer,
435 * sampler, and image states of all contexts, it should atomically
438 * Each context will compare this with its own last known value of
439 * the counter before drawing and re-emit the states accordingly.
441 unsigned dirty_tex_counter
;
443 /* Atomically increment this counter when an existing texture's
444 * metadata is enabled or disabled in a way that requires changing
445 * contexts' compressed texture binding masks.
447 unsigned compressed_colortex_counter
;
450 /* Context flags to set so that all writes from earlier jobs
451 * in the CP are seen by L2 clients.
455 /* Context flags to set so that all writes from earlier
456 * compute jobs are seen by L2 clients.
458 unsigned compute_to_L2
;
461 void (*query_opaque_metadata
)(struct r600_common_screen
*rscreen
,
462 struct r600_texture
*rtex
,
463 struct radeon_bo_metadata
*md
);
465 void (*apply_opaque_metadata
)(struct r600_common_screen
*rscreen
,
466 struct r600_texture
*rtex
,
467 struct radeon_bo_metadata
*md
);
470 /* This encapsulates a state or an operation which can emitted into the GPU
473 void (*emit
)(struct r600_common_context
*ctx
, struct r600_atom
*state
);
478 struct r600_so_target
{
479 struct pipe_stream_output_target b
;
481 /* The buffer where BUFFER_FILLED_SIZE is stored. */
482 struct r600_resource
*buf_filled_size
;
483 unsigned buf_filled_size_offset
;
484 bool buf_filled_size_valid
;
486 unsigned stride_in_dw
;
489 struct r600_streamout
{
490 struct r600_atom begin_atom
;
492 unsigned num_dw_for_end
;
494 unsigned enabled_mask
;
495 unsigned num_targets
;
496 struct r600_so_target
*targets
[PIPE_MAX_SO_BUFFERS
];
498 unsigned append_bitmask
;
501 /* External state which comes from the vertex shader,
502 * it must be set explicitly when binding a shader. */
503 uint16_t *stride_in_dw
;
504 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
506 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
507 unsigned hw_enabled_mask
;
509 /* The state of VGT_STRMOUT_(CONFIG|EN). */
510 struct r600_atom enable_atom
;
511 bool streamout_enabled
;
512 bool prims_gen_query_enabled
;
513 int num_prims_gen_queries
;
516 struct r600_signed_scissor
{
523 struct r600_scissors
{
524 struct r600_atom atom
;
526 struct pipe_scissor_state states
[R600_MAX_VIEWPORTS
];
529 struct r600_viewports
{
530 struct r600_atom atom
;
532 unsigned depth_range_dirty_mask
;
533 struct pipe_viewport_state states
[R600_MAX_VIEWPORTS
];
534 struct r600_signed_scissor as_scissor
[R600_MAX_VIEWPORTS
];
538 struct radeon_winsys_cs
*cs
;
539 void (*flush
)(void *ctx
, unsigned flags
,
540 struct pipe_fence_handle
**fence
);
543 /* Saved CS data for debugging features. */
544 struct radeon_saved_cs
{
548 struct radeon_bo_list_item
*bo_list
;
552 struct r600_common_context
{
553 struct pipe_context b
; /* base class */
555 struct r600_common_screen
*screen
;
556 struct radeon_winsys
*ws
;
557 struct radeon_winsys_ctx
*ctx
;
558 enum radeon_family family
;
559 enum chip_class chip_class
;
560 struct r600_ring gfx
;
561 struct r600_ring dma
;
562 struct pipe_fence_handle
*last_gfx_fence
;
563 struct pipe_fence_handle
*last_sdma_fence
;
564 struct r600_resource
*eop_bug_scratch
;
565 unsigned num_gfx_cs_flushes
;
566 unsigned initial_gfx_cs_size
;
567 unsigned gpu_reset_counter
;
568 unsigned last_dirty_tex_counter
;
569 unsigned last_compressed_colortex_counter
;
571 struct threaded_context
*tc
;
572 struct u_suballocator
*allocator_zeroed_memory
;
573 struct slab_child_pool pool_transfers
;
574 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
576 /* Current unaccounted memory usage. */
581 struct r600_streamout streamout
;
582 struct r600_scissors scissors
;
583 struct r600_viewports viewports
;
584 bool scissor_enabled
;
586 bool vs_writes_viewport_index
;
587 bool vs_disables_clipping_viewport
;
589 /* Additional context states. */
590 unsigned flags
; /* flush flags */
593 /* Maintain the list of active queries for pausing between IBs. */
594 int num_occlusion_queries
;
595 int num_perfect_occlusion_queries
;
596 struct list_head active_queries
;
597 unsigned num_cs_dw_queries_suspend
;
599 unsigned num_draw_calls
;
600 unsigned num_decompress_calls
;
601 unsigned num_mrt_draw_calls
;
602 unsigned num_prim_restart_calls
;
603 unsigned num_spill_draw_calls
;
604 unsigned num_compute_calls
;
605 unsigned num_spill_compute_calls
;
606 unsigned num_dma_calls
;
607 unsigned num_cp_dma_calls
;
608 unsigned num_vs_flushes
;
609 unsigned num_ps_flushes
;
610 unsigned num_cs_flushes
;
611 unsigned num_cb_cache_flushes
;
612 unsigned num_db_cache_flushes
;
613 unsigned num_L2_invalidates
;
614 unsigned num_L2_writebacks
;
615 unsigned num_resident_handles
;
616 uint64_t num_alloc_tex_transfer_bytes
;
617 unsigned last_tex_ps_draw_ratio
; /* for query */
619 /* Render condition. */
620 struct r600_atom render_cond_atom
;
621 struct pipe_query
*render_cond
;
622 unsigned render_cond_mode
;
623 bool render_cond_invert
;
624 bool render_cond_force_off
; /* for u_blitter */
626 /* MSAA sample locations.
627 * The first index is the sample index.
628 * The second index is the coordinate: X, Y. */
629 float sample_locations_1x
[1][2];
630 float sample_locations_2x
[2][2];
631 float sample_locations_4x
[4][2];
632 float sample_locations_8x
[8][2];
633 float sample_locations_16x
[16][2];
635 /* Statistics gathering for the DCC enablement heuristic. It can't be
636 * in r600_texture because r600_texture can be shared by multiple
637 * contexts. This is for back buffers only. We shouldn't get too many
640 * X11 DRI3 rotates among a finite set of back buffers. They should
641 * all fit in this array. If they don't, separate DCC might never be
642 * enabled by DCC stat gathering.
645 struct r600_texture
*tex
;
646 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
647 struct pipe_query
*ps_stats
[3];
648 /* If all slots are used and another slot is needed,
649 * the least recently used slot is evicted based on this. */
650 int64_t last_use_timestamp
;
654 struct pipe_debug_callback debug
;
655 struct pipe_device_reset_callback device_reset_callback
;
656 struct u_log_context
*log
;
658 void *query_result_shader
;
660 /* Copy one resource to another using async DMA. */
661 void (*dma_copy
)(struct pipe_context
*ctx
,
662 struct pipe_resource
*dst
,
664 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
665 struct pipe_resource
*src
,
667 const struct pipe_box
*src_box
);
669 void (*dma_clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
670 uint64_t offset
, uint64_t size
, unsigned value
);
672 void (*clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
673 uint64_t offset
, uint64_t size
, unsigned value
,
674 enum r600_coherency coher
);
676 void (*blit_decompress_depth
)(struct pipe_context
*ctx
,
677 struct r600_texture
*texture
,
678 struct r600_texture
*staging
,
679 unsigned first_level
, unsigned last_level
,
680 unsigned first_layer
, unsigned last_layer
,
681 unsigned first_sample
, unsigned last_sample
);
683 void (*decompress_dcc
)(struct pipe_context
*ctx
,
684 struct r600_texture
*rtex
);
686 /* Reallocate the buffer and update all resource bindings where
687 * the buffer is bound, including all resource descriptors. */
688 void (*invalidate_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
);
690 /* Update all resource bindings where the buffer is bound, including
691 * all resource descriptors. This is invalidate_buffer without
692 * the invalidation. */
693 void (*rebind_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
694 uint64_t old_gpu_address
);
696 /* Enable or disable occlusion queries. */
697 void (*set_occlusion_query_state
)(struct pipe_context
*ctx
, bool enable
);
699 void (*save_qbo_state
)(struct pipe_context
*ctx
, struct r600_qbo_state
*st
);
701 /* This ensures there is enough space in the command stream. */
702 void (*need_gfx_cs_space
)(struct pipe_context
*ctx
, unsigned num_dw
,
703 bool include_draw_vbo
);
705 void (*set_atom_dirty
)(struct r600_common_context
*ctx
,
706 struct r600_atom
*atom
, bool dirty
);
708 void (*check_vm_faults
)(struct r600_common_context
*ctx
,
709 struct radeon_saved_cs
*saved
,
710 enum ring_type ring
);
713 /* r600_buffer_common.c */
714 bool r600_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
715 struct pb_buffer
*buf
,
716 enum radeon_bo_usage usage
);
717 void *r600_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
718 struct r600_resource
*resource
,
720 void r600_buffer_subdata(struct pipe_context
*ctx
,
721 struct pipe_resource
*buffer
,
722 unsigned usage
, unsigned offset
,
723 unsigned size
, const void *data
);
724 void r600_init_resource_fields(struct r600_common_screen
*rscreen
,
725 struct r600_resource
*res
,
726 uint64_t size
, unsigned alignment
);
727 bool r600_alloc_resource(struct r600_common_screen
*rscreen
,
728 struct r600_resource
*res
);
729 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
730 const struct pipe_resource
*templ
,
732 struct pipe_resource
* r600_aligned_buffer_create(struct pipe_screen
*screen
,
737 struct pipe_resource
*
738 r600_buffer_from_user_memory(struct pipe_screen
*screen
,
739 const struct pipe_resource
*templ
,
742 r600_invalidate_resource(struct pipe_context
*ctx
,
743 struct pipe_resource
*resource
);
744 void r600_replace_buffer_storage(struct pipe_context
*ctx
,
745 struct pipe_resource
*dst
,
746 struct pipe_resource
*src
);
748 /* r600_common_pipe.c */
749 void r600_gfx_write_event_eop(struct r600_common_context
*ctx
,
750 unsigned event
, unsigned event_flags
,
752 struct r600_resource
*buf
, uint64_t va
,
753 uint32_t new_fence
, unsigned query_type
);
754 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen
*screen
);
755 void r600_gfx_wait_fence(struct r600_common_context
*ctx
,
756 uint64_t va
, uint32_t ref
, uint32_t mask
);
757 void r600_draw_rectangle(struct blitter_context
*blitter
,
758 int x1
, int y1
, int x2
, int y2
, float depth
,
759 enum blitter_attrib_type type
,
760 const union pipe_color_union
*attrib
);
761 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
762 struct radeon_winsys
*ws
);
763 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
);
764 void r600_preflush_suspend_features(struct r600_common_context
*ctx
);
765 void r600_postflush_resume_features(struct r600_common_context
*ctx
);
766 bool r600_common_context_init(struct r600_common_context
*rctx
,
767 struct r600_common_screen
*rscreen
,
768 unsigned context_flags
);
769 void r600_common_context_cleanup(struct r600_common_context
*rctx
);
770 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
772 bool r600_extra_shader_checks(struct r600_common_screen
*rscreen
,
774 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
775 uint64_t offset
, uint64_t size
, unsigned value
);
776 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
777 const struct pipe_resource
*templ
);
778 const char *r600_get_llvm_processor_name(enum radeon_family family
);
779 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
,
780 struct r600_resource
*dst
, struct r600_resource
*src
);
781 void radeon_save_cs(struct radeon_winsys
*ws
, struct radeon_winsys_cs
*cs
,
782 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
783 void radeon_clear_saved_cs(struct radeon_saved_cs
*saved
);
784 bool r600_check_device_reset(struct r600_common_context
*rctx
);
786 /* r600_gpu_load.c */
787 void r600_gpu_load_kill_thread(struct r600_common_screen
*rscreen
);
788 uint64_t r600_begin_counter(struct r600_common_screen
*rscreen
, unsigned type
);
789 unsigned r600_end_counter(struct r600_common_screen
*rscreen
, unsigned type
,
792 /* r600_perfcounters.c */
793 void r600_perfcounters_destroy(struct r600_common_screen
*rscreen
);
796 void r600_init_screen_query_functions(struct r600_common_screen
*rscreen
);
797 void r600_query_init(struct r600_common_context
*rctx
);
798 void r600_suspend_queries(struct r600_common_context
*ctx
);
799 void r600_resume_queries(struct r600_common_context
*ctx
);
800 void r600_query_fix_enabled_rb_mask(struct r600_common_screen
*rscreen
);
802 /* r600_streamout.c */
803 void r600_streamout_buffers_dirty(struct r600_common_context
*rctx
);
804 void r600_set_streamout_targets(struct pipe_context
*ctx
,
805 unsigned num_targets
,
806 struct pipe_stream_output_target
**targets
,
807 const unsigned *offset
);
808 void r600_emit_streamout_end(struct r600_common_context
*rctx
);
809 void r600_update_prims_generated_query_state(struct r600_common_context
*rctx
,
810 unsigned type
, int diff
);
811 void r600_streamout_init(struct r600_common_context
*rctx
);
813 /* r600_test_dma.c */
814 void r600_test_dma(struct r600_common_screen
*rscreen
);
817 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
818 struct r600_texture
*rdst
,
819 unsigned dst_level
, unsigned dstx
,
820 unsigned dsty
, unsigned dstz
,
821 struct r600_texture
*rsrc
,
823 const struct pipe_box
*src_box
);
824 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
825 struct r600_texture
*rtex
,
827 struct r600_fmask_info
*out
);
828 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
829 struct r600_texture
*rtex
,
830 struct r600_cmask_info
*out
);
831 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
832 struct pipe_resource
*texture
,
833 struct r600_texture
**staging
);
834 void r600_print_texture_info(struct r600_common_screen
*rscreen
,
835 struct r600_texture
*rtex
, struct u_log_context
*log
);
836 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
837 const struct pipe_resource
*templ
);
838 bool vi_dcc_formats_compatible(enum pipe_format format1
,
839 enum pipe_format format2
);
840 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
842 enum pipe_format view_format
);
843 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
844 struct pipe_resource
*tex
,
846 enum pipe_format view_format
);
847 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
848 struct pipe_resource
*texture
,
849 const struct pipe_surface
*templ
,
850 unsigned width0
, unsigned height0
,
851 unsigned width
, unsigned height
);
852 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
853 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
854 struct r600_texture
*tex
);
855 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
856 struct r600_texture
*tex
);
857 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
858 struct r600_texture
*tex
);
859 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
860 struct r600_texture
*rtex
,
861 unsigned level
, unsigned clear_value
);
862 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
863 struct pipe_framebuffer_state
*fb
,
864 struct r600_atom
*fb_state
,
865 unsigned *buffers
, ubyte
*dirty_cbufs
,
866 const union pipe_color_union
*color
);
867 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
868 struct r600_texture
*rtex
);
869 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
);
870 void r600_init_context_texture_functions(struct r600_common_context
*rctx
);
872 /* r600_viewport.c */
873 void evergreen_apply_scissor_bug_workaround(struct r600_common_context
*rctx
,
874 struct pipe_scissor_state
*scissor
);
875 void r600_viewport_set_rast_deps(struct r600_common_context
*rctx
,
876 bool scissor_enable
, bool clip_halfz
);
877 void r600_update_vs_writes_viewport_index(struct r600_common_context
*rctx
,
878 struct tgsi_shader_info
*info
);
879 void r600_init_viewport_functions(struct r600_common_context
*rctx
);
882 extern const uint32_t eg_sample_locs_2x
[4];
883 extern const unsigned eg_max_dist_2x
;
884 extern const uint32_t eg_sample_locs_4x
[4];
885 extern const unsigned eg_max_dist_4x
;
886 void cayman_get_sample_position(struct pipe_context
*ctx
, unsigned sample_count
,
887 unsigned sample_index
, float *out_value
);
888 void cayman_init_msaa(struct pipe_context
*ctx
);
889 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
890 void cayman_emit_msaa_config(struct radeon_winsys_cs
*cs
, int nr_samples
,
891 int ps_iter_samples
, int overrast_samples
,
892 unsigned sc_mode_cntl_1
);
895 /* Inline helpers. */
897 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
899 return (struct r600_resource
*)r
;
903 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
905 pipe_resource_reference((struct pipe_resource
**)ptr
,
906 (struct pipe_resource
*)res
);
910 r600_texture_reference(struct r600_texture
**ptr
, struct r600_texture
*res
)
912 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->resource
.b
.b
);
916 r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
918 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
919 struct r600_resource
*res
= (struct r600_resource
*)r
;
922 /* Add memory usage for need_gfx_cs_space */
923 rctx
->vram
+= res
->vram_usage
;
924 rctx
->gtt
+= res
->gart_usage
;
928 static inline bool r600_get_strmout_en(struct r600_common_context
*rctx
)
930 return rctx
->streamout
.streamout_enabled
||
931 rctx
->streamout
.prims_gen_query_enabled
;
934 #define SQ_TEX_XY_FILTER_POINT 0x00
935 #define SQ_TEX_XY_FILTER_BILINEAR 0x01
936 #define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
937 #define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03
939 static inline unsigned eg_tex_filter(unsigned filter
, unsigned max_aniso
)
941 if (filter
== PIPE_TEX_FILTER_LINEAR
)
942 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
943 : SQ_TEX_XY_FILTER_BILINEAR
;
945 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
946 : SQ_TEX_XY_FILTER_POINT
;
949 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
962 static inline unsigned r600_wavefront_size(enum radeon_family family
)
982 static inline enum radeon_bo_priority
983 r600_get_sampler_view_priority(struct r600_resource
*res
)
985 if (res
->b
.b
.target
== PIPE_BUFFER
)
986 return RADEON_PRIO_SAMPLER_BUFFER
;
988 if (res
->b
.b
.nr_samples
> 1)
989 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
991 return RADEON_PRIO_SAMPLER_TEXTURE
;
995 r600_can_sample_zs(struct r600_texture
*tex
, bool stencil_sampler
)
997 return (stencil_sampler
&& tex
->can_sample_s
) ||
998 (!stencil_sampler
&& tex
->can_sample_z
);
1002 vi_dcc_enabled(struct r600_texture
*tex
, unsigned level
)
1004 return tex
->dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
1007 #define COMPUTE_DBG(rscreen, fmt, args...) \
1009 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
1012 #define R600_ERR(fmt, args...) \
1013 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1015 /* For MSAA sample positions. */
1016 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1017 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1018 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1019 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1020 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1022 static inline int S_FIXED(float value
, unsigned frac_bits
)
1024 return value
* (1 << frac_bits
);