2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
37 #include "radeon/radeon_winsys.h"
39 #include "util/u_blitter.h"
40 #include "util/list.h"
41 #include "util/u_range.h"
42 #include "util/u_slab.h"
43 #include "util/u_suballoc.h"
44 #include "util/u_transfer.h"
46 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
47 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
48 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
50 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
51 #define R600_CONTEXT_PRIVATE_FLAG (1u << 1)
53 /* special primitive types */
54 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
58 #define DBG_TEX (1 << 0)
60 #define DBG_COMPUTE (1 << 2)
61 #define DBG_VM (1 << 3)
62 #define DBG_TRACE_CS (1 << 4)
64 #define DBG_FS (1 << 5)
65 #define DBG_VS (1 << 6)
66 #define DBG_GS (1 << 7)
67 #define DBG_PS (1 << 8)
68 #define DBG_CS (1 << 9)
69 #define DBG_TCS (1 << 10)
70 #define DBG_TES (1 << 11)
71 #define DBG_NO_IR (1 << 12)
72 #define DBG_NO_TGSI (1 << 13)
73 #define DBG_NO_ASM (1 << 14)
74 /* Bits 21-31 are reserved for the r600g driver. */
76 #define DBG_NO_ASYNC_DMA (1llu << 32)
77 #define DBG_NO_HYPERZ (1llu << 33)
78 #define DBG_NO_DISCARD_RANGE (1llu << 34)
79 #define DBG_NO_2D_TILING (1llu << 35)
80 #define DBG_NO_TILING (1llu << 36)
81 #define DBG_SWITCH_ON_EOP (1llu << 37)
82 #define DBG_FORCE_DMA (1llu << 38)
83 #define DBG_PRECOMPILE (1llu << 39)
84 #define DBG_INFO (1llu << 40)
85 #define DBG_NO_WC (1llu << 41)
86 #define DBG_CHECK_VM (1llu << 42)
87 #define DBG_NO_DCC (1llu << 43)
88 #define DBG_NO_DCC_CLEAR (1llu << 44)
89 #define DBG_NO_RB_PLUS (1llu << 45)
90 #define DBG_SI_SCHED (1llu << 46)
92 #define R600_MAP_BUFFER_ALIGNMENT 64
94 struct r600_common_context
;
95 struct r600_perfcounters
;
97 struct radeon_shader_reloc
{
102 struct radeon_shader_binary
{
107 /** Config/Context register state that accompanies this shader.
108 * This is a stream of dword pairs. First dword contains the
109 * register address, the second dword contains the value.*/
110 unsigned char *config
;
111 unsigned config_size
;
113 /** The number of bytes of config information for each global symbol.
115 unsigned config_size_per_symbol
;
117 /** Constant data accessed by the shader. This will be uploaded
118 * into a constant buffer. */
119 unsigned char *rodata
;
120 unsigned rodata_size
;
122 /** List of symbol offsets for the shader */
123 uint64_t *global_symbol_offsets
;
124 unsigned global_symbol_count
;
126 struct radeon_shader_reloc
*relocs
;
127 unsigned reloc_count
;
129 /** Disassembled shader in a string. */
133 void radeon_shader_binary_init(struct radeon_shader_binary
*b
);
134 void radeon_shader_binary_clean(struct radeon_shader_binary
*b
);
136 struct r600_resource
{
139 /* Winsys objects. */
140 struct pb_buffer
*buf
;
141 uint64_t gpu_address
;
143 /* Resource state. */
144 enum radeon_bo_domain domains
;
146 /* The buffer range which is initialized (with a write transfer,
147 * streamout, DMA, or as a random access target). The rest of
148 * the buffer is considered invalid and can be mapped unsynchronized.
150 * This allows unsychronized mapping of a buffer range which hasn't
151 * been used yet. It's for applications which forget to use
152 * the unsynchronized map flag and expect the driver to figure it out.
154 struct util_range valid_buffer_range
;
156 /* For buffers only. This indicates that a write operation has been
157 * performed by TC L2, but the cache hasn't been flushed.
158 * Any hw block which doesn't use or bypasses TC L2 should check this
159 * flag and flush the cache before using the buffer.
161 * For example, TC L2 must be flushed if a buffer which has been
162 * modified by a shader store instruction is about to be used as
163 * an index buffer. The reason is that VGT DMA index fetching doesn't
169 struct r600_transfer
{
170 struct pipe_transfer transfer
;
171 struct r600_resource
*staging
;
175 struct r600_fmask_info
{
179 unsigned pitch_in_pixels
;
180 unsigned bank_height
;
181 unsigned slice_tile_max
;
182 unsigned tile_mode_index
;
185 struct r600_cmask_info
{
193 unsigned slice_tile_max
;
194 unsigned base_address_reg
;
197 struct r600_htile_info
{
204 struct r600_texture
{
205 struct r600_resource resource
;
209 unsigned dirty_level_mask
; /* each bit says if that mipmap is compressed */
210 unsigned stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
211 struct r600_texture
*flushed_depth_texture
;
212 boolean is_flushing_texture
;
213 struct radeon_surf surface
;
215 /* Colorbuffer compression and fast clear. */
216 struct r600_fmask_info fmask
;
217 struct r600_cmask_info cmask
;
218 struct r600_resource
*cmask_buffer
;
219 struct r600_resource
*dcc_buffer
;
220 unsigned cb_color_info
; /* fast clear enable bit */
221 unsigned color_clear_value
[2];
223 /* Depth buffer compression and fast clear. */
224 struct r600_htile_info htile
;
225 struct r600_resource
*htile_buffer
;
226 bool depth_cleared
; /* if it was cleared at least once */
227 float depth_clear_value
;
228 bool stencil_cleared
; /* if it was cleared at least once */
229 uint8_t stencil_clear_value
;
231 bool non_disp_tiling
; /* R600-Cayman only */
234 struct r600_surface
{
235 struct pipe_surface base
;
237 bool color_initialized
;
238 bool depth_initialized
;
240 /* Misc. color flags. */
241 bool alphatest_bypass
;
245 /* Color registers. */
246 unsigned cb_color_info
;
247 unsigned cb_color_base
;
248 unsigned cb_color_view
;
249 unsigned cb_color_size
; /* R600 only */
250 unsigned cb_color_dim
; /* EG only */
251 unsigned cb_color_pitch
; /* EG and later */
252 unsigned cb_color_slice
; /* EG and later */
253 unsigned cb_dcc_base
; /* VI and later */
254 unsigned cb_color_attrib
; /* EG and later */
255 unsigned cb_dcc_control
; /* VI and later */
256 unsigned cb_color_fmask
; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
257 unsigned cb_color_fmask_slice
; /* EG and later */
258 unsigned cb_color_cmask
; /* CB_COLORn_TILE (r600 only) */
259 unsigned cb_color_mask
; /* R600 only */
260 unsigned spi_shader_col_format
; /* SI+, no blending, no alpha-to-coverage. */
261 unsigned spi_shader_col_format_alpha
; /* SI+, alpha-to-coverage */
262 unsigned spi_shader_col_format_blend
; /* SI+, blending without alpha. */
263 unsigned spi_shader_col_format_blend_alpha
; /* SI+, blending with alpha. */
264 struct r600_resource
*cb_buffer_fmask
; /* Used for FMASK relocations. R600 only */
265 struct r600_resource
*cb_buffer_cmask
; /* Used for CMASK relocations. R600 only */
268 unsigned db_depth_info
; /* R600 only, then SI and later */
269 unsigned db_z_info
; /* EG and later */
270 unsigned db_depth_base
; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
271 unsigned db_depth_view
;
272 unsigned db_depth_size
;
273 unsigned db_depth_slice
; /* EG and later */
274 unsigned db_stencil_base
; /* EG and later */
275 unsigned db_stencil_info
; /* EG and later */
276 unsigned db_prefetch_limit
; /* R600 only */
277 unsigned db_htile_surface
;
278 unsigned db_htile_data_base
;
279 unsigned db_preload_control
; /* EG and later */
280 unsigned pa_su_poly_offset_db_fmt_cntl
;
283 struct r600_tiling_info
{
284 unsigned num_channels
;
286 unsigned group_bytes
;
289 struct r600_common_screen
{
290 struct pipe_screen b
;
291 struct radeon_winsys
*ws
;
292 enum radeon_family family
;
293 enum chip_class chip_class
;
294 struct radeon_info info
;
295 struct r600_tiling_info tiling_info
;
296 uint64_t debug_flags
;
300 /* Auxiliary context. Mainly used to initialize resources.
301 * It must be locked prior to using and flushed before unlocking. */
302 struct pipe_context
*aux_context
;
303 pipe_mutex aux_context_lock
;
305 struct r600_resource
*trace_bo
;
309 /* This must be in the screen, because UE4 uses one context for
310 * compilation and another one for rendering.
312 unsigned num_compilations
;
313 /* Along with ST_DEBUG=precompile, this should show if applications
314 * are loading shaders on demand. This is a monotonic counter.
316 unsigned num_shaders_created
;
318 /* GPU load thread. */
319 pipe_mutex gpu_load_mutex
;
320 pipe_thread gpu_load_thread
;
321 unsigned gpu_load_counter_busy
;
322 unsigned gpu_load_counter_idle
;
323 volatile unsigned gpu_load_stop_thread
; /* bool */
325 char renderer_string
[64];
327 /* Performance counters. */
328 struct r600_perfcounters
*perfcounters
;
331 /* This encapsulates a state or an operation which can emitted into the GPU
334 void (*emit
)(struct r600_common_context
*ctx
, struct r600_atom
*state
);
339 struct r600_so_target
{
340 struct pipe_stream_output_target b
;
342 /* The buffer where BUFFER_FILLED_SIZE is stored. */
343 struct r600_resource
*buf_filled_size
;
344 unsigned buf_filled_size_offset
;
345 bool buf_filled_size_valid
;
347 unsigned stride_in_dw
;
350 struct r600_streamout
{
351 struct r600_atom begin_atom
;
353 unsigned num_dw_for_end
;
355 unsigned enabled_mask
;
356 unsigned num_targets
;
357 struct r600_so_target
*targets
[PIPE_MAX_SO_BUFFERS
];
359 unsigned append_bitmask
;
362 /* External state which comes from the vertex shader,
363 * it must be set explicitly when binding a shader. */
364 unsigned *stride_in_dw
;
365 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
367 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
368 unsigned hw_enabled_mask
;
370 /* The state of VGT_STRMOUT_(CONFIG|EN). */
371 struct r600_atom enable_atom
;
372 bool streamout_enabled
;
373 bool prims_gen_query_enabled
;
374 int num_prims_gen_queries
;
378 struct radeon_winsys_cs
*cs
;
379 void (*flush
)(void *ctx
, unsigned flags
,
380 struct pipe_fence_handle
**fence
);
383 struct r600_common_context
{
384 struct pipe_context b
; /* base class */
386 struct r600_common_screen
*screen
;
387 struct radeon_winsys
*ws
;
388 struct radeon_winsys_ctx
*ctx
;
389 enum radeon_family family
;
390 enum chip_class chip_class
;
391 struct r600_ring gfx
;
392 struct r600_ring dma
;
393 struct pipe_fence_handle
*last_sdma_fence
;
394 unsigned initial_gfx_cs_size
;
395 unsigned gpu_reset_counter
;
397 struct u_upload_mgr
*uploader
;
398 struct u_suballocator
*allocator_so_filled_size
;
399 struct util_slab_mempool pool_transfers
;
401 /* Current unaccounted memory usage. */
406 struct r600_streamout streamout
;
408 /* Additional context states. */
409 unsigned flags
; /* flush flags */
412 /* The list of active queries. Only one query of each type can be active. */
413 int num_occlusion_queries
;
414 /* Keep track of non-timer queries, because they should be suspended
415 * during context flushing.
416 * The timer queries (TIME_ELAPSED) shouldn't be suspended for blits,
417 * but they should be suspended between IBs. */
418 struct list_head active_nontimer_queries
;
419 struct list_head active_timer_queries
;
420 unsigned num_cs_dw_nontimer_queries_suspend
;
421 bool nontimer_queries_suspended_by_flush
;
422 unsigned num_cs_dw_timer_queries_suspend
;
423 /* Additional hardware info. */
424 unsigned backend_mask
;
425 unsigned max_db
; /* for OQ */
427 unsigned num_draw_calls
;
429 /* Render condition. */
430 struct r600_atom render_cond_atom
;
431 struct pipe_query
*render_cond
;
432 unsigned render_cond_mode
;
433 boolean render_cond_invert
;
434 bool render_cond_force_off
; /* for u_blitter */
436 /* MSAA sample locations.
437 * The first index is the sample index.
438 * The second index is the coordinate: X, Y. */
439 float sample_locations_1x
[1][2];
440 float sample_locations_2x
[2][2];
441 float sample_locations_4x
[4][2];
442 float sample_locations_8x
[8][2];
443 float sample_locations_16x
[16][2];
445 /* The list of all texture buffer objects in this context.
446 * This list is walked when a buffer is invalidated/reallocated and
447 * the GPU addresses are updated. */
448 struct list_head texture_buffers
;
450 struct pipe_debug_callback debug
;
452 /* Copy one resource to another using async DMA. */
453 void (*dma_copy
)(struct pipe_context
*ctx
,
454 struct pipe_resource
*dst
,
456 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
457 struct pipe_resource
*src
,
459 const struct pipe_box
*src_box
);
461 void (*clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
462 unsigned offset
, unsigned size
, unsigned value
,
463 bool is_framebuffer
);
465 void (*blit_decompress_depth
)(struct pipe_context
*ctx
,
466 struct r600_texture
*texture
,
467 struct r600_texture
*staging
,
468 unsigned first_level
, unsigned last_level
,
469 unsigned first_layer
, unsigned last_layer
,
470 unsigned first_sample
, unsigned last_sample
);
472 /* Reallocate the buffer and update all resource bindings where
473 * the buffer is bound, including all resource descriptors. */
474 void (*invalidate_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
);
476 /* Enable or disable occlusion queries. */
477 void (*set_occlusion_query_state
)(struct pipe_context
*ctx
, bool enable
);
479 /* This ensures there is enough space in the command stream. */
480 void (*need_gfx_cs_space
)(struct pipe_context
*ctx
, unsigned num_dw
,
481 bool include_draw_vbo
);
483 void (*set_atom_dirty
)(struct r600_common_context
*ctx
,
484 struct r600_atom
*atom
, bool dirty
);
488 boolean
r600_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
489 struct pb_buffer
*buf
,
490 enum radeon_bo_usage usage
);
491 void *r600_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
492 struct r600_resource
*resource
,
494 bool r600_init_resource(struct r600_common_screen
*rscreen
,
495 struct r600_resource
*res
,
496 unsigned size
, unsigned alignment
,
497 bool use_reusable_pool
);
498 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
499 const struct pipe_resource
*templ
,
501 struct pipe_resource
* r600_aligned_buffer_create(struct pipe_screen
*screen
,
506 struct pipe_resource
*
507 r600_buffer_from_user_memory(struct pipe_screen
*screen
,
508 const struct pipe_resource
*templ
,
511 r600_invalidate_resource(struct pipe_context
*ctx
,
512 struct pipe_resource
*resource
);
514 /* r600_common_pipe.c */
515 void r600_draw_rectangle(struct blitter_context
*blitter
,
516 int x1
, int y1
, int x2
, int y2
, float depth
,
517 enum blitter_attrib_type type
,
518 const union pipe_color_union
*attrib
);
519 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
520 struct radeon_winsys
*ws
);
521 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
);
522 void r600_preflush_suspend_features(struct r600_common_context
*ctx
);
523 void r600_postflush_resume_features(struct r600_common_context
*ctx
);
524 bool r600_common_context_init(struct r600_common_context
*rctx
,
525 struct r600_common_screen
*rscreen
);
526 void r600_common_context_cleanup(struct r600_common_context
*rctx
);
527 void r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
);
528 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
530 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
531 unsigned offset
, unsigned size
, unsigned value
,
532 bool is_framebuffer
);
533 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
534 const struct pipe_resource
*templ
);
535 const char *r600_get_llvm_processor_name(enum radeon_family family
);
536 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
);
538 /* r600_gpu_load.c */
539 void r600_gpu_load_kill_thread(struct r600_common_screen
*rscreen
);
540 uint64_t r600_gpu_load_begin(struct r600_common_screen
*rscreen
);
541 unsigned r600_gpu_load_end(struct r600_common_screen
*rscreen
, uint64_t begin
);
543 /* r600_perfcounters.c */
544 void r600_perfcounters_destroy(struct r600_common_screen
*rscreen
);
547 void r600_init_screen_query_functions(struct r600_common_screen
*rscreen
);
548 void r600_query_init(struct r600_common_context
*rctx
);
549 void r600_suspend_nontimer_queries(struct r600_common_context
*ctx
);
550 void r600_resume_nontimer_queries(struct r600_common_context
*ctx
);
551 void r600_suspend_timer_queries(struct r600_common_context
*ctx
);
552 void r600_resume_timer_queries(struct r600_common_context
*ctx
);
553 void r600_query_init_backend_mask(struct r600_common_context
*ctx
);
555 /* r600_streamout.c */
556 void r600_streamout_buffers_dirty(struct r600_common_context
*rctx
);
557 void r600_set_streamout_targets(struct pipe_context
*ctx
,
558 unsigned num_targets
,
559 struct pipe_stream_output_target
**targets
,
560 const unsigned *offset
);
561 void r600_emit_streamout_end(struct r600_common_context
*rctx
);
562 void r600_update_prims_generated_query_state(struct r600_common_context
*rctx
,
563 unsigned type
, int diff
);
564 void r600_streamout_init(struct r600_common_context
*rctx
);
567 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
568 struct r600_texture
*rtex
,
570 struct r600_fmask_info
*out
);
571 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
572 struct r600_texture
*rtex
,
573 struct r600_cmask_info
*out
);
574 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
575 struct pipe_resource
*texture
,
576 struct r600_texture
**staging
);
577 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
);
578 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
579 const struct pipe_resource
*templ
);
580 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
581 struct pipe_resource
*texture
,
582 const struct pipe_surface
*templ
,
583 unsigned width
, unsigned height
);
584 unsigned r600_translate_colorswap(enum pipe_format format
);
585 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
586 struct pipe_framebuffer_state
*fb
,
587 struct r600_atom
*fb_state
,
588 unsigned *buffers
, unsigned *dirty_cbufs
,
589 const union pipe_color_union
*color
);
590 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
);
591 void r600_init_context_texture_functions(struct r600_common_context
*rctx
);
594 extern const uint32_t eg_sample_locs_2x
[4];
595 extern const unsigned eg_max_dist_2x
;
596 extern const uint32_t eg_sample_locs_4x
[4];
597 extern const unsigned eg_max_dist_4x
;
598 void cayman_get_sample_position(struct pipe_context
*ctx
, unsigned sample_count
,
599 unsigned sample_index
, float *out_value
);
600 void cayman_init_msaa(struct pipe_context
*ctx
);
601 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
602 void cayman_emit_msaa_config(struct radeon_winsys_cs
*cs
, int nr_samples
,
603 int ps_iter_samples
, int overrast_samples
);
606 /* Inline helpers. */
608 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
610 return (struct r600_resource
*)r
;
614 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
616 pipe_resource_reference((struct pipe_resource
**)ptr
,
617 (struct pipe_resource
*)res
);
620 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
622 if (filter
<= 1) return 0;
623 if (filter
<= 2) return 1;
624 if (filter
<= 4) return 2;
625 if (filter
<= 8) return 3;
629 static inline unsigned r600_wavefront_size(enum radeon_family family
)
649 static inline enum radeon_bo_priority
650 r600_get_sampler_view_priority(struct r600_resource
*res
)
652 if (res
->b
.b
.target
== PIPE_BUFFER
)
653 return RADEON_PRIO_SAMPLER_BUFFER
;
655 if (res
->b
.b
.nr_samples
> 1)
656 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
658 return RADEON_PRIO_SAMPLER_TEXTURE
;
661 #define COMPUTE_DBG(rscreen, fmt, args...) \
663 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
666 #define R600_ERR(fmt, args...) \
667 fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
669 /* For MSAA sample positions. */
670 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
671 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
672 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
673 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
674 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))