src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/u_slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  47 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  48 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  49
  50 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  51 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 1)
  52
  53 /* special primitive types */
  54 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  55
  56 /* Debug flags. */
  57 /* logging */
  58 #define DBG_TEX                 (1 << 0)
  59 /* gap - reuse */
  60 #define DBG_COMPUTE             (1 << 2)
  61 #define DBG_VM                  (1 << 3)
  62 #define DBG_TRACE_CS            (1 << 4)
  63 /* shader logging */
  64 #define DBG_FS                  (1 << 5)
  65 #define DBG_VS                  (1 << 6)
  66 #define DBG_GS                  (1 << 7)
  67 #define DBG_PS                  (1 << 8)
  68 #define DBG_CS                  (1 << 9)
  69 #define DBG_TCS                 (1 << 10)
  70 #define DBG_TES                 (1 << 11)
  71 #define DBG_NO_IR               (1 << 12)
  72 #define DBG_NO_TGSI             (1 << 13)
  73 #define DBG_NO_ASM              (1 << 14)
  74 /* Bits 21-31 are reserved for the r600g driver. */
  75 /* features */
  76 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  77 #define DBG_NO_HYPERZ           (1llu << 33)
  78 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  79 #define DBG_NO_2D_TILING        (1llu << 35)
  80 #define DBG_NO_TILING           (1llu << 36)
  81 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  82 #define DBG_FORCE_DMA           (1llu << 38)
  83 #define DBG_PRECOMPILE          (1llu << 39)
  84 #define DBG_INFO                (1llu << 40)
  85 #define DBG_NO_WC               (1llu << 41)
  86 #define DBG_CHECK_VM            (1llu << 42)
  87 #define DBG_NO_DCC              (1llu << 43)
  88 #define DBG_NO_DCC_CLEAR        (1llu << 44)
  89 #define DBG_NO_RB_PLUS          (1llu << 45)
  90
  91 #define R600_MAP_BUFFER_ALIGNMENT 64
  92
  93 struct r600_common_context;
  94 struct r600_perfcounters;
  95
  96 struct radeon_shader_reloc {
  97         char *name;
  98         uint64_t offset;
  99 };
 100
 101 struct radeon_shader_binary {
 102         /** Shader code */
 103         unsigned char *code;
 104         unsigned code_size;
 105
 106         /** Config/Context register state that accompanies this shader.
 107          * This is a stream of dword pairs.  First dword contains the
 108          * register address, the second dword contains the value.*/
 109         unsigned char *config;
 110         unsigned config_size;
 111
 112         /** The number of bytes of config information for each global symbol.
 113          */
 114         unsigned config_size_per_symbol;
 115
 116         /** Constant data accessed by the shader.  This will be uploaded
 117          * into a constant buffer. */
 118         unsigned char *rodata;
 119         unsigned rodata_size;
 120
 121         /** List of symbol offsets for the shader */
 122         uint64_t *global_symbol_offsets;
 123         unsigned global_symbol_count;
 124
 125         struct radeon_shader_reloc *relocs;
 126         unsigned reloc_count;
 127
 128         /** Disassembled shader in a string. */
 129         char *disasm_string;
 130 };
 131
 132 struct r600_resource {
 133         struct u_resource               b;
 134
 135         /* Winsys objects. */
 136         struct pb_buffer                *buf;
 137         uint64_t                        gpu_address;
 138
 139         /* Resource state. */
 140         enum radeon_bo_domain           domains;
 141
 142         /* The buffer range which is initialized (with a write transfer,
 143          * streamout, DMA, or as a random access target). The rest of
 144          * the buffer is considered invalid and can be mapped unsynchronized.
 145          *
 146          * This allows unsychronized mapping of a buffer range which hasn't
 147          * been used yet. It's for applications which forget to use
 148          * the unsynchronized map flag and expect the driver to figure it out.
 149          */
 150         struct util_range               valid_buffer_range;
 151
 152         /* For buffers only. This indicates that a write operation has been
 153          * performed by TC L2, but the cache hasn't been flushed.
 154          * Any hw block which doesn't use or bypasses TC L2 should check this
 155          * flag and flush the cache before using the buffer.
 156          *
 157          * For example, TC L2 must be flushed if a buffer which has been
 158          * modified by a shader store instruction is about to be used as
 159          * an index buffer. The reason is that VGT DMA index fetching doesn't
 160          * use TC L2.
 161          */
 162         bool                            TC_L2_dirty;
 163 };
 164
 165 struct r600_transfer {
 166         struct pipe_transfer            transfer;
 167         struct r600_resource            *staging;
 168         unsigned                        offset;
 169 };
 170
 171 struct r600_fmask_info {
 172         unsigned offset;
 173         unsigned size;
 174         unsigned alignment;
 175         unsigned pitch_in_pixels;
 176         unsigned bank_height;
 177         unsigned slice_tile_max;
 178         unsigned tile_mode_index;
 179 };
 180
 181 struct r600_cmask_info {
 182         unsigned offset;
 183         unsigned size;
 184         unsigned alignment;
 185         unsigned pitch;
 186         unsigned height;
 187         unsigned xalign;
 188         unsigned yalign;
 189         unsigned slice_tile_max;
 190         unsigned base_address_reg;
 191 };
 192
 193 struct r600_htile_info {
 194         unsigned pitch;
 195         unsigned height;
 196         unsigned xalign;
 197         unsigned yalign;
 198 };
 199
 200 struct r600_texture {
 201         struct r600_resource            resource;
 202
 203         unsigned                        size;
 204         bool                            is_depth;
 205         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 206         unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 207         struct r600_texture             *flushed_depth_texture;
 208         boolean                         is_flushing_texture;
 209         struct radeon_surf              surface;
 210
 211         /* Colorbuffer compression and fast clear. */
 212         struct r600_fmask_info          fmask;
 213         struct r600_cmask_info          cmask;
 214         struct r600_resource            *cmask_buffer;
 215         struct r600_resource            *dcc_buffer;
 216         unsigned                        cb_color_info; /* fast clear enable bit */
 217         unsigned                        color_clear_value[2];
 218
 219         /* Depth buffer compression and fast clear. */
 220         struct r600_htile_info          htile;
 221         struct r600_resource            *htile_buffer;
 222         bool                            depth_cleared; /* if it was cleared at least once */
 223         float                           depth_clear_value;
 224         bool                            stencil_cleared; /* if it was cleared at least once */
 225         uint8_t                         stencil_clear_value;
 226
 227         bool                            non_disp_tiling; /* R600-Cayman only */
 228 };
 229
 230 struct r600_surface {
 231         struct pipe_surface             base;
 232
 233         bool color_initialized;
 234         bool depth_initialized;
 235
 236         /* Misc. color flags. */
 237         bool alphatest_bypass;
 238         bool export_16bpc;
 239         bool color_is_int8;
 240
 241         /* Color registers. */
 242         unsigned cb_color_info;
 243         unsigned cb_color_base;
 244         unsigned cb_color_view;
 245         unsigned cb_color_size;         /* R600 only */
 246         unsigned cb_color_dim;          /* EG only */
 247         unsigned cb_color_pitch;        /* EG and later */
 248         unsigned cb_color_slice;        /* EG and later */
 249         unsigned cb_dcc_base;           /* VI and later */
 250         unsigned cb_color_attrib;       /* EG and later */
 251         unsigned cb_dcc_control;        /* VI and later */
 252         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 253         unsigned cb_color_fmask_slice;  /* EG and later */
 254         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 255         unsigned cb_color_mask;         /* R600 only */
 256         unsigned spi_shader_col_format;         /* SI+, no blending, no alpha-to-coverage. */
 257         unsigned spi_shader_col_format_alpha;   /* SI+, alpha-to-coverage */
 258         unsigned spi_shader_col_format_blend;   /* SI+, blending without alpha. */
 259         unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
 260         unsigned sx_ps_downconvert;     /* Stoney only */
 261         unsigned sx_blend_opt_epsilon;  /* Stoney only */
 262         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 263         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 264
 265         /* DB registers. */
 266         unsigned db_depth_info;         /* R600 only, then SI and later */
 267         unsigned db_z_info;             /* EG and later */
 268         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 269         unsigned db_depth_view;
 270         unsigned db_depth_size;
 271         unsigned db_depth_slice;        /* EG and later */
 272         unsigned db_stencil_base;       /* EG and later */
 273         unsigned db_stencil_info;       /* EG and later */
 274         unsigned db_prefetch_limit;     /* R600 only */
 275         unsigned db_htile_surface;
 276         unsigned db_htile_data_base;
 277         unsigned db_preload_control;    /* EG and later */
 278         unsigned pa_su_poly_offset_db_fmt_cntl;
 279 };
 280
 281 struct r600_tiling_info {
 282         unsigned num_channels;
 283         unsigned num_banks;
 284         unsigned group_bytes;
 285 };
 286
 287 struct r600_common_screen {
 288         struct pipe_screen              b;
 289         struct radeon_winsys            *ws;
 290         enum radeon_family              family;
 291         enum chip_class                 chip_class;
 292         struct radeon_info              info;
 293         struct r600_tiling_info         tiling_info;
 294         uint64_t                        debug_flags;
 295         bool                            has_cp_dma;
 296         bool                            has_streamout;
 297
 298         /* Auxiliary context. Mainly used to initialize resources.
 299          * It must be locked prior to using and flushed before unlocking. */
 300         struct pipe_context             *aux_context;
 301         pipe_mutex                      aux_context_lock;
 302
 303         struct r600_resource            *trace_bo;
 304         uint32_t                        *trace_ptr;
 305         unsigned                        cs_count;
 306
 307         /* This must be in the screen, because UE4 uses one context for
 308          * compilation and another one for rendering.
 309          */
 310         unsigned                        num_compilations;
 311         /* Along with ST_DEBUG=precompile, this should show if applications
 312          * are loading shaders on demand. This is a monotonic counter.
 313          */
 314         unsigned                        num_shaders_created;
 315
 316         /* GPU load thread. */
 317         pipe_mutex                      gpu_load_mutex;
 318         pipe_thread                     gpu_load_thread;
 319         unsigned                        gpu_load_counter_busy;
 320         unsigned                        gpu_load_counter_idle;
 321         volatile unsigned               gpu_load_stop_thread; /* bool */
 322
 323         char                            renderer_string[64];
 324
 325         /* Performance counters. */
 326         struct r600_perfcounters        *perfcounters;
 327 };
 328
 329 /* This encapsulates a state or an operation which can emitted into the GPU
 330  * command stream. */
 331 struct r600_atom {
 332         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 333         unsigned                num_dw;
 334         unsigned short          id;
 335 };
 336
 337 struct r600_so_target {
 338         struct pipe_stream_output_target b;
 339
 340         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 341         struct r600_resource    *buf_filled_size;
 342         unsigned                buf_filled_size_offset;
 343         bool                    buf_filled_size_valid;
 344
 345         unsigned                stride_in_dw;
 346 };
 347
 348 struct r600_streamout {
 349         struct r600_atom                begin_atom;
 350         bool                            begin_emitted;
 351         unsigned                        num_dw_for_end;
 352
 353         unsigned                        enabled_mask;
 354         unsigned                        num_targets;
 355         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 356
 357         unsigned                        append_bitmask;
 358         bool                            suspended;
 359
 360         /* External state which comes from the vertex shader,
 361          * it must be set explicitly when binding a shader. */
 362         unsigned                        *stride_in_dw;
 363         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 364
 365         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 366         unsigned                        hw_enabled_mask;
 367
 368         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 369         struct r600_atom                enable_atom;
 370         bool                            streamout_enabled;
 371         bool                            prims_gen_query_enabled;
 372         int                             num_prims_gen_queries;
 373 };
 374
 375 struct r600_ring {
 376         struct radeon_winsys_cs         *cs;
 377         void (*flush)(void *ctx, unsigned flags,
 378                       struct pipe_fence_handle **fence);
 379 };
 380
 381 struct r600_common_context {
 382         struct pipe_context b; /* base class */
 383
 384         struct r600_common_screen       *screen;
 385         struct radeon_winsys            *ws;
 386         struct radeon_winsys_ctx        *ctx;
 387         enum radeon_family              family;
 388         enum chip_class                 chip_class;
 389         struct r600_ring                gfx;
 390         struct r600_ring                dma;
 391         struct pipe_fence_handle        *last_sdma_fence;
 392         unsigned                        initial_gfx_cs_size;
 393         unsigned                        gpu_reset_counter;
 394
 395         struct u_upload_mgr             *uploader;
 396         struct u_suballocator           *allocator_so_filled_size;
 397         struct util_slab_mempool        pool_transfers;
 398
 399         /* Current unaccounted memory usage. */
 400         uint64_t                        vram;
 401         uint64_t                        gtt;
 402
 403         /* States. */
 404         struct r600_streamout           streamout;
 405
 406         /* Additional context states. */
 407         unsigned flags; /* flush flags */
 408
 409         /* Queries. */
 410         /* The list of active queries. Only one query of each type can be active. */
 411         int                             num_occlusion_queries;
 412         /* Keep track of non-timer queries, because they should be suspended
 413          * during context flushing.
 414          * The timer queries (TIME_ELAPSED) shouldn't be suspended for blits,
 415          * but they should be suspended between IBs. */
 416         struct list_head                active_nontimer_queries;
 417         struct list_head                active_timer_queries;
 418         unsigned                        num_cs_dw_nontimer_queries_suspend;
 419         bool                            nontimer_queries_suspended_by_flush;
 420         unsigned                        num_cs_dw_timer_queries_suspend;
 421         /* Additional hardware info. */
 422         unsigned                        backend_mask;
 423         unsigned                        max_db; /* for OQ */
 424         /* Misc stats. */
 425         unsigned                        num_draw_calls;
 426
 427         /* Render condition. */
 428         struct r600_atom                render_cond_atom;
 429         struct pipe_query               *render_cond;
 430         unsigned                        render_cond_mode;
 431         boolean                         render_cond_invert;
 432         bool                            render_cond_force_off; /* for u_blitter */
 433
 434         /* MSAA sample locations.
 435          * The first index is the sample index.
 436          * The second index is the coordinate: X, Y. */
 437         float                           sample_locations_1x[1][2];
 438         float                           sample_locations_2x[2][2];
 439         float                           sample_locations_4x[4][2];
 440         float                           sample_locations_8x[8][2];
 441         float                           sample_locations_16x[16][2];
 442
 443         /* The list of all texture buffer objects in this context.
 444          * This list is walked when a buffer is invalidated/reallocated and
 445          * the GPU addresses are updated. */
 446         struct list_head                texture_buffers;
 447
 448         struct pipe_debug_callback      debug;
 449
 450         /* Copy one resource to another using async DMA. */
 451         void (*dma_copy)(struct pipe_context *ctx,
 452                          struct pipe_resource *dst,
 453                          unsigned dst_level,
 454                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 455                          struct pipe_resource *src,
 456                          unsigned src_level,
 457                          const struct pipe_box *src_box);
 458
 459         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 460                              unsigned offset, unsigned size, unsigned value,
 461                              bool is_framebuffer);
 462
 463         void (*blit_decompress_depth)(struct pipe_context *ctx,
 464                                       struct r600_texture *texture,
 465                                       struct r600_texture *staging,
 466                                       unsigned first_level, unsigned last_level,
 467                                       unsigned first_layer, unsigned last_layer,
 468                                       unsigned first_sample, unsigned last_sample);
 469
 470         /* Reallocate the buffer and update all resource bindings where
 471          * the buffer is bound, including all resource descriptors. */
 472         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 473
 474         /* Enable or disable occlusion queries. */
 475         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 476
 477         /* This ensures there is enough space in the command stream. */
 478         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 479                                   bool include_draw_vbo);
 480
 481         void (*set_atom_dirty)(struct r600_common_context *ctx,
 482                                struct r600_atom *atom, bool dirty);
 483 };
 484
 485 /* r600_buffer.c */
 486 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 487                                         struct pb_buffer *buf,
 488                                         enum radeon_bo_usage usage);
 489 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 490                                       struct r600_resource *resource,
 491                                       unsigned usage);
 492 bool r600_init_resource(struct r600_common_screen *rscreen,
 493                         struct r600_resource *res,
 494                         unsigned size, unsigned alignment,
 495                         bool use_reusable_pool);
 496 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 497                                          const struct pipe_resource *templ,
 498                                          unsigned alignment);
 499 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
 500                                                   unsigned bind,
 501                                                   unsigned usage,
 502                                                   unsigned size,
 503                                                   unsigned alignment);
 504 struct pipe_resource *
 505 r600_buffer_from_user_memory(struct pipe_screen *screen,
 506                              const struct pipe_resource *templ,
 507                              void *user_memory);
 508 void
 509 r600_invalidate_resource(struct pipe_context *ctx,
 510                          struct pipe_resource *resource);
 511
 512 /* r600_common_pipe.c */
 513 void r600_draw_rectangle(struct blitter_context *blitter,
 514                          int x1, int y1, int x2, int y2, float depth,
 515                          enum blitter_attrib_type type,
 516                          const union pipe_color_union *attrib);
 517 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 518                              struct radeon_winsys *ws);
 519 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 520 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 521 void r600_postflush_resume_features(struct r600_common_context *ctx);
 522 bool r600_common_context_init(struct r600_common_context *rctx,
 523                               struct r600_common_screen *rscreen);
 524 void r600_common_context_cleanup(struct r600_common_context *rctx);
 525 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 526 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 527                           unsigned processor);
 528 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 529                               unsigned offset, unsigned size, unsigned value,
 530                               bool is_framebuffer);
 531 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 532                                                   const struct pipe_resource *templ);
 533 const char *r600_get_llvm_processor_name(enum radeon_family family);
 534 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw);
 535
 536 /* r600_gpu_load.c */
 537 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 538 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
 539 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 540
 541 /* r600_perfcounters.c */
 542 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
 543
 544 /* r600_query.c */
 545 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
 546 void r600_query_init(struct r600_common_context *rctx);
 547 void r600_suspend_nontimer_queries(struct r600_common_context *ctx);
 548 void r600_resume_nontimer_queries(struct r600_common_context *ctx);
 549 void r600_suspend_timer_queries(struct r600_common_context *ctx);
 550 void r600_resume_timer_queries(struct r600_common_context *ctx);
 551 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 552
 553 /* r600_streamout.c */
 554 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 555 void r600_set_streamout_targets(struct pipe_context *ctx,
 556                                 unsigned num_targets,
 557                                 struct pipe_stream_output_target **targets,
 558                                 const unsigned *offset);
 559 void r600_emit_streamout_end(struct r600_common_context *rctx);
 560 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 561                                              unsigned type, int diff);
 562 void r600_streamout_init(struct r600_common_context *rctx);
 563
 564 /* r600_texture.c */
 565 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 566                                  struct r600_texture *rtex,
 567                                  unsigned nr_samples,
 568                                  struct r600_fmask_info *out);
 569 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 570                                  struct r600_texture *rtex,
 571                                  struct r600_cmask_info *out);
 572 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 573                                      struct pipe_resource *texture,
 574                                      struct r600_texture **staging);
 575 void r600_print_texture_info(struct r600_texture *rtex, FILE *f);
 576 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 577                                         const struct pipe_resource *templ);
 578 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 579                                                 struct pipe_resource *texture,
 580                                                 const struct pipe_surface *templ,
 581                                                 unsigned width, unsigned height);
 582 unsigned r600_translate_colorswap(enum pipe_format format);
 583 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 584                                    struct pipe_framebuffer_state *fb,
 585                                    struct r600_atom *fb_state,
 586                                    unsigned *buffers, unsigned *dirty_cbufs,
 587                                    const union pipe_color_union *color);
 588 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 589 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 590
 591 /* cayman_msaa.c */
 592 extern const uint32_t eg_sample_locs_2x[4];
 593 extern const unsigned eg_max_dist_2x;
 594 extern const uint32_t eg_sample_locs_4x[4];
 595 extern const unsigned eg_max_dist_4x;
 596 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 597                                 unsigned sample_index, float *out_value);
 598 void cayman_init_msaa(struct pipe_context *ctx);
 599 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 600 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 601                              int ps_iter_samples, int overrast_samples);
 602
 603
 604 /* Inline helpers. */
 605
 606 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 607 {
 608         return (struct r600_resource*)r;
 609 }
 610
 611 static inline void
 612 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 613 {
 614         pipe_resource_reference((struct pipe_resource **)ptr,
 615                                 (struct pipe_resource *)res);
 616 }
 617
 618 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 619 {
 620         if (filter <= 1)   return 0;
 621         if (filter <= 2)   return 1;
 622         if (filter <= 4)   return 2;
 623         if (filter <= 8)   return 3;
 624          /* else */        return 4;
 625 }
 626
 627 static inline unsigned r600_wavefront_size(enum radeon_family family)
 628 {
 629         switch (family) {
 630         case CHIP_RV610:
 631         case CHIP_RS780:
 632         case CHIP_RV620:
 633         case CHIP_RS880:
 634                 return 16;
 635         case CHIP_RV630:
 636         case CHIP_RV635:
 637         case CHIP_RV730:
 638         case CHIP_RV710:
 639         case CHIP_PALM:
 640         case CHIP_CEDAR:
 641                 return 32;
 642         default:
 643                 return 64;
 644         }
 645 }
 646
 647 static inline enum radeon_bo_priority
 648 r600_get_sampler_view_priority(struct r600_resource *res)
 649 {
 650         if (res->b.b.target == PIPE_BUFFER)
 651                 return RADEON_PRIO_SAMPLER_BUFFER;
 652
 653         if (res->b.b.nr_samples > 1)
 654                 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
 655
 656         return RADEON_PRIO_SAMPLER_TEXTURE;
 657 }
 658
 659 #define COMPUTE_DBG(rscreen, fmt, args...) \
 660         do { \
 661                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 662         } while (0);
 663
 664 #define R600_ERR(fmt, args...) \
 665         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
 666
 667 /* For MSAA sample positions. */
 668 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 669         (((s0x) & 0xf) | (((s0y) & 0xf) << 4) |            \
 670         (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |     \
 671         (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |    \
 672          (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
 673
 674 #endif