src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/u_slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  47 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  48 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  49
  50 #define R600_QUERY_DRAW_CALLS           (PIPE_QUERY_DRIVER_SPECIFIC + 0)
  51 #define R600_QUERY_REQUESTED_VRAM       (PIPE_QUERY_DRIVER_SPECIFIC + 1)
  52 #define R600_QUERY_REQUESTED_GTT        (PIPE_QUERY_DRIVER_SPECIFIC + 2)
  53 #define R600_QUERY_BUFFER_WAIT_TIME     (PIPE_QUERY_DRIVER_SPECIFIC + 3)
  54 #define R600_QUERY_NUM_CS_FLUSHES       (PIPE_QUERY_DRIVER_SPECIFIC + 4)
  55 #define R600_QUERY_NUM_BYTES_MOVED      (PIPE_QUERY_DRIVER_SPECIFIC + 5)
  56 #define R600_QUERY_VRAM_USAGE           (PIPE_QUERY_DRIVER_SPECIFIC + 6)
  57 #define R600_QUERY_GTT_USAGE            (PIPE_QUERY_DRIVER_SPECIFIC + 7)
  58 #define R600_QUERY_GPU_TEMPERATURE      (PIPE_QUERY_DRIVER_SPECIFIC + 8)
  59 #define R600_QUERY_CURRENT_GPU_SCLK     (PIPE_QUERY_DRIVER_SPECIFIC + 9)
  60 #define R600_QUERY_CURRENT_GPU_MCLK     (PIPE_QUERY_DRIVER_SPECIFIC + 10)
  61 #define R600_QUERY_GPU_LOAD             (PIPE_QUERY_DRIVER_SPECIFIC + 11)
  62 #define R600_QUERY_NUM_COMPILATIONS     (PIPE_QUERY_DRIVER_SPECIFIC + 12)
  63 #define R600_QUERY_NUM_SHADERS_CREATED  (PIPE_QUERY_DRIVER_SPECIFIC + 13)
  64
  65 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  66 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 1)
  67
  68 /* special primitive types */
  69 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  70
  71 /* Debug flags. */
  72 /* logging */
  73 #define DBG_TEX                 (1 << 0)
  74 #define DBG_TEXMIP              (1 << 1)
  75 #define DBG_COMPUTE             (1 << 2)
  76 #define DBG_VM                  (1 << 3)
  77 #define DBG_TRACE_CS            (1 << 4)
  78 /* shader logging */
  79 #define DBG_FS                  (1 << 5)
  80 #define DBG_VS                  (1 << 6)
  81 #define DBG_GS                  (1 << 7)
  82 #define DBG_PS                  (1 << 8)
  83 #define DBG_CS                  (1 << 9)
  84 #define DBG_TCS                 (1 << 10)
  85 #define DBG_TES                 (1 << 11)
  86 #define DBG_NO_IR               (1 << 12)
  87 #define DBG_NO_TGSI             (1 << 13)
  88 #define DBG_NO_ASM              (1 << 14)
  89 /* Bits 21-31 are reserved for the r600g driver. */
  90 /* features */
  91 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  92 #define DBG_NO_HYPERZ           (1llu << 33)
  93 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  94 #define DBG_NO_2D_TILING        (1llu << 35)
  95 #define DBG_NO_TILING           (1llu << 36)
  96 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  97 #define DBG_FORCE_DMA           (1llu << 38)
  98 #define DBG_PRECOMPILE          (1llu << 39)
  99 #define DBG_INFO                (1llu << 40)
 100 #define DBG_NO_WC               (1llu << 41)
 101 #define DBG_CHECK_VM            (1llu << 42)
 102 #define DBG_NO_DCC              (1llu << 43)
 103 #define DBG_NO_DCC_CLEAR        (1llu << 44)
 104
 105 #define R600_MAP_BUFFER_ALIGNMENT 64
 106
 107 struct r600_common_context;
 108
 109 struct radeon_shader_reloc {
 110         char *name;
 111         uint64_t offset;
 112 };
 113
 114 struct radeon_shader_binary {
 115         /** Shader code */
 116         unsigned char *code;
 117         unsigned code_size;
 118
 119         /** Config/Context register state that accompanies this shader.
 120          * This is a stream of dword pairs.  First dword contains the
 121          * register address, the second dword contains the value.*/
 122         unsigned char *config;
 123         unsigned config_size;
 124
 125         /** The number of bytes of config information for each global symbol.
 126          */
 127         unsigned config_size_per_symbol;
 128
 129         /** Constant data accessed by the shader.  This will be uploaded
 130          * into a constant buffer. */
 131         unsigned char *rodata;
 132         unsigned rodata_size;
 133
 134         /** List of symbol offsets for the shader */
 135         uint64_t *global_symbol_offsets;
 136         unsigned global_symbol_count;
 137
 138         struct radeon_shader_reloc *relocs;
 139         unsigned reloc_count;
 140
 141         /** Disassembled shader in a string. */
 142         char *disasm_string;
 143 };
 144
 145 struct r600_resource {
 146         struct u_resource               b;
 147
 148         /* Winsys objects. */
 149         struct pb_buffer                *buf;
 150         struct radeon_winsys_cs_handle  *cs_buf;
 151         uint64_t                        gpu_address;
 152
 153         /* Resource state. */
 154         enum radeon_bo_domain           domains;
 155
 156         /* The buffer range which is initialized (with a write transfer,
 157          * streamout, DMA, or as a random access target). The rest of
 158          * the buffer is considered invalid and can be mapped unsynchronized.
 159          *
 160          * This allows unsychronized mapping of a buffer range which hasn't
 161          * been used yet. It's for applications which forget to use
 162          * the unsynchronized map flag and expect the driver to figure it out.
 163          */
 164         struct util_range               valid_buffer_range;
 165
 166         /* For buffers only. This indicates that a write operation has been
 167          * performed by TC L2, but the cache hasn't been flushed.
 168          * Any hw block which doesn't use or bypasses TC L2 should check this
 169          * flag and flush the cache before using the buffer.
 170          *
 171          * For example, TC L2 must be flushed if a buffer which has been
 172          * modified by a shader store instruction is about to be used as
 173          * an index buffer. The reason is that VGT DMA index fetching doesn't
 174          * use TC L2.
 175          */
 176         bool                            TC_L2_dirty;
 177 };
 178
 179 struct r600_transfer {
 180         struct pipe_transfer            transfer;
 181         struct r600_resource            *staging;
 182         unsigned                        offset;
 183 };
 184
 185 struct r600_fmask_info {
 186         unsigned offset;
 187         unsigned size;
 188         unsigned alignment;
 189         unsigned pitch;
 190         unsigned bank_height;
 191         unsigned slice_tile_max;
 192         unsigned tile_mode_index;
 193 };
 194
 195 struct r600_cmask_info {
 196         unsigned offset;
 197         unsigned size;
 198         unsigned alignment;
 199         unsigned slice_tile_max;
 200         unsigned base_address_reg;
 201 };
 202
 203 struct r600_texture {
 204         struct r600_resource            resource;
 205
 206         unsigned                        size;
 207         unsigned                        pitch_override;
 208         bool                            is_depth;
 209         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 210         unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 211         struct r600_texture             *flushed_depth_texture;
 212         boolean                         is_flushing_texture;
 213         struct radeon_surf              surface;
 214
 215         /* Colorbuffer compression and fast clear. */
 216         struct r600_fmask_info          fmask;
 217         struct r600_cmask_info          cmask;
 218         struct r600_resource            *cmask_buffer;
 219         struct r600_resource            *dcc_buffer;
 220         unsigned                        cb_color_info; /* fast clear enable bit */
 221         unsigned                        color_clear_value[2];
 222
 223         /* Depth buffer compression and fast clear. */
 224         struct r600_resource            *htile_buffer;
 225         bool                            depth_cleared; /* if it was cleared at least once */
 226         float                           depth_clear_value;
 227
 228         bool                            non_disp_tiling; /* R600-Cayman only */
 229 };
 230
 231 struct r600_surface {
 232         struct pipe_surface             base;
 233
 234         bool color_initialized;
 235         bool depth_initialized;
 236
 237         /* Misc. color flags. */
 238         bool alphatest_bypass;
 239         bool export_16bpc;
 240
 241         /* Color registers. */
 242         unsigned cb_color_info;
 243         unsigned cb_color_base;
 244         unsigned cb_color_view;
 245         unsigned cb_color_size;         /* R600 only */
 246         unsigned cb_color_dim;          /* EG only */
 247         unsigned cb_color_pitch;        /* EG and later */
 248         unsigned cb_color_slice;        /* EG and later */
 249         unsigned cb_dcc_base;           /* VI and later */
 250         unsigned cb_color_attrib;       /* EG and later */
 251         unsigned cb_dcc_control;        /* VI and later */
 252         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 253         unsigned cb_color_fmask_slice;  /* EG and later */
 254         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 255         unsigned cb_color_mask;         /* R600 only */
 256         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 257         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 258
 259         /* DB registers. */
 260         unsigned db_depth_info;         /* R600 only, then SI and later */
 261         unsigned db_z_info;             /* EG and later */
 262         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 263         unsigned db_depth_view;
 264         unsigned db_depth_size;
 265         unsigned db_depth_slice;        /* EG and later */
 266         unsigned db_stencil_base;       /* EG and later */
 267         unsigned db_stencil_info;       /* EG and later */
 268         unsigned db_prefetch_limit;     /* R600 only */
 269         unsigned db_htile_surface;
 270         unsigned db_htile_data_base;
 271         unsigned db_preload_control;    /* EG and later */
 272         unsigned pa_su_poly_offset_db_fmt_cntl;
 273 };
 274
 275 struct r600_tiling_info {
 276         unsigned num_channels;
 277         unsigned num_banks;
 278         unsigned group_bytes;
 279 };
 280
 281 struct r600_common_screen {
 282         struct pipe_screen              b;
 283         struct radeon_winsys            *ws;
 284         enum radeon_family              family;
 285         enum chip_class                 chip_class;
 286         struct radeon_info              info;
 287         struct r600_tiling_info         tiling_info;
 288         uint64_t                        debug_flags;
 289         bool                            has_cp_dma;
 290         bool                            has_streamout;
 291
 292         /* Auxiliary context. Mainly used to initialize resources.
 293          * It must be locked prior to using and flushed before unlocking. */
 294         struct pipe_context             *aux_context;
 295         pipe_mutex                      aux_context_lock;
 296
 297         struct r600_resource            *trace_bo;
 298         uint32_t                        *trace_ptr;
 299         unsigned                        cs_count;
 300
 301         /* This must be in the screen, because UE4 uses one context for
 302          * compilation and another one for rendering.
 303          */
 304         unsigned                        num_compilations;
 305         /* Along with ST_DEBUG=precompile, this should show if applications
 306          * are loading shaders on demand. This is a monotonic counter.
 307          */
 308         unsigned                        num_shaders_created;
 309
 310         /* GPU load thread. */
 311         pipe_mutex                      gpu_load_mutex;
 312         pipe_thread                     gpu_load_thread;
 313         unsigned                        gpu_load_counter_busy;
 314         unsigned                        gpu_load_counter_idle;
 315         volatile unsigned               gpu_load_stop_thread; /* bool */
 316
 317         char                            renderer_string[64];
 318 };
 319
 320 /* This encapsulates a state or an operation which can emitted into the GPU
 321  * command stream. */
 322 struct r600_atom {
 323         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 324         unsigned                num_dw;
 325         unsigned short          id;
 326 };
 327
 328 struct r600_so_target {
 329         struct pipe_stream_output_target b;
 330
 331         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 332         struct r600_resource    *buf_filled_size;
 333         unsigned                buf_filled_size_offset;
 334         bool                    buf_filled_size_valid;
 335
 336         unsigned                stride_in_dw;
 337 };
 338
 339 struct r600_streamout {
 340         struct r600_atom                begin_atom;
 341         bool                            begin_emitted;
 342         unsigned                        num_dw_for_end;
 343
 344         unsigned                        enabled_mask;
 345         unsigned                        num_targets;
 346         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 347
 348         unsigned                        append_bitmask;
 349         bool                            suspended;
 350
 351         /* External state which comes from the vertex shader,
 352          * it must be set explicitly when binding a shader. */
 353         unsigned                        *stride_in_dw;
 354         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 355
 356         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 357         unsigned                        hw_enabled_mask;
 358
 359         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 360         struct r600_atom                enable_atom;
 361         bool                            streamout_enabled;
 362         bool                            prims_gen_query_enabled;
 363         int                             num_prims_gen_queries;
 364 };
 365
 366 struct r600_ring {
 367         struct radeon_winsys_cs         *cs;
 368         void (*flush)(void *ctx, unsigned flags,
 369                       struct pipe_fence_handle **fence);
 370 };
 371
 372 struct r600_common_context {
 373         struct pipe_context b; /* base class */
 374
 375         struct r600_common_screen       *screen;
 376         struct radeon_winsys            *ws;
 377         struct radeon_winsys_ctx        *ctx;
 378         enum radeon_family              family;
 379         enum chip_class                 chip_class;
 380         struct r600_ring                gfx;
 381         struct r600_ring                dma;
 382         struct pipe_fence_handle        *last_sdma_fence;
 383         unsigned                        initial_gfx_cs_size;
 384         unsigned                        gpu_reset_counter;
 385
 386         struct u_upload_mgr             *uploader;
 387         struct u_suballocator           *allocator_so_filled_size;
 388         struct util_slab_mempool        pool_transfers;
 389
 390         /* Current unaccounted memory usage. */
 391         uint64_t                        vram;
 392         uint64_t                        gtt;
 393
 394         /* States. */
 395         struct r600_streamout           streamout;
 396
 397         /* Additional context states. */
 398         unsigned flags; /* flush flags */
 399
 400         /* Queries. */
 401         /* The list of active queries. Only one query of each type can be active. */
 402         int                             num_occlusion_queries;
 403         /* Keep track of non-timer queries, because they should be suspended
 404          * during context flushing.
 405          * The timer queries (TIME_ELAPSED) shouldn't be suspended for blits,
 406          * but they should be suspended between IBs. */
 407         struct list_head                active_nontimer_queries;
 408         struct list_head                active_timer_queries;
 409         unsigned                        num_cs_dw_nontimer_queries_suspend;
 410         unsigned                        num_cs_dw_timer_queries_suspend;
 411         /* If queries have been suspended. */
 412         bool                            queries_suspended_for_flush;
 413         /* Additional hardware info. */
 414         unsigned                        backend_mask;
 415         unsigned                        max_db; /* for OQ */
 416         /* Misc stats. */
 417         unsigned                        num_draw_calls;
 418
 419         /* Render condition. */
 420         struct r600_atom                render_cond_atom;
 421         struct pipe_query               *render_cond;
 422         unsigned                        render_cond_mode;
 423         boolean                         render_cond_invert;
 424         bool                            render_cond_force_off; /* for u_blitter */
 425
 426         /* MSAA sample locations.
 427          * The first index is the sample index.
 428          * The second index is the coordinate: X, Y. */
 429         float                           sample_locations_1x[1][2];
 430         float                           sample_locations_2x[2][2];
 431         float                           sample_locations_4x[4][2];
 432         float                           sample_locations_8x[8][2];
 433         float                           sample_locations_16x[16][2];
 434
 435         /* The list of all texture buffer objects in this context.
 436          * This list is walked when a buffer is invalidated/reallocated and
 437          * the GPU addresses are updated. */
 438         struct list_head                texture_buffers;
 439
 440         /* Copy one resource to another using async DMA. */
 441         void (*dma_copy)(struct pipe_context *ctx,
 442                          struct pipe_resource *dst,
 443                          unsigned dst_level,
 444                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 445                          struct pipe_resource *src,
 446                          unsigned src_level,
 447                          const struct pipe_box *src_box);
 448
 449         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 450                              unsigned offset, unsigned size, unsigned value,
 451                              bool is_framebuffer);
 452
 453         void (*blit_decompress_depth)(struct pipe_context *ctx,
 454                                       struct r600_texture *texture,
 455                                       struct r600_texture *staging,
 456                                       unsigned first_level, unsigned last_level,
 457                                       unsigned first_layer, unsigned last_layer,
 458                                       unsigned first_sample, unsigned last_sample);
 459
 460         /* Reallocate the buffer and update all resource bindings where
 461          * the buffer is bound, including all resource descriptors. */
 462         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 463
 464         /* Enable or disable occlusion queries. */
 465         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 466
 467         /* This ensures there is enough space in the command stream. */
 468         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 469                                   bool include_draw_vbo);
 470
 471         void (*set_atom_dirty)(struct r600_common_context *ctx,
 472                                struct r600_atom *atom, bool dirty);
 473 };
 474
 475 /* r600_buffer.c */
 476 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 477                                         struct radeon_winsys_cs_handle *buf,
 478                                         enum radeon_bo_usage usage);
 479 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 480                                       struct r600_resource *resource,
 481                                       unsigned usage);
 482 bool r600_init_resource(struct r600_common_screen *rscreen,
 483                         struct r600_resource *res,
 484                         unsigned size, unsigned alignment,
 485                         bool use_reusable_pool);
 486 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 487                                          const struct pipe_resource *templ,
 488                                          unsigned alignment);
 489 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
 490                                                   unsigned bind,
 491                                                   unsigned usage,
 492                                                   unsigned size,
 493                                                   unsigned alignment);
 494 struct pipe_resource *
 495 r600_buffer_from_user_memory(struct pipe_screen *screen,
 496                              const struct pipe_resource *templ,
 497                              void *user_memory);
 498
 499 /* r600_common_pipe.c */
 500 void r600_draw_rectangle(struct blitter_context *blitter,
 501                          int x1, int y1, int x2, int y2, float depth,
 502                          enum blitter_attrib_type type,
 503                          const union pipe_color_union *attrib);
 504 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 505                              struct radeon_winsys *ws);
 506 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 507 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 508 void r600_postflush_resume_features(struct r600_common_context *ctx);
 509 bool r600_common_context_init(struct r600_common_context *rctx,
 510                               struct r600_common_screen *rscreen);
 511 void r600_common_context_cleanup(struct r600_common_context *rctx);
 512 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 513 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 514                           const struct tgsi_token *tokens);
 515 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 516                               unsigned offset, unsigned size, unsigned value,
 517                               bool is_framebuffer);
 518 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 519                                                   const struct pipe_resource *templ);
 520 const char *r600_get_llvm_processor_name(enum radeon_family family);
 521 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw);
 522
 523 /* r600_gpu_load.c */
 524 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 525 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
 526 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 527
 528 /* r600_query.c */
 529 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
 530 void r600_query_init(struct r600_common_context *rctx);
 531 void r600_suspend_nontimer_queries(struct r600_common_context *ctx);
 532 void r600_resume_nontimer_queries(struct r600_common_context *ctx);
 533 void r600_suspend_timer_queries(struct r600_common_context *ctx);
 534 void r600_resume_timer_queries(struct r600_common_context *ctx);
 535 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 536
 537 /* r600_streamout.c */
 538 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 539 void r600_set_streamout_targets(struct pipe_context *ctx,
 540                                 unsigned num_targets,
 541                                 struct pipe_stream_output_target **targets,
 542                                 const unsigned *offset);
 543 void r600_emit_streamout_end(struct r600_common_context *rctx);
 544 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 545                                              unsigned type, int diff);
 546 void r600_streamout_init(struct r600_common_context *rctx);
 547
 548 /* r600_texture.c */
 549 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 550                                  struct r600_texture *rtex,
 551                                  unsigned nr_samples,
 552                                  struct r600_fmask_info *out);
 553 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 554                                  struct r600_texture *rtex,
 555                                  struct r600_cmask_info *out);
 556 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 557                                      struct pipe_resource *texture,
 558                                      struct r600_texture **staging);
 559 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 560                                         const struct pipe_resource *templ);
 561 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 562                                                 struct pipe_resource *texture,
 563                                                 const struct pipe_surface *templ,
 564                                                 unsigned width, unsigned height);
 565 unsigned r600_translate_colorswap(enum pipe_format format);
 566 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 567                                    struct pipe_framebuffer_state *fb,
 568                                    struct r600_atom *fb_state,
 569                                    unsigned *buffers, unsigned *dirty_cbufs,
 570                                    const union pipe_color_union *color);
 571 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 572 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 573
 574 /* cayman_msaa.c */
 575 extern const uint32_t eg_sample_locs_2x[4];
 576 extern const unsigned eg_max_dist_2x;
 577 extern const uint32_t eg_sample_locs_4x[4];
 578 extern const unsigned eg_max_dist_4x;
 579 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 580                                 unsigned sample_index, float *out_value);
 581 void cayman_init_msaa(struct pipe_context *ctx);
 582 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 583 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 584                              int ps_iter_samples, int overrast_samples);
 585
 586
 587 /* Inline helpers. */
 588
 589 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 590 {
 591         return (struct r600_resource*)r;
 592 }
 593
 594 static inline void
 595 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 596 {
 597         pipe_resource_reference((struct pipe_resource **)ptr,
 598                                 (struct pipe_resource *)res);
 599 }
 600
 601 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 602 {
 603         if (filter <= 1)   return 0;
 604         if (filter <= 2)   return 1;
 605         if (filter <= 4)   return 2;
 606         if (filter <= 8)   return 3;
 607          /* else */        return 4;
 608 }
 609
 610 static inline unsigned r600_wavefront_size(enum radeon_family family)
 611 {
 612         switch (family) {
 613         case CHIP_RV610:
 614         case CHIP_RS780:
 615         case CHIP_RV620:
 616         case CHIP_RS880:
 617                 return 16;
 618         case CHIP_RV630:
 619         case CHIP_RV635:
 620         case CHIP_RV730:
 621         case CHIP_RV710:
 622         case CHIP_PALM:
 623         case CHIP_CEDAR:
 624                 return 32;
 625         default:
 626                 return 64;
 627         }
 628 }
 629
 630 static inline enum radeon_bo_priority
 631 r600_get_sampler_view_priority(struct r600_resource *res)
 632 {
 633         if (res->b.b.target == PIPE_BUFFER)
 634                 return RADEON_PRIO_SAMPLER_BUFFER;
 635
 636         if (res->b.b.nr_samples > 1)
 637                 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
 638
 639         return RADEON_PRIO_SAMPLER_TEXTURE;
 640 }
 641
 642 #define COMPUTE_DBG(rscreen, fmt, args...) \
 643         do { \
 644                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 645         } while (0);
 646
 647 #define R600_ERR(fmt, args...) \
 648         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
 649
 650 /* For MSAA sample positions. */
 651 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 652         (((s0x) & 0xf) | (((s0y) & 0xf) << 4) |            \
 653         (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |     \
 654         (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |    \
 655          (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
 656
 657 #endif