src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/u_slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  47 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  48 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  49
  50 #define R600_QUERY_DRAW_CALLS           (PIPE_QUERY_DRIVER_SPECIFIC + 0)
  51 #define R600_QUERY_REQUESTED_VRAM       (PIPE_QUERY_DRIVER_SPECIFIC + 1)
  52 #define R600_QUERY_REQUESTED_GTT        (PIPE_QUERY_DRIVER_SPECIFIC + 2)
  53 #define R600_QUERY_BUFFER_WAIT_TIME     (PIPE_QUERY_DRIVER_SPECIFIC + 3)
  54 #define R600_QUERY_NUM_CS_FLUSHES       (PIPE_QUERY_DRIVER_SPECIFIC + 4)
  55 #define R600_QUERY_NUM_BYTES_MOVED      (PIPE_QUERY_DRIVER_SPECIFIC + 5)
  56 #define R600_QUERY_VRAM_USAGE           (PIPE_QUERY_DRIVER_SPECIFIC + 6)
  57 #define R600_QUERY_GTT_USAGE            (PIPE_QUERY_DRIVER_SPECIFIC + 7)
  58 #define R600_QUERY_GPU_TEMPERATURE      (PIPE_QUERY_DRIVER_SPECIFIC + 8)
  59 #define R600_QUERY_CURRENT_GPU_SCLK     (PIPE_QUERY_DRIVER_SPECIFIC + 9)
  60 #define R600_QUERY_CURRENT_GPU_MCLK     (PIPE_QUERY_DRIVER_SPECIFIC + 10)
  61 #define R600_QUERY_GPU_LOAD             (PIPE_QUERY_DRIVER_SPECIFIC + 11)
  62
  63 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  64 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 1)
  65
  66 /* special primitive types */
  67 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  68
  69 /* Debug flags. */
  70 /* logging */
  71 #define DBG_TEX                 (1 << 0)
  72 #define DBG_TEXMIP              (1 << 1)
  73 #define DBG_COMPUTE             (1 << 2)
  74 #define DBG_VM                  (1 << 3)
  75 #define DBG_TRACE_CS            (1 << 4)
  76 /* shader logging */
  77 #define DBG_FS                  (1 << 5)
  78 #define DBG_VS                  (1 << 6)
  79 #define DBG_GS                  (1 << 7)
  80 #define DBG_PS                  (1 << 8)
  81 #define DBG_CS                  (1 << 9)
  82 #define DBG_TCS                 (1 << 10)
  83 #define DBG_TES                 (1 << 11)
  84 /* features */
  85 #define DBG_NO_ASYNC_DMA        (1 << 12)
  86 #define DBG_NO_HYPERZ           (1 << 13)
  87 #define DBG_NO_DISCARD_RANGE    (1 << 14)
  88 #define DBG_NO_2D_TILING        (1 << 15)
  89 #define DBG_NO_TILING           (1 << 16)
  90 #define DBG_SWITCH_ON_EOP       (1 << 17)
  91 #define DBG_FORCE_DMA           (1 << 18)
  92 #define DBG_PRECOMPILE          (1 << 19)
  93 #define DBG_INFO                (1 << 20)
  94 /* The maximum allowed bit is 20. */
  95
  96 #define R600_MAP_BUFFER_ALIGNMENT 64
  97
  98 struct r600_common_context;
  99
 100 struct radeon_shader_reloc {
 101         char *name;
 102         uint64_t offset;
 103 };
 104
 105 struct radeon_shader_binary {
 106         /** Shader code */
 107         unsigned char *code;
 108         unsigned code_size;
 109
 110         /** Config/Context register state that accompanies this shader.
 111          * This is a stream of dword pairs.  First dword contains the
 112          * register address, the second dword contains the value.*/
 113         unsigned char *config;
 114         unsigned config_size;
 115
 116         /** The number of bytes of config information for each global symbol.
 117          */
 118         unsigned config_size_per_symbol;
 119
 120         /** Constant data accessed by the shader.  This will be uploaded
 121          * into a constant buffer. */
 122         unsigned char *rodata;
 123         unsigned rodata_size;
 124
 125         /** List of symbol offsets for the shader */
 126         uint64_t *global_symbol_offsets;
 127         unsigned global_symbol_count;
 128
 129         struct radeon_shader_reloc *relocs;
 130         unsigned reloc_count;
 131
 132         /** Disassembled shader in a string. */
 133         char *disasm_string;
 134 };
 135
 136 struct r600_resource {
 137         struct u_resource               b;
 138
 139         /* Winsys objects. */
 140         struct pb_buffer                *buf;
 141         struct radeon_winsys_cs_handle  *cs_buf;
 142         uint64_t                        gpu_address;
 143
 144         /* Resource state. */
 145         enum radeon_bo_domain           domains;
 146
 147         /* The buffer range which is initialized (with a write transfer,
 148          * streamout, DMA, or as a random access target). The rest of
 149          * the buffer is considered invalid and can be mapped unsynchronized.
 150          *
 151          * This allows unsychronized mapping of a buffer range which hasn't
 152          * been used yet. It's for applications which forget to use
 153          * the unsynchronized map flag and expect the driver to figure it out.
 154          */
 155         struct util_range               valid_buffer_range;
 156
 157         /* For buffers only. This indicates that a write operation has been
 158          * performed by TC L2, but the cache hasn't been flushed.
 159          * Any hw block which doesn't use or bypasses TC L2 should check this
 160          * flag and flush the cache before using the buffer.
 161          *
 162          * For example, TC L2 must be flushed if a buffer which has been
 163          * modified by a shader store instruction is about to be used as
 164          * an index buffer. The reason is that VGT DMA index fetching doesn't
 165          * use TC L2.
 166          */
 167         bool                            TC_L2_dirty;
 168 };
 169
 170 struct r600_transfer {
 171         struct pipe_transfer            transfer;
 172         struct r600_resource            *staging;
 173         unsigned                        offset;
 174 };
 175
 176 struct r600_fmask_info {
 177         unsigned offset;
 178         unsigned size;
 179         unsigned alignment;
 180         unsigned pitch;
 181         unsigned bank_height;
 182         unsigned slice_tile_max;
 183         unsigned tile_mode_index;
 184 };
 185
 186 struct r600_cmask_info {
 187         unsigned offset;
 188         unsigned size;
 189         unsigned alignment;
 190         unsigned slice_tile_max;
 191         unsigned base_address_reg;
 192 };
 193
 194 struct r600_texture {
 195         struct r600_resource            resource;
 196
 197         unsigned                        size;
 198         unsigned                        pitch_override;
 199         bool                            is_depth;
 200         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 201         struct r600_texture             *flushed_depth_texture;
 202         boolean                         is_flushing_texture;
 203         struct radeon_surf              surface;
 204
 205         /* Colorbuffer compression and fast clear. */
 206         struct r600_fmask_info          fmask;
 207         struct r600_cmask_info          cmask;
 208         struct r600_resource            *cmask_buffer;
 209         unsigned                        cb_color_info; /* fast clear enable bit */
 210         unsigned                        color_clear_value[2];
 211
 212         /* Depth buffer compression and fast clear. */
 213         struct r600_resource            *htile_buffer;
 214         bool                            depth_cleared; /* if it was cleared at least once */
 215         float                           depth_clear_value;
 216
 217         bool                            non_disp_tiling; /* R600-Cayman only */
 218 };
 219
 220 struct r600_surface {
 221         struct pipe_surface             base;
 222
 223         bool color_initialized;
 224         bool depth_initialized;
 225
 226         /* Misc. color flags. */
 227         bool alphatest_bypass;
 228         bool export_16bpc;
 229
 230         /* Color registers. */
 231         unsigned cb_color_info;
 232         unsigned cb_color_base;
 233         unsigned cb_color_view;
 234         unsigned cb_color_size;         /* R600 only */
 235         unsigned cb_color_dim;          /* EG only */
 236         unsigned cb_color_pitch;        /* EG and later */
 237         unsigned cb_color_slice;        /* EG and later */
 238         unsigned cb_color_attrib;       /* EG and later */
 239         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 240         unsigned cb_color_fmask_slice;  /* EG and later */
 241         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 242         unsigned cb_color_mask;         /* R600 only */
 243         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 244         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 245
 246         /* DB registers. */
 247         unsigned db_depth_info;         /* R600 only, then SI and later */
 248         unsigned db_z_info;             /* EG and later */
 249         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 250         unsigned db_depth_view;
 251         unsigned db_depth_size;
 252         unsigned db_depth_slice;        /* EG and later */
 253         unsigned db_stencil_base;       /* EG and later */
 254         unsigned db_stencil_info;       /* EG and later */
 255         unsigned db_prefetch_limit;     /* R600 only */
 256         unsigned db_htile_surface;
 257         unsigned db_htile_data_base;
 258         unsigned db_preload_control;    /* EG and later */
 259         unsigned pa_su_poly_offset_db_fmt_cntl;
 260 };
 261
 262 struct r600_tiling_info {
 263         unsigned num_channels;
 264         unsigned num_banks;
 265         unsigned group_bytes;
 266 };
 267
 268 struct r600_common_screen {
 269         struct pipe_screen              b;
 270         struct radeon_winsys            *ws;
 271         enum radeon_family              family;
 272         enum chip_class                 chip_class;
 273         struct radeon_info              info;
 274         struct r600_tiling_info         tiling_info;
 275         unsigned                        debug_flags;
 276         bool                            has_cp_dma;
 277         bool                            has_streamout;
 278
 279         /* Auxiliary context. Mainly used to initialize resources.
 280          * It must be locked prior to using and flushed before unlocking. */
 281         struct pipe_context             *aux_context;
 282         pipe_mutex                      aux_context_lock;
 283
 284         struct r600_resource            *trace_bo;
 285         uint32_t                        *trace_ptr;
 286         unsigned                        cs_count;
 287
 288         /* GPU load thread. */
 289         pipe_mutex                      gpu_load_mutex;
 290         pipe_thread                     gpu_load_thread;
 291         unsigned                        gpu_load_counter_busy;
 292         unsigned                        gpu_load_counter_idle;
 293         volatile unsigned               gpu_load_stop_thread; /* bool */
 294 };
 295
 296 /* This encapsulates a state or an operation which can emitted into the GPU
 297  * command stream. */
 298 struct r600_atom {
 299         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 300         unsigned                num_dw;
 301         bool                    dirty;
 302 };
 303
 304 struct r600_so_target {
 305         struct pipe_stream_output_target b;
 306
 307         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 308         struct r600_resource    *buf_filled_size;
 309         unsigned                buf_filled_size_offset;
 310         bool                    buf_filled_size_valid;
 311
 312         unsigned                stride_in_dw;
 313 };
 314
 315 struct r600_streamout {
 316         struct r600_atom                begin_atom;
 317         bool                            begin_emitted;
 318         unsigned                        num_dw_for_end;
 319
 320         unsigned                        enabled_mask;
 321         unsigned                        num_targets;
 322         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 323
 324         unsigned                        append_bitmask;
 325         bool                            suspended;
 326
 327         /* External state which comes from the vertex shader,
 328          * it must be set explicitly when binding a shader. */
 329         unsigned                        *stride_in_dw;
 330         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 331
 332         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 333         unsigned                        hw_enabled_mask;
 334
 335         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 336         struct r600_atom                enable_atom;
 337         bool                            streamout_enabled;
 338         bool                            prims_gen_query_enabled;
 339         int                             num_prims_gen_queries;
 340 };
 341
 342 struct r600_ring {
 343         struct radeon_winsys_cs         *cs;
 344         bool                            flushing;
 345         void (*flush)(void *ctx, unsigned flags,
 346                       struct pipe_fence_handle **fence);
 347 };
 348
 349 struct r600_rings {
 350         struct r600_ring                gfx;
 351         struct r600_ring                dma;
 352 };
 353
 354 struct r600_common_context {
 355         struct pipe_context b; /* base class */
 356
 357         struct r600_common_screen       *screen;
 358         struct radeon_winsys            *ws;
 359         enum radeon_family              family;
 360         enum chip_class                 chip_class;
 361         struct r600_rings               rings;
 362         unsigned                        initial_gfx_cs_size;
 363         unsigned                        gpu_reset_counter;
 364
 365         struct u_upload_mgr             *uploader;
 366         struct u_suballocator           *allocator_so_filled_size;
 367         struct util_slab_mempool        pool_transfers;
 368
 369         /* Current unaccounted memory usage. */
 370         uint64_t                        vram;
 371         uint64_t                        gtt;
 372
 373         /* States. */
 374         struct r600_streamout           streamout;
 375
 376         /* Additional context states. */
 377         unsigned flags; /* flush flags */
 378
 379         /* Queries. */
 380         /* The list of active queries. Only one query of each type can be active. */
 381         int                             num_occlusion_queries;
 382         /* Keep track of non-timer queries, because they should be suspended
 383          * during context flushing.
 384          * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
 385         struct list_head                active_nontimer_queries;
 386         unsigned                        num_cs_dw_nontimer_queries_suspend;
 387         /* If queries have been suspended. */
 388         bool                            nontimer_queries_suspended;
 389         /* Additional hardware info. */
 390         unsigned                        backend_mask;
 391         unsigned                        max_db; /* for OQ */
 392         /* Misc stats. */
 393         unsigned                        num_draw_calls;
 394
 395         /* Render condition. */
 396         struct pipe_query               *current_render_cond;
 397         unsigned                        current_render_cond_mode;
 398         boolean                         current_render_cond_cond;
 399         boolean                         predicate_drawing;
 400         /* For context flushing. */
 401         struct pipe_query               *saved_render_cond;
 402         boolean                         saved_render_cond_cond;
 403         unsigned                        saved_render_cond_mode;
 404
 405         /* MSAA sample locations.
 406          * The first index is the sample index.
 407          * The second index is the coordinate: X, Y. */
 408         float                           sample_locations_1x[1][2];
 409         float                           sample_locations_2x[2][2];
 410         float                           sample_locations_4x[4][2];
 411         float                           sample_locations_8x[8][2];
 412         float                           sample_locations_16x[16][2];
 413
 414         /* The list of all texture buffer objects in this context.
 415          * This list is walked when a buffer is invalidated/reallocated and
 416          * the GPU addresses are updated. */
 417         struct list_head                texture_buffers;
 418
 419         /* Copy one resource to another using async DMA. */
 420         void (*dma_copy)(struct pipe_context *ctx,
 421                          struct pipe_resource *dst,
 422                          unsigned dst_level,
 423                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 424                          struct pipe_resource *src,
 425                          unsigned src_level,
 426                          const struct pipe_box *src_box);
 427
 428         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 429                              unsigned offset, unsigned size, unsigned value,
 430                              bool is_framebuffer);
 431
 432         void (*blit_decompress_depth)(struct pipe_context *ctx,
 433                                       struct r600_texture *texture,
 434                                       struct r600_texture *staging,
 435                                       unsigned first_level, unsigned last_level,
 436                                       unsigned first_layer, unsigned last_layer,
 437                                       unsigned first_sample, unsigned last_sample);
 438
 439         /* Reallocate the buffer and update all resource bindings where
 440          * the buffer is bound, including all resource descriptors. */
 441         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 442
 443         /* Enable or disable occlusion queries. */
 444         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 445
 446         /* This ensures there is enough space in the command stream. */
 447         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 448                                   bool include_draw_vbo);
 449 };
 450
 451 /* r600_buffer.c */
 452 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 453                                         struct radeon_winsys_cs_handle *buf,
 454                                         enum radeon_bo_usage usage);
 455 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 456                                       struct r600_resource *resource,
 457                                       unsigned usage);
 458 bool r600_init_resource(struct r600_common_screen *rscreen,
 459                         struct r600_resource *res,
 460                         unsigned size, unsigned alignment,
 461                         bool use_reusable_pool);
 462 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 463                                          const struct pipe_resource *templ,
 464                                          unsigned alignment);
 465 struct pipe_resource *
 466 r600_buffer_from_user_memory(struct pipe_screen *screen,
 467                              const struct pipe_resource *templ,
 468                              void *user_memory);
 469
 470 /* r600_common_pipe.c */
 471 void r600_draw_rectangle(struct blitter_context *blitter,
 472                          int x1, int y1, int x2, int y2, float depth,
 473                          enum blitter_attrib_type type,
 474                          const union pipe_color_union *attrib);
 475 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 476                              struct radeon_winsys *ws);
 477 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 478 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 479 void r600_postflush_resume_features(struct r600_common_context *ctx);
 480 bool r600_common_context_init(struct r600_common_context *rctx,
 481                               struct r600_common_screen *rscreen);
 482 void r600_common_context_cleanup(struct r600_common_context *rctx);
 483 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 484 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 485                           const struct tgsi_token *tokens);
 486 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 487                               unsigned offset, unsigned size, unsigned value,
 488                               bool is_framebuffer);
 489 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 490                                                   const struct pipe_resource *templ);
 491 const char *r600_get_llvm_processor_name(enum radeon_family family);
 492 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw);
 493
 494 /* r600_gpu_load.c */
 495 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 496 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
 497 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 498
 499 /* r600_query.c */
 500 void r600_query_init(struct r600_common_context *rctx);
 501 void r600_suspend_nontimer_queries(struct r600_common_context *ctx);
 502 void r600_resume_nontimer_queries(struct r600_common_context *ctx);
 503 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 504
 505 /* r600_streamout.c */
 506 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 507 void r600_set_streamout_targets(struct pipe_context *ctx,
 508                                 unsigned num_targets,
 509                                 struct pipe_stream_output_target **targets,
 510                                 const unsigned *offset);
 511 void r600_emit_streamout_end(struct r600_common_context *rctx);
 512 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 513                                              unsigned type, int diff);
 514 void r600_streamout_init(struct r600_common_context *rctx);
 515
 516 /* r600_texture.c */
 517 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 518                                  struct r600_texture *rtex,
 519                                  unsigned nr_samples,
 520                                  struct r600_fmask_info *out);
 521 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 522                                  struct r600_texture *rtex,
 523                                  struct r600_cmask_info *out);
 524 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 525                                      struct pipe_resource *texture,
 526                                      struct r600_texture **staging);
 527 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 528                                         const struct pipe_resource *templ);
 529 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 530                                                 struct pipe_resource *texture,
 531                                                 const struct pipe_surface *templ,
 532                                                 unsigned width, unsigned height);
 533 unsigned r600_translate_colorswap(enum pipe_format format);
 534 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 535                                    struct pipe_framebuffer_state *fb,
 536                                    struct r600_atom *fb_state,
 537                                    unsigned *buffers,
 538                                    const union pipe_color_union *color);
 539 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 540 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 541
 542 /* cayman_msaa.c */
 543 extern const uint32_t eg_sample_locs_2x[4];
 544 extern const unsigned eg_max_dist_2x;
 545 extern const uint32_t eg_sample_locs_4x[4];
 546 extern const unsigned eg_max_dist_4x;
 547 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 548                                 unsigned sample_index, float *out_value);
 549 void cayman_init_msaa(struct pipe_context *ctx);
 550 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 551 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 552                              int ps_iter_samples, int overrast_samples);
 553
 554
 555 /* Inline helpers. */
 556
 557 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 558 {
 559         return (struct r600_resource*)r;
 560 }
 561
 562 static inline void
 563 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 564 {
 565         pipe_resource_reference((struct pipe_resource **)ptr,
 566                                 (struct pipe_resource *)res);
 567 }
 568
 569 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 570 {
 571         if (filter <= 1)   return 0;
 572         if (filter <= 2)   return 1;
 573         if (filter <= 4)   return 2;
 574         if (filter <= 8)   return 3;
 575          /* else */        return 4;
 576 }
 577
 578 static inline unsigned r600_wavefront_size(enum radeon_family family)
 579 {
 580         switch (family) {
 581         case CHIP_RV610:
 582         case CHIP_RS780:
 583         case CHIP_RV620:
 584         case CHIP_RS880:
 585                 return 16;
 586         case CHIP_RV630:
 587         case CHIP_RV635:
 588         case CHIP_RV730:
 589         case CHIP_RV710:
 590         case CHIP_PALM:
 591         case CHIP_CEDAR:
 592                 return 32;
 593         default:
 594                 return 64;
 595         }
 596 }
 597
 598 #define COMPUTE_DBG(rscreen, fmt, args...) \
 599         do { \
 600                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 601         } while (0);
 602
 603 #define R600_ERR(fmt, args...) \
 604         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
 605
 606 /* For MSAA sample positions. */
 607 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 608         (((s0x) & 0xf) | (((s0y) & 0xf) << 4) |            \
 609         (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |     \
 610         (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |    \
 611          (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
 612
 613 #endif