src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "../../winsys/radeon/drm/radeon_winsys.h"
  38
  39 #include "util/u_double_list.h"
  40 #include "util/u_range.h"
  41 #include "util/u_slab.h"
  42 #include "util/u_suballoc.h"
  43 #include "util/u_transfer.h"
  44
  45 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  46 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  47 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  48
  49 #define R600_QUERY_DRAW_CALLS           (PIPE_QUERY_DRIVER_SPECIFIC + 0)
  50 #define R600_QUERY_REQUESTED_VRAM       (PIPE_QUERY_DRIVER_SPECIFIC + 1)
  51 #define R600_QUERY_REQUESTED_GTT        (PIPE_QUERY_DRIVER_SPECIFIC + 2)
  52 #define R600_QUERY_BUFFER_WAIT_TIME     (PIPE_QUERY_DRIVER_SPECIFIC + 3)
  53
  54 /* read caches */
  55 #define R600_CONTEXT_INV_VERTEX_CACHE           (1 << 0)
  56 #define R600_CONTEXT_INV_TEX_CACHE              (1 << 1)
  57 #define R600_CONTEXT_INV_CONST_CACHE            (1 << 2)
  58 #define R600_CONTEXT_INV_SHADER_CACHE           (1 << 3)
  59 /* read-write caches */
  60 #define R600_CONTEXT_STREAMOUT_FLUSH            (1 << 8)
  61 #define R600_CONTEXT_FLUSH_AND_INV              (1 << 9)
  62 #define R600_CONTEXT_FLUSH_AND_INV_CB_META      (1 << 10)
  63 #define R600_CONTEXT_FLUSH_AND_INV_DB_META      (1 << 11)
  64 #define R600_CONTEXT_FLUSH_AND_INV_DB           (1 << 12)
  65 #define R600_CONTEXT_FLUSH_AND_INV_CB           (1 << 13)
  66 /* engine synchronization */
  67 #define R600_CONTEXT_PS_PARTIAL_FLUSH           (1 << 16)
  68 #define R600_CONTEXT_WAIT_3D_IDLE               (1 << 17)
  69 #define R600_CONTEXT_WAIT_CP_DMA_IDLE           (1 << 18)
  70 #define R600_CONTEXT_VGT_FLUSH                  (1 << 19)
  71
  72 /* Debug flags. */
  73 /* logging */
  74 #define DBG_TEX                 (1 << 0)
  75 #define DBG_TEXMIP              (1 << 1)
  76 #define DBG_COMPUTE             (1 << 2)
  77 #define DBG_VM                  (1 << 3)
  78 #define DBG_TRACE_CS            (1 << 4)
  79 /* shaders */
  80 #define DBG_FS                  (1 << 8)
  81 #define DBG_VS                  (1 << 9)
  82 #define DBG_GS                  (1 << 10)
  83 #define DBG_PS                  (1 << 11)
  84 #define DBG_CS                  (1 << 12)
  85 /* features */
  86 #define DBG_HYPERZ              (1 << 13)
  87 #define DBG_NO_DISCARD_RANGE    (1 << 14)
  88 /* The maximum allowed bit is 15. */
  89
  90 #define R600_MAP_BUFFER_ALIGNMENT 64
  91
  92 struct r600_common_context;
  93
  94 struct radeon_shader_binary {
  95         /** Shader code */
  96         unsigned char *code;
  97         unsigned code_size;
  98
  99         /** Config/Context register state that accompanies this shader.
 100          * This is a stream of dword pairs.  First dword contains the
 101          * register address, the second dword contains the value.*/
 102         unsigned char *config;
 103         unsigned config_size;
 104
 105         /** Set to 1 if the disassembly for this binary has been dumped to
 106          *  stderr. */
 107         int disassembled;
 108 };
 109
 110 struct r600_resource {
 111         struct u_resource               b;
 112
 113         /* Winsys objects. */
 114         struct pb_buffer                *buf;
 115         struct radeon_winsys_cs_handle  *cs_buf;
 116
 117         /* Resource state. */
 118         enum radeon_bo_domain           domains;
 119
 120         /* The buffer range which is initialized (with a write transfer,
 121          * streamout, DMA, or as a random access target). The rest of
 122          * the buffer is considered invalid and can be mapped unsynchronized.
 123          *
 124          * This allows unsychronized mapping of a buffer range which hasn't
 125          * been used yet. It's for applications which forget to use
 126          * the unsynchronized map flag and expect the driver to figure it out.
 127          */
 128         struct util_range               valid_buffer_range;
 129 };
 130
 131 struct r600_transfer {
 132         struct pipe_transfer            transfer;
 133         struct r600_resource            *staging;
 134         unsigned                        offset;
 135 };
 136
 137 struct r600_fmask_info {
 138         unsigned offset;
 139         unsigned size;
 140         unsigned alignment;
 141         unsigned pitch;
 142         unsigned bank_height;
 143         unsigned slice_tile_max;
 144         unsigned tile_mode_index;
 145 };
 146
 147 struct r600_cmask_info {
 148         unsigned offset;
 149         unsigned size;
 150         unsigned alignment;
 151         unsigned slice_tile_max;
 152         unsigned base_address_reg;
 153 };
 154
 155 struct r600_texture {
 156         struct r600_resource            resource;
 157
 158         unsigned                        size;
 159         unsigned                        pitch_override;
 160         bool                            is_depth;
 161         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 162         struct r600_texture             *flushed_depth_texture;
 163         boolean                         is_flushing_texture;
 164         struct radeon_surface           surface;
 165
 166         /* Colorbuffer compression and fast clear. */
 167         struct r600_fmask_info          fmask;
 168         struct r600_cmask_info          cmask;
 169         struct r600_resource            *cmask_buffer;
 170         unsigned                        cb_color_info; /* fast clear enable bit */
 171         unsigned                        color_clear_value[2];
 172
 173         /* Depth buffer compression and fast clear. */
 174         struct r600_resource            *htile_buffer;
 175         float                           depth_clear_value;
 176
 177         bool                            non_disp_tiling; /* R600-Cayman only */
 178         unsigned                        mipmap_shift;
 179 };
 180
 181 struct r600_surface {
 182         struct pipe_surface             base;
 183
 184         bool color_initialized;
 185         bool depth_initialized;
 186
 187         /* Misc. color flags. */
 188         bool alphatest_bypass;
 189         bool export_16bpc;
 190
 191         /* Color registers. */
 192         unsigned cb_color_info;
 193         unsigned cb_color_base;
 194         unsigned cb_color_view;
 195         unsigned cb_color_size;         /* R600 only */
 196         unsigned cb_color_dim;          /* EG only */
 197         unsigned cb_color_pitch;        /* EG and later */
 198         unsigned cb_color_slice;        /* EG and later */
 199         unsigned cb_color_attrib;       /* EG and later */
 200         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 201         unsigned cb_color_fmask_slice;  /* EG and later */
 202         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 203         unsigned cb_color_mask;         /* R600 only */
 204         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 205         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 206
 207         /* DB registers. */
 208         unsigned db_depth_info;         /* R600 only, then SI and later */
 209         unsigned db_z_info;             /* EG and later */
 210         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 211         unsigned db_depth_view;
 212         unsigned db_depth_size;
 213         unsigned db_depth_slice;        /* EG and later */
 214         unsigned db_stencil_base;       /* EG and later */
 215         unsigned db_stencil_info;       /* EG and later */
 216         unsigned db_prefetch_limit;     /* R600 only */
 217         unsigned db_htile_surface;
 218         unsigned db_htile_data_base;
 219         unsigned db_preload_control;    /* EG and later */
 220         unsigned pa_su_poly_offset_db_fmt_cntl;
 221 };
 222
 223 struct r600_tiling_info {
 224         unsigned num_channels;
 225         unsigned num_banks;
 226         unsigned group_bytes;
 227 };
 228
 229 struct r600_common_screen {
 230         struct pipe_screen              b;
 231         struct radeon_winsys            *ws;
 232         enum radeon_family              family;
 233         enum chip_class                 chip_class;
 234         struct radeon_info              info;
 235         struct r600_tiling_info         tiling_info;
 236         unsigned                        debug_flags;
 237         bool                            has_cp_dma;
 238         bool                            has_streamout;
 239
 240         /* Auxiliary context. Mainly used to initialize resources.
 241          * It must be locked prior to using and flushed before unlocking. */
 242         struct pipe_context             *aux_context;
 243         pipe_mutex                      aux_context_lock;
 244
 245         struct r600_resource            *trace_bo;
 246         uint32_t                        *trace_ptr;
 247         unsigned                        cs_count;
 248 };
 249
 250 /* This encapsulates a state or an operation which can emitted into the GPU
 251  * command stream. */
 252 struct r600_atom {
 253         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 254         unsigned                num_dw;
 255         bool                    dirty;
 256 };
 257
 258 struct r600_so_target {
 259         struct pipe_stream_output_target b;
 260
 261         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 262         struct r600_resource    *buf_filled_size;
 263         unsigned                buf_filled_size_offset;
 264
 265         unsigned                stride_in_dw;
 266 };
 267
 268 struct r600_streamout {
 269         struct r600_atom                begin_atom;
 270         bool                            begin_emitted;
 271         unsigned                        num_dw_for_end;
 272
 273         unsigned                        enabled_mask;
 274         unsigned                        num_targets;
 275         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 276
 277         unsigned                        append_bitmask;
 278         bool                            suspended;
 279
 280         /* External state which comes from the vertex shader,
 281          * it must be set explicitly when binding a shader. */
 282         unsigned                        *stride_in_dw;
 283 };
 284
 285 struct r600_ring {
 286         struct radeon_winsys_cs         *cs;
 287         bool                            flushing;
 288         void (*flush)(void *ctx, unsigned flags);
 289 };
 290
 291 struct r600_rings {
 292         struct r600_ring                gfx;
 293         struct r600_ring                dma;
 294 };
 295
 296 struct r600_common_context {
 297         struct pipe_context b; /* base class */
 298
 299         struct r600_common_screen       *screen;
 300         struct radeon_winsys            *ws;
 301         enum radeon_family              family;
 302         enum chip_class                 chip_class;
 303         struct r600_rings               rings;
 304         unsigned                        initial_gfx_cs_size;
 305
 306         struct u_upload_mgr             *uploader;
 307         struct u_suballocator           *allocator_so_filled_size;
 308         struct util_slab_mempool        pool_transfers;
 309
 310         /* Current unaccounted memory usage. */
 311         uint64_t                        vram;
 312         uint64_t                        gtt;
 313
 314         /* States. */
 315         struct r600_streamout           streamout;
 316
 317         /* Additional context states. */
 318         unsigned flags; /* flush flags */
 319
 320         /* Queries. */
 321         /* The list of active queries. Only one query of each type can be active. */
 322         int                             num_occlusion_queries;
 323         int                             num_pipelinestat_queries;
 324         /* Keep track of non-timer queries, because they should be suspended
 325          * during context flushing.
 326          * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
 327         struct list_head                active_nontimer_queries;
 328         unsigned                        num_cs_dw_nontimer_queries_suspend;
 329         /* If queries have been suspended. */
 330         bool                            nontimer_queries_suspended;
 331         /* Additional hardware info. */
 332         unsigned                        backend_mask;
 333         unsigned                        max_db; /* for OQ */
 334         /* Misc stats. */
 335         unsigned                        num_draw_calls;
 336
 337         /* Render condition. */
 338         struct pipe_query               *current_render_cond;
 339         unsigned                        current_render_cond_mode;
 340         boolean                         current_render_cond_cond;
 341         boolean                         predicate_drawing;
 342
 343         /* Copy one resource to another using async DMA.
 344          * False is returned if the copy couldn't be done. */
 345         boolean (*dma_copy)(struct pipe_context *ctx,
 346                             struct pipe_resource *dst,
 347                             unsigned dst_level,
 348                             unsigned dst_x, unsigned dst_y, unsigned dst_z,
 349                             struct pipe_resource *src,
 350                             unsigned src_level,
 351                             const struct pipe_box *src_box);
 352
 353         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 354                              unsigned offset, unsigned size, unsigned value);
 355
 356         void (*blit_decompress_depth)(struct pipe_context *ctx,
 357                                       struct r600_texture *texture,
 358                                       struct r600_texture *staging,
 359                                       unsigned first_level, unsigned last_level,
 360                                       unsigned first_layer, unsigned last_layer,
 361                                       unsigned first_sample, unsigned last_sample);
 362
 363         /* Reallocate the buffer and update all resource bindings where
 364          * the buffer is bound, including all resource descriptors. */
 365         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 366
 367         /* Enable or disable occlusion queries. */
 368         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 369
 370         /* This ensures there is enough space in the command stream. */
 371         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 372                                   bool include_draw_vbo);
 373 };
 374
 375 /* r600_buffer.c */
 376 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 377                                         struct radeon_winsys_cs_handle *buf,
 378                                         enum radeon_bo_usage usage);
 379 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 380                                       struct r600_resource *resource,
 381                                       unsigned usage);
 382 bool r600_init_resource(struct r600_common_screen *rscreen,
 383                         struct r600_resource *res,
 384                         unsigned size, unsigned alignment,
 385                         bool use_reusable_pool);
 386 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 387                                          const struct pipe_resource *templ,
 388                                          unsigned alignment);
 389
 390 /* r600_common_pipe.c */
 391 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 392                              struct radeon_winsys *ws);
 393 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 394 bool r600_common_context_init(struct r600_common_context *rctx,
 395                               struct r600_common_screen *rscreen);
 396 void r600_common_context_cleanup(struct r600_common_context *rctx);
 397 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 398 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 399                           const struct tgsi_token *tokens);
 400 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 401                               unsigned offset, unsigned size, unsigned value);
 402 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 403                                                   const struct pipe_resource *templ);
 404 const char *r600_get_llvm_processor_name(enum radeon_family family);
 405
 406 /* r600_query.c */
 407 void r600_query_init(struct r600_common_context *rctx);
 408 void r600_suspend_nontimer_queries(struct r600_common_context *ctx);
 409 void r600_resume_nontimer_queries(struct r600_common_context *ctx);
 410 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 411
 412 /* r600_streamout.c */
 413 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 414 void r600_set_streamout_targets(struct pipe_context *ctx,
 415                                 unsigned num_targets,
 416                                 struct pipe_stream_output_target **targets,
 417                                 const unsigned *offset);
 418 void r600_emit_streamout_end(struct r600_common_context *rctx);
 419 void r600_streamout_init(struct r600_common_context *rctx);
 420
 421 /* r600_texture.c */
 422 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 423                                  struct r600_texture *rtex,
 424                                  unsigned nr_samples,
 425                                  struct r600_fmask_info *out);
 426 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 427                                  struct r600_texture *rtex,
 428                                  struct r600_cmask_info *out);
 429 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 430                                      struct pipe_resource *texture,
 431                                      struct r600_texture **staging);
 432 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 433                                         const struct pipe_resource *templ);
 434 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 435                                                 struct pipe_resource *texture,
 436                                                 const struct pipe_surface *templ,
 437                                                 unsigned width, unsigned height);
 438 unsigned r600_translate_colorswap(enum pipe_format format);
 439 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 440                                    struct pipe_framebuffer_state *fb,
 441                                    struct r600_atom *fb_state,
 442                                    unsigned *buffers,
 443                                    const union pipe_color_union *color);
 444 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 445 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 446
 447 /* cayman_msaa.c */
 448 extern const uint32_t eg_sample_locs_2x[4];
 449 extern const unsigned eg_max_dist_2x;
 450 extern const uint32_t eg_sample_locs_4x[4];
 451 extern const unsigned eg_max_dist_4x;
 452 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 453                                 unsigned sample_index, float *out_value);
 454 void cayman_emit_msaa_state(struct radeon_winsys_cs *cs, int nr_samples);
 455
 456
 457 /* Inline helpers. */
 458
 459 static INLINE struct r600_resource *r600_resource(struct pipe_resource *r)
 460 {
 461         return (struct r600_resource*)r;
 462 }
 463
 464 static INLINE void
 465 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 466 {
 467         pipe_resource_reference((struct pipe_resource **)ptr,
 468                                 (struct pipe_resource *)res);
 469 }
 470
 471 #define R600_ERR(fmt, args...) \
 472         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
 473
 474 /* For MSAA sample positions. */
 475 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 476         (((s0x) & 0xf) | (((s0y) & 0xf) << 4) |            \
 477         (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |     \
 478         (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |    \
 479          (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
 480
 481 #endif