projects / mesa.git / blob
? search:


fb52dfb529772c58dcca30b29e9e3a751a9c13bf
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.h
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 /**
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
30 */
31
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
34
35 #include <stdio.h>
36
37 #include "amd/common/ac_binary.h"
38
39 #include "radeon/radeon_winsys.h"
40
41 #include "util/disk_cache.h"
42 #include "util/u_blitter.h"
43 #include "util/list.h"
44 #include "util/u_range.h"
45 #include "util/slab.h"
46 #include "util/u_suballoc.h"
47 #include "util/u_transfer.h"
48 #include "util/u_threaded_context.h"
49
50 #define ATI_VENDOR_ID 0x1002
51
52 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
53 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
54 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
55 #define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
56 #define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
57
58 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
59 /* Pipeline & streamout query controls. */
60 #define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
61 #define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
62 #define R600_CONTEXT_PRIVATE_FLAG (1u << 3)
63
64 /* special primitive types */
65 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
66
67 /* Debug flags. */
68 /* logging */
69 #define DBG_TEX (1 << 0)
70 #define DBG_NIR (1 << 1)
71 #define DBG_COMPUTE (1 << 2)
72 #define DBG_VM (1 << 3)
73 /* gap - reuse */
74 /* shader logging */
75 #define DBG_FS (1 << 5)
76 #define DBG_VS (1 << 6)
77 #define DBG_GS (1 << 7)
78 #define DBG_PS (1 << 8)
79 #define DBG_CS (1 << 9)
80 #define DBG_TCS (1 << 10)
81 #define DBG_TES (1 << 11)
82 #define DBG_NO_IR (1 << 12)
83 #define DBG_NO_TGSI (1 << 13)
84 #define DBG_NO_ASM (1 << 14)
85 #define DBG_PREOPT_IR (1 << 15)
86 #define DBG_CHECK_IR (1 << 16)
87 #define DBG_NO_OPT_VARIANT (1 << 17)
88 #define DBG_FS_CORRECT_DERIVS_AFTER_KILL (1 << 18)
89 /* gaps */
90 #define DBG_TEST_DMA (1 << 20)
91 /* Bits 21-31 are reserved for the r600g driver. */
92 /* features */
93 #define DBG_NO_ASYNC_DMA (1ull << 32)
94 #define DBG_NO_HYPERZ (1ull << 33)
95 #define DBG_NO_DISCARD_RANGE (1ull << 34)
96 #define DBG_NO_2D_TILING (1ull << 35)
97 #define DBG_NO_TILING (1ull << 36)
98 #define DBG_SWITCH_ON_EOP (1ull << 37)
99 #define DBG_FORCE_DMA (1ull << 38)
100 #define DBG_PRECOMPILE (1ull << 39)
101 #define DBG_INFO (1ull << 40)
102 #define DBG_NO_WC (1ull << 41)
103 #define DBG_CHECK_VM (1ull << 42)
104 #define DBG_NO_DCC (1ull << 43)
105 #define DBG_NO_DCC_CLEAR (1ull << 44)
106 #define DBG_NO_RB_PLUS (1ull << 45)
107 #define DBG_SI_SCHED (1ull << 46)
108 #define DBG_MONOLITHIC_SHADERS (1ull << 47)
109 #define DBG_NO_CE (1ull << 48)
110 #define DBG_UNSAFE_MATH (1ull << 49)
111 #define DBG_NO_DCC_FB (1ull << 50)
112 #define DBG_TEST_VMFAULT_CP (1ull << 51)
113 #define DBG_TEST_VMFAULT_SDMA (1ull << 52)
114 #define DBG_TEST_VMFAULT_SHADER (1ull << 53)
115
116 #define R600_MAP_BUFFER_ALIGNMENT 64
117 #define R600_MAX_VIEWPORTS 16
118
119 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
120
121 enum r600_coherency {
122 R600_COHERENCY_NONE, /* no cache flushes needed */
123 R600_COHERENCY_SHADER,
124 R600_COHERENCY_CB_META,
125 };
126
127 #ifdef PIPE_ARCH_BIG_ENDIAN
128 #define R600_BIG_ENDIAN 1
129 #else
130 #define R600_BIG_ENDIAN 0
131 #endif
132
133 struct r600_common_context;
134 struct r600_perfcounters;
135 struct tgsi_shader_info;
136 struct r600_qbo_state;
137
138 void radeon_shader_binary_init(struct ac_shader_binary *b);
139 void radeon_shader_binary_clean(struct ac_shader_binary *b);
140
141 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
142 * at the moment.
143 */
144 struct r600_resource {
145 struct threaded_resource b;
146
147 /* Winsys objects. */
148 struct pb_buffer *buf;
149 uint64_t gpu_address;
150 /* Memory usage if the buffer placement is optimal. */
151 uint64_t vram_usage;
152 uint64_t gart_usage;
153
154 /* Resource properties. */
155 uint64_t bo_size;
156 unsigned bo_alignment;
157 enum radeon_bo_domain domains;
158 enum radeon_bo_flag flags;
159 unsigned bind_history;
160
161 /* The buffer range which is initialized (with a write transfer,
162 * streamout, DMA, or as a random access target). The rest of
163 * the buffer is considered invalid and can be mapped unsynchronized.
164 *
165 * This allows unsychronized mapping of a buffer range which hasn't
166 * been used yet. It's for applications which forget to use
167 * the unsynchronized map flag and expect the driver to figure it out.
168 */
169 struct util_range valid_buffer_range;
170
171 /* For buffers only. This indicates that a write operation has been
172 * performed by TC L2, but the cache hasn't been flushed.
173 * Any hw block which doesn't use or bypasses TC L2 should check this
174 * flag and flush the cache before using the buffer.
175 *
176 * For example, TC L2 must be flushed if a buffer which has been
177 * modified by a shader store instruction is about to be used as
178 * an index buffer. The reason is that VGT DMA index fetching doesn't
179 * use TC L2.
180 */
181 bool TC_L2_dirty;
182
183 /* Whether the resource has been exported via resource_get_handle. */
184 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
185
186 /* Whether this resource is referenced by bindless handles. */
187 bool texture_handle_allocated;
188 bool image_handle_allocated;
189 };
190
191 struct r600_transfer {
192 struct threaded_transfer b;
193 struct r600_resource *staging;
194 unsigned offset;
195 };
196
197 struct r600_fmask_info {
198 uint64_t offset;
199 uint64_t size;
200 unsigned alignment;
201 unsigned pitch_in_pixels;
202 unsigned bank_height;
203 unsigned slice_tile_max;
204 unsigned tile_mode_index;
205 unsigned tile_swizzle;
206 };
207
208 struct r600_cmask_info {
209 uint64_t offset;
210 uint64_t size;
211 unsigned alignment;
212 unsigned slice_tile_max;
213 uint64_t base_address_reg;
214 };
215
216 struct r600_texture {
217 struct r600_resource resource;
218
219 uint64_t size;
220 unsigned num_level0_transfers;
221 enum pipe_format db_render_format;
222 bool is_depth;
223 bool db_compatible;
224 bool can_sample_z;
225 bool can_sample_s;
226 unsigned dirty_level_mask; /* each bit says if that mipmap is compressed */
227 unsigned stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
228 struct r600_texture *flushed_depth_texture;
229 struct radeon_surf surface;
230
231 /* Colorbuffer compression and fast clear. */
232 struct r600_fmask_info fmask;
233 struct r600_cmask_info cmask;
234 struct r600_resource *cmask_buffer;
235 uint64_t dcc_offset; /* 0 = disabled */
236 unsigned cb_color_info; /* fast clear enable bit */
237 unsigned color_clear_value[2];
238 unsigned last_msaa_resolve_target_micro_mode;
239
240 /* Depth buffer compression and fast clear. */
241 uint64_t htile_offset;
242 bool tc_compatible_htile;
243 bool depth_cleared; /* if it was cleared at least once */
244 float depth_clear_value;
245 bool stencil_cleared; /* if it was cleared at least once */
246 uint8_t stencil_clear_value;
247
248 bool non_disp_tiling; /* R600-Cayman only */
249
250 /* Whether the texture is a displayable back buffer and needs DCC
251 * decompression, which is expensive. Therefore, it's enabled only
252 * if statistics suggest that it will pay off and it's allocated
253 * separately. It can't be bound as a sampler by apps. Limited to
254 * target == 2D and last_level == 0. If enabled, dcc_offset contains
255 * the absolute GPUVM address, not the relative one.
256 */
257 struct r600_resource *dcc_separate_buffer;
258 /* When DCC is temporarily disabled, the separate buffer is here. */
259 struct r600_resource *last_dcc_separate_buffer;
260 /* We need to track DCC dirtiness, because st/dri usually calls
261 * flush_resource twice per frame (not a bug) and we don't wanna
262 * decompress DCC twice. Also, the dirty tracking must be done even
263 * if DCC isn't used, because it's required by the DCC usage analysis
264 * for a possible future enablement.
265 */
266 bool separate_dcc_dirty;
267 /* Statistics gathering for the DCC enablement heuristic. */
268 bool dcc_gather_statistics;
269 /* Estimate of how much this color buffer is written to in units of
270 * full-screen draws: ps_invocations / (width * height)
271 * Shader kills, late Z, and blending with trivial discards make it
272 * inaccurate (we need to count CB updates, not PS invocations).
273 */
274 unsigned ps_draw_ratio;
275 /* The number of clears since the last DCC usage analysis. */
276 unsigned num_slow_clears;
277
278 /* Counter that should be non-zero if the texture is bound to a
279 * framebuffer. Implemented in radeonsi only.
280 */
281 uint32_t framebuffers_bound;
282 };
283
284 struct r600_surface {
285 struct pipe_surface base;
286
287 /* These can vary with block-compressed textures. */
288 unsigned width0;
289 unsigned height0;
290
291 bool color_initialized;
292 bool depth_initialized;
293
294 /* Misc. color flags. */
295 bool alphatest_bypass;
296 bool export_16bpc;
297 bool color_is_int8;
298 bool color_is_int10;
299 bool dcc_incompatible;
300
301 /* Color registers. */
302 unsigned cb_color_info;
303 unsigned cb_color_base;
304 unsigned cb_color_view;
305 unsigned cb_color_size; /* R600 only */
306 unsigned cb_color_dim; /* EG only */
307 unsigned cb_color_pitch; /* EG and later */
308 unsigned cb_color_slice; /* EG and later */
309 unsigned cb_color_attrib; /* EG and later */
310 unsigned cb_color_attrib2; /* GFX9 and later */
311 unsigned cb_dcc_control; /* VI and later */
312 unsigned cb_color_fmask; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
313 unsigned cb_color_fmask_slice; /* EG and later */
314 unsigned cb_color_cmask; /* CB_COLORn_TILE (r600 only) */
315 unsigned cb_color_mask; /* R600 only */
316 unsigned spi_shader_col_format; /* SI+, no blending, no alpha-to-coverage. */
317 unsigned spi_shader_col_format_alpha; /* SI+, alpha-to-coverage */
318 unsigned spi_shader_col_format_blend; /* SI+, blending without alpha. */
319 unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
320 struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
321 struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
322
323 /* DB registers. */
324 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
325 uint64_t db_stencil_base; /* EG and later */
326 uint64_t db_htile_data_base;
327 unsigned db_depth_info; /* R600 only, then SI and later */
328 unsigned db_z_info; /* EG and later */
329 unsigned db_z_info2; /* GFX9+ */
330 unsigned db_depth_view;
331 unsigned db_depth_size;
332 unsigned db_depth_slice; /* EG and later */
333 unsigned db_stencil_info; /* EG and later */
334 unsigned db_stencil_info2; /* GFX9+ */
335 unsigned db_prefetch_limit; /* R600 only */
336 unsigned db_htile_surface;
337 unsigned db_preload_control; /* EG and later */
338 };
339
340 struct r600_mmio_counter {
341 unsigned busy;
342 unsigned idle;
343 };
344
345 union r600_mmio_counters {
346 struct {
347 /* For global GPU load including SDMA. */
348 struct r600_mmio_counter gpu;
349
350 /* GRBM_STATUS */
351 struct r600_mmio_counter spi;
352 struct r600_mmio_counter gui;
353 struct r600_mmio_counter ta;
354 struct r600_mmio_counter gds;
355 struct r600_mmio_counter vgt;
356 struct r600_mmio_counter ia;
357 struct r600_mmio_counter sx;
358 struct r600_mmio_counter wd;
359 struct r600_mmio_counter bci;
360 struct r600_mmio_counter sc;
361 struct r600_mmio_counter pa;
362 struct r600_mmio_counter db;
363 struct r600_mmio_counter cp;
364 struct r600_mmio_counter cb;
365
366 /* SRBM_STATUS2 */
367 struct r600_mmio_counter sdma;
368
369 /* CP_STAT */
370 struct r600_mmio_counter pfp;
371 struct r600_mmio_counter meq;
372 struct r600_mmio_counter me;
373 struct r600_mmio_counter surf_sync;
374 struct r600_mmio_counter dma;
375 struct r600_mmio_counter scratch_ram;
376 struct r600_mmio_counter ce;
377 } named;
378 unsigned array[0];
379 };
380
381 struct r600_common_screen {
382 struct pipe_screen b;
383 struct radeon_winsys *ws;
384 enum radeon_family family;
385 enum chip_class chip_class;
386 struct radeon_info info;
387 uint64_t debug_flags;
388 bool has_cp_dma;
389 bool has_streamout;
390 bool has_rbplus; /* if RB+ registers exist */
391 bool rbplus_allowed; /* if RB+ is allowed */
392
393 struct disk_cache *disk_shader_cache;
394
395 struct slab_parent_pool pool_transfers;
396
397 /* Texture filter settings. */
398 int force_aniso; /* -1 = disabled */
399
400 /* Auxiliary context. Mainly used to initialize resources.
401 * It must be locked prior to using and flushed before unlocking. */
402 struct pipe_context *aux_context;
403 mtx_t aux_context_lock;
404
405 /* This must be in the screen, because UE4 uses one context for
406 * compilation and another one for rendering.
407 */
408 unsigned num_compilations;
409 /* Along with ST_DEBUG=precompile, this should show if applications
410 * are loading shaders on demand. This is a monotonic counter.
411 */
412 unsigned num_shaders_created;
413 unsigned num_shader_cache_hits;
414
415 /* GPU load thread. */
416 mtx_t gpu_load_mutex;
417 thrd_t gpu_load_thread;
418 union r600_mmio_counters mmio_counters;
419 volatile unsigned gpu_load_stop_thread; /* bool */
420
421 char renderer_string[100];
422
423 /* Performance counters. */
424 struct r600_perfcounters *perfcounters;
425
426 /* If pipe_screen wants to recompute and re-emit the framebuffer,
427 * sampler, and image states of all contexts, it should atomically
428 * increment this.
429 *
430 * Each context will compare this with its own last known value of
431 * the counter before drawing and re-emit the states accordingly.
432 */
433 unsigned dirty_tex_counter;
434
435 /* Atomically increment this counter when an existing texture's
436 * metadata is enabled or disabled in a way that requires changing
437 * contexts' compressed texture binding masks.
438 */
439 unsigned compressed_colortex_counter;
440
441 struct {
442 /* Context flags to set so that all writes from earlier jobs
443 * in the CP are seen by L2 clients.
444 */
445 unsigned cp_to_L2;
446
447 /* Context flags to set so that all writes from earlier
448 * compute jobs are seen by L2 clients.
449 */
450 unsigned compute_to_L2;
451 } barrier_flags;
452
453 void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
454 struct r600_texture *rtex,
455 struct radeon_bo_metadata *md);
456
457 void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
458 struct r600_texture *rtex,
459 struct radeon_bo_metadata *md);
460 };
461
462 /* This encapsulates a state or an operation which can emitted into the GPU
463 * command stream. */
464 struct r600_atom {
465 void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
466 unsigned num_dw;
467 unsigned short id;
468 };
469
470 struct r600_so_target {
471 struct pipe_stream_output_target b;
472
473 /* The buffer where BUFFER_FILLED_SIZE is stored. */
474 struct r600_resource *buf_filled_size;
475 unsigned buf_filled_size_offset;
476 bool buf_filled_size_valid;
477
478 unsigned stride_in_dw;
479 };
480
481 struct r600_streamout {
482 struct r600_atom begin_atom;
483 bool begin_emitted;
484 unsigned num_dw_for_end;
485
486 unsigned enabled_mask;
487 unsigned num_targets;
488 struct r600_so_target *targets[PIPE_MAX_SO_BUFFERS];
489
490 unsigned append_bitmask;
491 bool suspended;
492
493 /* External state which comes from the vertex shader,
494 * it must be set explicitly when binding a shader. */
495 uint16_t *stride_in_dw;
496 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
497
498 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
499 unsigned hw_enabled_mask;
500
501 /* The state of VGT_STRMOUT_(CONFIG|EN). */
502 struct r600_atom enable_atom;
503 bool streamout_enabled;
504 bool prims_gen_query_enabled;
505 int num_prims_gen_queries;
506 };
507
508 struct r600_signed_scissor {
509 int minx;
510 int miny;
511 int maxx;
512 int maxy;
513 };
514
515 struct r600_scissors {
516 struct r600_atom atom;
517 unsigned dirty_mask;
518 struct pipe_scissor_state states[R600_MAX_VIEWPORTS];
519 };
520
521 struct r600_viewports {
522 struct r600_atom atom;
523 unsigned dirty_mask;
524 unsigned depth_range_dirty_mask;
525 struct pipe_viewport_state states[R600_MAX_VIEWPORTS];
526 struct r600_signed_scissor as_scissor[R600_MAX_VIEWPORTS];
527 };
528
529 struct r600_ring {
530 struct radeon_winsys_cs *cs;
531 void (*flush)(void *ctx, unsigned flags,
532 struct pipe_fence_handle **fence);
533 };
534
535 /* Saved CS data for debugging features. */
536 struct radeon_saved_cs {
537 uint32_t *ib;
538 unsigned num_dw;
539
540 struct radeon_bo_list_item *bo_list;
541 unsigned bo_count;
542 };
543
544 struct r600_common_context {
545 struct pipe_context b; /* base class */
546
547 struct r600_common_screen *screen;
548 struct radeon_winsys *ws;
549 struct radeon_winsys_ctx *ctx;
550 enum radeon_family family;
551 enum chip_class chip_class;
552 struct r600_ring gfx;
553 struct r600_ring dma;
554 struct pipe_fence_handle *last_gfx_fence;
555 struct pipe_fence_handle *last_sdma_fence;
556 unsigned num_gfx_cs_flushes;
557 unsigned initial_gfx_cs_size;
558 unsigned gpu_reset_counter;
559 unsigned last_dirty_tex_counter;
560 unsigned last_compressed_colortex_counter;
561
562 struct threaded_context *tc;
563 struct u_suballocator *allocator_zeroed_memory;
564 struct slab_child_pool pool_transfers;
565 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
566
567 /* Current unaccounted memory usage. */
568 uint64_t vram;
569 uint64_t gtt;
570
571 /* States. */
572 struct r600_streamout streamout;
573 struct r600_scissors scissors;
574 struct r600_viewports viewports;
575 bool scissor_enabled;
576 bool clip_halfz;
577 bool vs_writes_viewport_index;
578 bool vs_disables_clipping_viewport;
579
580 /* Additional context states. */
581 unsigned flags; /* flush flags */
582
583 /* Queries. */
584 /* Maintain the list of active queries for pausing between IBs. */
585 int num_occlusion_queries;
586 int num_perfect_occlusion_queries;
587 struct list_head active_queries;
588 unsigned num_cs_dw_queries_suspend;
589 /* Misc stats. */
590 unsigned num_draw_calls;
591 unsigned num_mrt_draw_calls;
592 unsigned num_prim_restart_calls;
593 unsigned num_spill_draw_calls;
594 unsigned num_compute_calls;
595 unsigned num_spill_compute_calls;
596 unsigned num_dma_calls;
597 unsigned num_cp_dma_calls;
598 unsigned num_vs_flushes;
599 unsigned num_ps_flushes;
600 unsigned num_cs_flushes;
601 unsigned num_cb_cache_flushes;
602 unsigned num_db_cache_flushes;
603 unsigned num_L2_invalidates;
604 unsigned num_L2_writebacks;
605 unsigned num_resident_handles;
606 uint64_t num_alloc_tex_transfer_bytes;
607 unsigned last_tex_ps_draw_ratio; /* for query */
608
609 /* Render condition. */
610 struct r600_atom render_cond_atom;
611 struct pipe_query *render_cond;
612 unsigned render_cond_mode;
613 bool render_cond_invert;
614 bool render_cond_force_off; /* for u_blitter */
615
616 /* MSAA sample locations.
617 * The first index is the sample index.
618 * The second index is the coordinate: X, Y. */
619 float sample_locations_1x[1][2];
620 float sample_locations_2x[2][2];
621 float sample_locations_4x[4][2];
622 float sample_locations_8x[8][2];
623 float sample_locations_16x[16][2];
624
625 /* Statistics gathering for the DCC enablement heuristic. It can't be
626 * in r600_texture because r600_texture can be shared by multiple
627 * contexts. This is for back buffers only. We shouldn't get too many
628 * of those.
629 *
630 * X11 DRI3 rotates among a finite set of back buffers. They should
631 * all fit in this array. If they don't, separate DCC might never be
632 * enabled by DCC stat gathering.
633 */
634 struct {
635 struct r600_texture *tex;
636 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
637 struct pipe_query *ps_stats[3];
638 /* If all slots are used and another slot is needed,
639 * the least recently used slot is evicted based on this. */
640 int64_t last_use_timestamp;
641 bool query_active;
642 } dcc_stats[5];
643
644 struct pipe_debug_callback debug;
645 struct pipe_device_reset_callback device_reset_callback;
646
647 void *query_result_shader;
648
649 /* Copy one resource to another using async DMA. */
650 void (*dma_copy)(struct pipe_context *ctx,
651 struct pipe_resource *dst,
652 unsigned dst_level,
653 unsigned dst_x, unsigned dst_y, unsigned dst_z,
654 struct pipe_resource *src,
655 unsigned src_level,
656 const struct pipe_box *src_box);
657
658 void (*dma_clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
659 uint64_t offset, uint64_t size, unsigned value);
660
661 void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
662 uint64_t offset, uint64_t size, unsigned value,
663 enum r600_coherency coher);
664
665 void (*blit_decompress_depth)(struct pipe_context *ctx,
666 struct r600_texture *texture,
667 struct r600_texture *staging,
668 unsigned first_level, unsigned last_level,
669 unsigned first_layer, unsigned last_layer,
670 unsigned first_sample, unsigned last_sample);
671
672 void (*decompress_dcc)(struct pipe_context *ctx,
673 struct r600_texture *rtex);
674
675 /* Reallocate the buffer and update all resource bindings where
676 * the buffer is bound, including all resource descriptors. */
677 void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
678
679 /* Update all resource bindings where the buffer is bound, including
680 * all resource descriptors. This is invalidate_buffer without
681 * the invalidation. */
682 void (*rebind_buffer)(struct pipe_context *ctx, struct pipe_resource *buf,
683 uint64_t old_gpu_address);
684
685 /* Enable or disable occlusion queries. */
686 void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
687
688 void (*save_qbo_state)(struct pipe_context *ctx, struct r600_qbo_state *st);
689
690 /* This ensures there is enough space in the command stream. */
691 void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
692 bool include_draw_vbo);
693
694 void (*set_atom_dirty)(struct r600_common_context *ctx,
695 struct r600_atom *atom, bool dirty);
696
697 void (*check_vm_faults)(struct r600_common_context *ctx,
698 struct radeon_saved_cs *saved,
699 enum ring_type ring);
700 };
701
702 /* r600_buffer_common.c */
703 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
704 struct pb_buffer *buf,
705 enum radeon_bo_usage usage);
706 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
707 struct r600_resource *resource,
708 unsigned usage);
709 void r600_buffer_subdata(struct pipe_context *ctx,
710 struct pipe_resource *buffer,
711 unsigned usage, unsigned offset,
712 unsigned size, const void *data);
713 void r600_init_resource_fields(struct r600_common_screen *rscreen,
714 struct r600_resource *res,
715 uint64_t size, unsigned alignment);
716 bool r600_alloc_resource(struct r600_common_screen *rscreen,
717 struct r600_resource *res);
718 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
719 const struct pipe_resource *templ,
720 unsigned alignment);
721 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
722 unsigned flags,
723 unsigned usage,
724 unsigned size,
725 unsigned alignment);
726 struct pipe_resource *
727 r600_buffer_from_user_memory(struct pipe_screen *screen,
728 const struct pipe_resource *templ,
729 void *user_memory);
730 void
731 r600_invalidate_resource(struct pipe_context *ctx,
732 struct pipe_resource *resource);
733 void r600_replace_buffer_storage(struct pipe_context *ctx,
734 struct pipe_resource *dst,
735 struct pipe_resource *src);
736
737 /* r600_common_pipe.c */
738 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
739 unsigned event, unsigned event_flags,
740 unsigned data_sel,
741 struct r600_resource *buf, uint64_t va,
742 uint32_t old_fence, uint32_t new_fence);
743 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen);
744 void r600_gfx_wait_fence(struct r600_common_context *ctx,
745 uint64_t va, uint32_t ref, uint32_t mask);
746 void r600_draw_rectangle(struct blitter_context *blitter,
747 int x1, int y1, int x2, int y2, float depth,
748 enum blitter_attrib_type type,
749 const union pipe_color_union *attrib);
750 bool r600_common_screen_init(struct r600_common_screen *rscreen,
751 struct radeon_winsys *ws, unsigned flags);
752 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
753 void r600_preflush_suspend_features(struct r600_common_context *ctx);
754 void r600_postflush_resume_features(struct r600_common_context *ctx);
755 bool r600_common_context_init(struct r600_common_context *rctx,
756 struct r600_common_screen *rscreen,
757 unsigned context_flags);
758 void r600_common_context_cleanup(struct r600_common_context *rctx);
759 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
760 unsigned processor);
761 bool r600_extra_shader_checks(struct r600_common_screen *rscreen,
762 unsigned processor);
763 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
764 uint64_t offset, uint64_t size, unsigned value);
765 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
766 const struct pipe_resource *templ);
767 const char *r600_get_llvm_processor_name(enum radeon_family family);
768 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
769 struct r600_resource *dst, struct r600_resource *src);
770 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
771 struct radeon_saved_cs *saved, bool get_buffer_list);
772 void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
773 bool r600_check_device_reset(struct r600_common_context *rctx);
774
775 /* r600_gpu_load.c */
776 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
777 uint64_t r600_begin_counter(struct r600_common_screen *rscreen, unsigned type);
778 unsigned r600_end_counter(struct r600_common_screen *rscreen, unsigned type,
779 uint64_t begin);
780
781 /* r600_perfcounters.c */
782 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
783
784 /* r600_query.c */
785 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
786 void r600_query_init(struct r600_common_context *rctx);
787 void r600_suspend_queries(struct r600_common_context *ctx);
788 void r600_resume_queries(struct r600_common_context *ctx);
789 void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen);
790
791 /* r600_streamout.c */
792 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
793 void r600_set_streamout_targets(struct pipe_context *ctx,
794 unsigned num_targets,
795 struct pipe_stream_output_target **targets,
796 const unsigned *offset);
797 void r600_emit_streamout_end(struct r600_common_context *rctx);
798 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
799 unsigned type, int diff);
800 void r600_streamout_init(struct r600_common_context *rctx);
801
802 /* r600_test_dma.c */
803 void r600_test_dma(struct r600_common_screen *rscreen);
804
805 /* r600_texture.c */
806 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
807 struct r600_texture *rdst,
808 unsigned dst_level, unsigned dstx,
809 unsigned dsty, unsigned dstz,
810 struct r600_texture *rsrc,
811 unsigned src_level,
812 const struct pipe_box *src_box);
813 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
814 struct r600_texture *rtex,
815 unsigned nr_samples,
816 struct r600_fmask_info *out);
817 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
818 struct r600_texture *rtex,
819 struct r600_cmask_info *out);
820 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
821 struct pipe_resource *texture,
822 struct r600_texture **staging);
823 void r600_print_texture_info(struct r600_common_screen *rscreen,
824 struct r600_texture *rtex, FILE *f);
825 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
826 const struct pipe_resource *templ);
827 bool vi_dcc_formats_compatible(enum pipe_format format1,
828 enum pipe_format format2);
829 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
830 unsigned level,
831 enum pipe_format view_format);
832 void vi_disable_dcc_if_incompatible_format(struct r600_common_context *rctx,
833 struct pipe_resource *tex,
834 unsigned level,
835 enum pipe_format view_format);
836 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
837 struct pipe_resource *texture,
838 const struct pipe_surface *templ,
839 unsigned width0, unsigned height0,
840 unsigned width, unsigned height);
841 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
842 void vi_separate_dcc_start_query(struct pipe_context *ctx,
843 struct r600_texture *tex);
844 void vi_separate_dcc_stop_query(struct pipe_context *ctx,
845 struct r600_texture *tex);
846 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
847 struct r600_texture *tex);
848 void vi_dcc_clear_level(struct r600_common_context *rctx,
849 struct r600_texture *rtex,
850 unsigned level, unsigned clear_value);
851 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
852 struct pipe_framebuffer_state *fb,
853 struct r600_atom *fb_state,
854 unsigned *buffers, ubyte *dirty_cbufs,
855 const union pipe_color_union *color);
856 bool r600_texture_disable_dcc(struct r600_common_context *rctx,
857 struct r600_texture *rtex);
858 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
859 void r600_init_context_texture_functions(struct r600_common_context *rctx);
860
861 /* r600_viewport.c */
862 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
863 struct pipe_scissor_state *scissor);
864 void r600_viewport_set_rast_deps(struct r600_common_context *rctx,
865 bool scissor_enable, bool clip_halfz);
866 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
867 struct tgsi_shader_info *info);
868 void r600_init_viewport_functions(struct r600_common_context *rctx);
869
870 /* cayman_msaa.c */
871 extern const uint32_t eg_sample_locs_2x[4];
872 extern const unsigned eg_max_dist_2x;
873 extern const uint32_t eg_sample_locs_4x[4];
874 extern const unsigned eg_max_dist_4x;
875 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
876 unsigned sample_index, float *out_value);
877 void cayman_init_msaa(struct pipe_context *ctx);
878 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
879 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
880 int ps_iter_samples, int overrast_samples,
881 unsigned sc_mode_cntl_1);
882
883
884 /* Inline helpers. */
885
886 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
887 {
888 return (struct r600_resource*)r;
889 }
890
891 static inline void
892 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
893 {
894 pipe_resource_reference((struct pipe_resource **)ptr,
895 (struct pipe_resource *)res);
896 }
897
898 static inline void
899 r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
900 {
901 pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
902 }
903
904 static inline void
905 r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
906 {
907 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
908 struct r600_resource *res = (struct r600_resource *)r;
909
910 if (res) {
911 /* Add memory usage for need_gfx_cs_space */
912 rctx->vram += res->vram_usage;
913 rctx->gtt += res->gart_usage;
914 }
915 }
916
917 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
918 {
919 return rctx->streamout.streamout_enabled ||
920 rctx->streamout.prims_gen_query_enabled;
921 }
922
923 #define SQ_TEX_XY_FILTER_POINT 0x00
924 #define SQ_TEX_XY_FILTER_BILINEAR 0x01
925 #define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
926 #define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03
927
928 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
929 {
930 if (filter == PIPE_TEX_FILTER_LINEAR)
931 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
932 : SQ_TEX_XY_FILTER_BILINEAR;
933 else
934 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
935 : SQ_TEX_XY_FILTER_POINT;
936 }
937
938 static inline unsigned r600_tex_aniso_filter(unsigned filter)
939 {
940 if (filter < 2)
941 return 0;
942 if (filter < 4)
943 return 1;
944 if (filter < 8)
945 return 2;
946 if (filter < 16)
947 return 3;
948 return 4;
949 }
950
951 static inline unsigned r600_wavefront_size(enum radeon_family family)
952 {
953 switch (family) {
954 case CHIP_RV610:
955 case CHIP_RS780:
956 case CHIP_RV620:
957 case CHIP_RS880:
958 return 16;
959 case CHIP_RV630:
960 case CHIP_RV635:
961 case CHIP_RV730:
962 case CHIP_RV710:
963 case CHIP_PALM:
964 case CHIP_CEDAR:
965 return 32;
966 default:
967 return 64;
968 }
969 }
970
971 static inline enum radeon_bo_priority
972 r600_get_sampler_view_priority(struct r600_resource *res)
973 {
974 if (res->b.b.target == PIPE_BUFFER)
975 return RADEON_PRIO_SAMPLER_BUFFER;
976
977 if (res->b.b.nr_samples > 1)
978 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
979
980 return RADEON_PRIO_SAMPLER_TEXTURE;
981 }
982
983 static inline bool
984 r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
985 {
986 return (stencil_sampler && tex->can_sample_s) ||
987 (!stencil_sampler && tex->can_sample_z);
988 }
989
990 static inline bool
991 vi_dcc_enabled(struct r600_texture *tex, unsigned level)
992 {
993 return tex->dcc_offset && level < tex->surface.num_dcc_levels;
994 }
995
996 #define COMPUTE_DBG(rscreen, fmt, args...) \
997 do { \
998 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
999 } while (0);
1000
1001 #define R600_ERR(fmt, args...) \
1002 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1003
1004 /* For MSAA sample positions. */
1005 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1006 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1007 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1008 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1009 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1010
1011 static inline int S_FIXED(float value, unsigned frac_bits)
1012 {
1013 return value * (1 << frac_bits);
1014 }
1015
1016 #endif