src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/u_slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  47 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  48 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  49
  50 #define R600_QUERY_DRAW_CALLS           (PIPE_QUERY_DRIVER_SPECIFIC + 0)
  51 #define R600_QUERY_REQUESTED_VRAM       (PIPE_QUERY_DRIVER_SPECIFIC + 1)
  52 #define R600_QUERY_REQUESTED_GTT        (PIPE_QUERY_DRIVER_SPECIFIC + 2)
  53 #define R600_QUERY_BUFFER_WAIT_TIME     (PIPE_QUERY_DRIVER_SPECIFIC + 3)
  54 #define R600_QUERY_NUM_CS_FLUSHES       (PIPE_QUERY_DRIVER_SPECIFIC + 4)
  55 #define R600_QUERY_NUM_BYTES_MOVED      (PIPE_QUERY_DRIVER_SPECIFIC + 5)
  56 #define R600_QUERY_VRAM_USAGE           (PIPE_QUERY_DRIVER_SPECIFIC + 6)
  57 #define R600_QUERY_GTT_USAGE            (PIPE_QUERY_DRIVER_SPECIFIC + 7)
  58 #define R600_QUERY_GPU_TEMPERATURE      (PIPE_QUERY_DRIVER_SPECIFIC + 8)
  59 #define R600_QUERY_CURRENT_GPU_SCLK     (PIPE_QUERY_DRIVER_SPECIFIC + 9)
  60 #define R600_QUERY_CURRENT_GPU_MCLK     (PIPE_QUERY_DRIVER_SPECIFIC + 10)
  61 #define R600_QUERY_GPU_LOAD             (PIPE_QUERY_DRIVER_SPECIFIC + 11)
  62
  63 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  64 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 1)
  65
  66 /* special primitive types */
  67 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  68
  69 /* Debug flags. */
  70 /* logging */
  71 #define DBG_TEX                 (1 << 0)
  72 #define DBG_TEXMIP              (1 << 1)
  73 #define DBG_COMPUTE             (1 << 2)
  74 #define DBG_VM                  (1 << 3)
  75 #define DBG_TRACE_CS            (1 << 4)
  76 /* shader logging */
  77 #define DBG_FS                  (1 << 5)
  78 #define DBG_VS                  (1 << 6)
  79 #define DBG_GS                  (1 << 7)
  80 #define DBG_PS                  (1 << 8)
  81 #define DBG_CS                  (1 << 9)
  82 #define DBG_TCS                 (1 << 10)
  83 #define DBG_TES                 (1 << 11)
  84 #define DBG_NO_IR               (1 << 12)
  85 #define DBG_NO_TGSI             (1 << 13)
  86 #define DBG_NO_ASM              (1 << 14)
  87 /* Bits 21-31 are reserved for the r600g driver. */
  88 /* features */
  89 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  90 #define DBG_NO_HYPERZ           (1llu << 33)
  91 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  92 #define DBG_NO_2D_TILING        (1llu << 35)
  93 #define DBG_NO_TILING           (1llu << 36)
  94 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  95 #define DBG_FORCE_DMA           (1llu << 38)
  96 #define DBG_PRECOMPILE          (1llu << 39)
  97 #define DBG_INFO                (1llu << 40)
  98
  99 #define R600_MAP_BUFFER_ALIGNMENT 64
 100
 101 struct r600_common_context;
 102
 103 struct radeon_shader_reloc {
 104         char *name;
 105         uint64_t offset;
 106 };
 107
 108 struct radeon_shader_binary {
 109         /** Shader code */
 110         unsigned char *code;
 111         unsigned code_size;
 112
 113         /** Config/Context register state that accompanies this shader.
 114          * This is a stream of dword pairs.  First dword contains the
 115          * register address, the second dword contains the value.*/
 116         unsigned char *config;
 117         unsigned config_size;
 118
 119         /** The number of bytes of config information for each global symbol.
 120          */
 121         unsigned config_size_per_symbol;
 122
 123         /** Constant data accessed by the shader.  This will be uploaded
 124          * into a constant buffer. */
 125         unsigned char *rodata;
 126         unsigned rodata_size;
 127
 128         /** List of symbol offsets for the shader */
 129         uint64_t *global_symbol_offsets;
 130         unsigned global_symbol_count;
 131
 132         struct radeon_shader_reloc *relocs;
 133         unsigned reloc_count;
 134
 135         /** Disassembled shader in a string. */
 136         char *disasm_string;
 137 };
 138
 139 struct r600_resource {
 140         struct u_resource               b;
 141
 142         /* Winsys objects. */
 143         struct pb_buffer                *buf;
 144         struct radeon_winsys_cs_handle  *cs_buf;
 145         uint64_t                        gpu_address;
 146
 147         /* Resource state. */
 148         enum radeon_bo_domain           domains;
 149
 150         /* The buffer range which is initialized (with a write transfer,
 151          * streamout, DMA, or as a random access target). The rest of
 152          * the buffer is considered invalid and can be mapped unsynchronized.
 153          *
 154          * This allows unsychronized mapping of a buffer range which hasn't
 155          * been used yet. It's for applications which forget to use
 156          * the unsynchronized map flag and expect the driver to figure it out.
 157          */
 158         struct util_range               valid_buffer_range;
 159
 160         /* For buffers only. This indicates that a write operation has been
 161          * performed by TC L2, but the cache hasn't been flushed.
 162          * Any hw block which doesn't use or bypasses TC L2 should check this
 163          * flag and flush the cache before using the buffer.
 164          *
 165          * For example, TC L2 must be flushed if a buffer which has been
 166          * modified by a shader store instruction is about to be used as
 167          * an index buffer. The reason is that VGT DMA index fetching doesn't
 168          * use TC L2.
 169          */
 170         bool                            TC_L2_dirty;
 171 };
 172
 173 struct r600_transfer {
 174         struct pipe_transfer            transfer;
 175         struct r600_resource            *staging;
 176         unsigned                        offset;
 177 };
 178
 179 struct r600_fmask_info {
 180         unsigned offset;
 181         unsigned size;
 182         unsigned alignment;
 183         unsigned pitch;
 184         unsigned bank_height;
 185         unsigned slice_tile_max;
 186         unsigned tile_mode_index;
 187 };
 188
 189 struct r600_cmask_info {
 190         unsigned offset;
 191         unsigned size;
 192         unsigned alignment;
 193         unsigned slice_tile_max;
 194         unsigned base_address_reg;
 195 };
 196
 197 struct r600_texture {
 198         struct r600_resource            resource;
 199
 200         unsigned                        size;
 201         unsigned                        pitch_override;
 202         bool                            is_depth;
 203         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 204         struct r600_texture             *flushed_depth_texture;
 205         boolean                         is_flushing_texture;
 206         struct radeon_surf              surface;
 207
 208         /* Colorbuffer compression and fast clear. */
 209         struct r600_fmask_info          fmask;
 210         struct r600_cmask_info          cmask;
 211         struct r600_resource            *cmask_buffer;
 212         unsigned                        cb_color_info; /* fast clear enable bit */
 213         unsigned                        color_clear_value[2];
 214
 215         /* Depth buffer compression and fast clear. */
 216         struct r600_resource            *htile_buffer;
 217         bool                            depth_cleared; /* if it was cleared at least once */
 218         float                           depth_clear_value;
 219
 220         bool                            non_disp_tiling; /* R600-Cayman only */
 221 };
 222
 223 struct r600_surface {
 224         struct pipe_surface             base;
 225
 226         bool color_initialized;
 227         bool depth_initialized;
 228
 229         /* Misc. color flags. */
 230         bool alphatest_bypass;
 231         bool export_16bpc;
 232
 233         /* Color registers. */
 234         unsigned cb_color_info;
 235         unsigned cb_color_base;
 236         unsigned cb_color_view;
 237         unsigned cb_color_size;         /* R600 only */
 238         unsigned cb_color_dim;          /* EG only */
 239         unsigned cb_color_pitch;        /* EG and later */
 240         unsigned cb_color_slice;        /* EG and later */
 241         unsigned cb_color_attrib;       /* EG and later */
 242         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 243         unsigned cb_color_fmask_slice;  /* EG and later */
 244         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 245         unsigned cb_color_mask;         /* R600 only */
 246         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 247         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 248
 249         /* DB registers. */
 250         unsigned db_depth_info;         /* R600 only, then SI and later */
 251         unsigned db_z_info;             /* EG and later */
 252         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 253         unsigned db_depth_view;
 254         unsigned db_depth_size;
 255         unsigned db_depth_slice;        /* EG and later */
 256         unsigned db_stencil_base;       /* EG and later */
 257         unsigned db_stencil_info;       /* EG and later */
 258         unsigned db_prefetch_limit;     /* R600 only */
 259         unsigned db_htile_surface;
 260         unsigned db_htile_data_base;
 261         unsigned db_preload_control;    /* EG and later */
 262         unsigned pa_su_poly_offset_db_fmt_cntl;
 263 };
 264
 265 struct r600_tiling_info {
 266         unsigned num_channels;
 267         unsigned num_banks;
 268         unsigned group_bytes;
 269 };
 270
 271 struct r600_common_screen {
 272         struct pipe_screen              b;
 273         struct radeon_winsys            *ws;
 274         enum radeon_family              family;
 275         enum chip_class                 chip_class;
 276         struct radeon_info              info;
 277         struct r600_tiling_info         tiling_info;
 278         uint64_t                        debug_flags;
 279         bool                            has_cp_dma;
 280         bool                            has_streamout;
 281
 282         /* Auxiliary context. Mainly used to initialize resources.
 283          * It must be locked prior to using and flushed before unlocking. */
 284         struct pipe_context             *aux_context;
 285         pipe_mutex                      aux_context_lock;
 286
 287         struct r600_resource            *trace_bo;
 288         uint32_t                        *trace_ptr;
 289         unsigned                        cs_count;
 290
 291         /* GPU load thread. */
 292         pipe_mutex                      gpu_load_mutex;
 293         pipe_thread                     gpu_load_thread;
 294         unsigned                        gpu_load_counter_busy;
 295         unsigned                        gpu_load_counter_idle;
 296         volatile unsigned               gpu_load_stop_thread; /* bool */
 297 };
 298
 299 /* This encapsulates a state or an operation which can emitted into the GPU
 300  * command stream. */
 301 struct r600_atom {
 302         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 303         unsigned                num_dw;
 304         bool                    dirty;
 305 };
 306
 307 struct r600_so_target {
 308         struct pipe_stream_output_target b;
 309
 310         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 311         struct r600_resource    *buf_filled_size;
 312         unsigned                buf_filled_size_offset;
 313         bool                    buf_filled_size_valid;
 314
 315         unsigned                stride_in_dw;
 316 };
 317
 318 struct r600_streamout {
 319         struct r600_atom                begin_atom;
 320         bool                            begin_emitted;
 321         unsigned                        num_dw_for_end;
 322
 323         unsigned                        enabled_mask;
 324         unsigned                        num_targets;
 325         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 326
 327         unsigned                        append_bitmask;
 328         bool                            suspended;
 329
 330         /* External state which comes from the vertex shader,
 331          * it must be set explicitly when binding a shader. */
 332         unsigned                        *stride_in_dw;
 333         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 334
 335         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 336         unsigned                        hw_enabled_mask;
 337
 338         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 339         struct r600_atom                enable_atom;
 340         bool                            streamout_enabled;
 341         bool                            prims_gen_query_enabled;
 342         int                             num_prims_gen_queries;
 343 };
 344
 345 struct r600_ring {
 346         struct radeon_winsys_cs         *cs;
 347         bool                            flushing;
 348         void (*flush)(void *ctx, unsigned flags,
 349                       struct pipe_fence_handle **fence);
 350 };
 351
 352 struct r600_rings {
 353         struct r600_ring                gfx;
 354         struct r600_ring                dma;
 355 };
 356
 357 struct r600_common_context {
 358         struct pipe_context b; /* base class */
 359
 360         struct r600_common_screen       *screen;
 361         struct radeon_winsys            *ws;
 362         enum radeon_family              family;
 363         enum chip_class                 chip_class;
 364         struct r600_rings               rings;
 365         unsigned                        initial_gfx_cs_size;
 366         unsigned                        gpu_reset_counter;
 367
 368         struct u_upload_mgr             *uploader;
 369         struct u_suballocator           *allocator_so_filled_size;
 370         struct util_slab_mempool        pool_transfers;
 371
 372         /* Current unaccounted memory usage. */
 373         uint64_t                        vram;
 374         uint64_t                        gtt;
 375
 376         /* States. */
 377         struct r600_streamout           streamout;
 378
 379         /* Additional context states. */
 380         unsigned flags; /* flush flags */
 381
 382         /* Queries. */
 383         /* The list of active queries. Only one query of each type can be active. */
 384         int                             num_occlusion_queries;
 385         /* Keep track of non-timer queries, because they should be suspended
 386          * during context flushing.
 387          * The timer queries (TIME_ELAPSED) shouldn't be suspended for blits,
 388          * but they should be suspended between IBs. */
 389         struct list_head                active_nontimer_queries;
 390         struct list_head                active_timer_queries;
 391         unsigned                        num_cs_dw_nontimer_queries_suspend;
 392         unsigned                        num_cs_dw_timer_queries_suspend;
 393         /* If queries have been suspended. */
 394         bool                            queries_suspended_for_flush;
 395         /* Additional hardware info. */
 396         unsigned                        backend_mask;
 397         unsigned                        max_db; /* for OQ */
 398         /* Misc stats. */
 399         unsigned                        num_draw_calls;
 400
 401         /* Render condition. */
 402         struct pipe_query               *current_render_cond;
 403         unsigned                        current_render_cond_mode;
 404         boolean                         current_render_cond_cond;
 405         boolean                         predicate_drawing;
 406         /* For context flushing. */
 407         struct pipe_query               *saved_render_cond;
 408         boolean                         saved_render_cond_cond;
 409         unsigned                        saved_render_cond_mode;
 410
 411         /* MSAA sample locations.
 412          * The first index is the sample index.
 413          * The second index is the coordinate: X, Y. */
 414         float                           sample_locations_1x[1][2];
 415         float                           sample_locations_2x[2][2];
 416         float                           sample_locations_4x[4][2];
 417         float                           sample_locations_8x[8][2];
 418         float                           sample_locations_16x[16][2];
 419
 420         /* The list of all texture buffer objects in this context.
 421          * This list is walked when a buffer is invalidated/reallocated and
 422          * the GPU addresses are updated. */
 423         struct list_head                texture_buffers;
 424
 425         /* Copy one resource to another using async DMA. */
 426         void (*dma_copy)(struct pipe_context *ctx,
 427                          struct pipe_resource *dst,
 428                          unsigned dst_level,
 429                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 430                          struct pipe_resource *src,
 431                          unsigned src_level,
 432                          const struct pipe_box *src_box);
 433
 434         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 435                              unsigned offset, unsigned size, unsigned value,
 436                              bool is_framebuffer);
 437
 438         void (*blit_decompress_depth)(struct pipe_context *ctx,
 439                                       struct r600_texture *texture,
 440                                       struct r600_texture *staging,
 441                                       unsigned first_level, unsigned last_level,
 442                                       unsigned first_layer, unsigned last_layer,
 443                                       unsigned first_sample, unsigned last_sample);
 444
 445         /* Reallocate the buffer and update all resource bindings where
 446          * the buffer is bound, including all resource descriptors. */
 447         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 448
 449         /* Enable or disable occlusion queries. */
 450         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 451
 452         /* This ensures there is enough space in the command stream. */
 453         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 454                                   bool include_draw_vbo);
 455 };
 456
 457 /* r600_buffer.c */
 458 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 459                                         struct radeon_winsys_cs_handle *buf,
 460                                         enum radeon_bo_usage usage);
 461 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 462                                       struct r600_resource *resource,
 463                                       unsigned usage);
 464 bool r600_init_resource(struct r600_common_screen *rscreen,
 465                         struct r600_resource *res,
 466                         unsigned size, unsigned alignment,
 467                         bool use_reusable_pool);
 468 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 469                                          const struct pipe_resource *templ,
 470                                          unsigned alignment);
 471 struct pipe_resource *
 472 r600_buffer_from_user_memory(struct pipe_screen *screen,
 473                              const struct pipe_resource *templ,
 474                              void *user_memory);
 475
 476 /* r600_common_pipe.c */
 477 void r600_draw_rectangle(struct blitter_context *blitter,
 478                          int x1, int y1, int x2, int y2, float depth,
 479                          enum blitter_attrib_type type,
 480                          const union pipe_color_union *attrib);
 481 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 482                              struct radeon_winsys *ws);
 483 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 484 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 485 void r600_postflush_resume_features(struct r600_common_context *ctx);
 486 bool r600_common_context_init(struct r600_common_context *rctx,
 487                               struct r600_common_screen *rscreen);
 488 void r600_common_context_cleanup(struct r600_common_context *rctx);
 489 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 490 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 491                           const struct tgsi_token *tokens);
 492 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 493                               unsigned offset, unsigned size, unsigned value,
 494                               bool is_framebuffer);
 495 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 496                                                   const struct pipe_resource *templ);
 497 const char *r600_get_llvm_processor_name(enum radeon_family family);
 498 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw);
 499
 500 /* r600_gpu_load.c */
 501 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 502 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
 503 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 504
 505 /* r600_query.c */
 506 void r600_query_init(struct r600_common_context *rctx);
 507 void r600_suspend_nontimer_queries(struct r600_common_context *ctx);
 508 void r600_resume_nontimer_queries(struct r600_common_context *ctx);
 509 void r600_suspend_timer_queries(struct r600_common_context *ctx);
 510 void r600_resume_timer_queries(struct r600_common_context *ctx);
 511 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 512
 513 /* r600_streamout.c */
 514 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 515 void r600_set_streamout_targets(struct pipe_context *ctx,
 516                                 unsigned num_targets,
 517                                 struct pipe_stream_output_target **targets,
 518                                 const unsigned *offset);
 519 void r600_emit_streamout_end(struct r600_common_context *rctx);
 520 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 521                                              unsigned type, int diff);
 522 void r600_streamout_init(struct r600_common_context *rctx);
 523
 524 /* r600_texture.c */
 525 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 526                                  struct r600_texture *rtex,
 527                                  unsigned nr_samples,
 528                                  struct r600_fmask_info *out);
 529 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 530                                  struct r600_texture *rtex,
 531                                  struct r600_cmask_info *out);
 532 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 533                                      struct pipe_resource *texture,
 534                                      struct r600_texture **staging);
 535 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 536                                         const struct pipe_resource *templ);
 537 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 538                                                 struct pipe_resource *texture,
 539                                                 const struct pipe_surface *templ,
 540                                                 unsigned width, unsigned height);
 541 unsigned r600_translate_colorswap(enum pipe_format format);
 542 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 543                                    struct pipe_framebuffer_state *fb,
 544                                    struct r600_atom *fb_state,
 545                                    unsigned *buffers,
 546                                    const union pipe_color_union *color);
 547 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 548 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 549
 550 /* cayman_msaa.c */
 551 extern const uint32_t eg_sample_locs_2x[4];
 552 extern const unsigned eg_max_dist_2x;
 553 extern const uint32_t eg_sample_locs_4x[4];
 554 extern const unsigned eg_max_dist_4x;
 555 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 556                                 unsigned sample_index, float *out_value);
 557 void cayman_init_msaa(struct pipe_context *ctx);
 558 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 559 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 560                              int ps_iter_samples, int overrast_samples);
 561
 562
 563 /* Inline helpers. */
 564
 565 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 566 {
 567         return (struct r600_resource*)r;
 568 }
 569
 570 static inline void
 571 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 572 {
 573         pipe_resource_reference((struct pipe_resource **)ptr,
 574                                 (struct pipe_resource *)res);
 575 }
 576
 577 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 578 {
 579         if (filter <= 1)   return 0;
 580         if (filter <= 2)   return 1;
 581         if (filter <= 4)   return 2;
 582         if (filter <= 8)   return 3;
 583          /* else */        return 4;
 584 }
 585
 586 static inline unsigned r600_wavefront_size(enum radeon_family family)
 587 {
 588         switch (family) {
 589         case CHIP_RV610:
 590         case CHIP_RS780:
 591         case CHIP_RV620:
 592         case CHIP_RS880:
 593                 return 16;
 594         case CHIP_RV630:
 595         case CHIP_RV635:
 596         case CHIP_RV730:
 597         case CHIP_RV710:
 598         case CHIP_PALM:
 599         case CHIP_CEDAR:
 600                 return 32;
 601         default:
 602                 return 64;
 603         }
 604 }
 605
 606 #define COMPUTE_DBG(rscreen, fmt, args...) \
 607         do { \
 608                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 609         } while (0);
 610
 611 #define R600_ERR(fmt, args...) \
 612         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
 613
 614 /* For MSAA sample positions. */
 615 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 616         (((s0x) & 0xf) | (((s0y) & 0xf) << 4) |            \
 617         (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |     \
 618         (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |    \
 619          (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
 620
 621 #endif