src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/u_slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define ATI_VENDOR_ID 0x1002
  47
  48 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  49 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  50 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  51 #define R600_RESOURCE_FLAG_DISABLE_DCC          (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
  52
  53 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  54 /* Pipeline & streamout query controls. */
  55 #define R600_CONTEXT_START_PIPELINE_STATS       (1u << 1)
  56 #define R600_CONTEXT_STOP_PIPELINE_STATS        (1u << 2)
  57 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 3)
  58
  59 /* special primitive types */
  60 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  61
  62 /* Debug flags. */
  63 /* logging */
  64 #define DBG_TEX                 (1 << 0)
  65 /* gap - reuse */
  66 #define DBG_COMPUTE             (1 << 2)
  67 #define DBG_VM                  (1 << 3)
  68 /* gap - reuse */
  69 /* shader logging */
  70 #define DBG_FS                  (1 << 5)
  71 #define DBG_VS                  (1 << 6)
  72 #define DBG_GS                  (1 << 7)
  73 #define DBG_PS                  (1 << 8)
  74 #define DBG_CS                  (1 << 9)
  75 #define DBG_TCS                 (1 << 10)
  76 #define DBG_TES                 (1 << 11)
  77 #define DBG_NO_IR               (1 << 12)
  78 #define DBG_NO_TGSI             (1 << 13)
  79 #define DBG_NO_ASM              (1 << 14)
  80 #define DBG_PREOPT_IR           (1 << 15)
  81 /* gaps */
  82 #define DBG_TEST_DMA            (1 << 20)
  83 /* Bits 21-31 are reserved for the r600g driver. */
  84 /* features */
  85 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  86 #define DBG_NO_HYPERZ           (1llu << 33)
  87 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  88 #define DBG_NO_2D_TILING        (1llu << 35)
  89 #define DBG_NO_TILING           (1llu << 36)
  90 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  91 #define DBG_FORCE_DMA           (1llu << 38)
  92 #define DBG_PRECOMPILE          (1llu << 39)
  93 #define DBG_INFO                (1llu << 40)
  94 #define DBG_NO_WC               (1llu << 41)
  95 #define DBG_CHECK_VM            (1llu << 42)
  96 #define DBG_NO_DCC              (1llu << 43)
  97 #define DBG_NO_DCC_CLEAR        (1llu << 44)
  98 #define DBG_NO_RB_PLUS          (1llu << 45)
  99 #define DBG_SI_SCHED            (1llu << 46)
 100 #define DBG_MONOLITHIC_SHADERS  (1llu << 47)
 101 #define DBG_NO_CE               (1llu << 48)
 102 #define DBG_UNSAFE_MATH         (1llu << 49)
 103 #define DBG_NO_DCC_FB           (1llu << 50)
 104
 105 #define R600_MAP_BUFFER_ALIGNMENT 64
 106 #define R600_MAX_VIEWPORTS        16
 107
 108 enum r600_coherency {
 109         R600_COHERENCY_NONE, /* no cache flushes needed */
 110         R600_COHERENCY_SHADER,
 111         R600_COHERENCY_CB_META,
 112 };
 113
 114 #ifdef PIPE_ARCH_BIG_ENDIAN
 115 #define R600_BIG_ENDIAN 1
 116 #else
 117 #define R600_BIG_ENDIAN 0
 118 #endif
 119
 120 struct r600_common_context;
 121 struct r600_perfcounters;
 122 struct tgsi_shader_info;
 123
 124 struct radeon_shader_reloc {
 125         char name[32];
 126         uint64_t offset;
 127 };
 128
 129 struct radeon_shader_binary {
 130         /** Shader code */
 131         unsigned char *code;
 132         unsigned code_size;
 133
 134         /** Config/Context register state that accompanies this shader.
 135          * This is a stream of dword pairs.  First dword contains the
 136          * register address, the second dword contains the value.*/
 137         unsigned char *config;
 138         unsigned config_size;
 139
 140         /** The number of bytes of config information for each global symbol.
 141          */
 142         unsigned config_size_per_symbol;
 143
 144         /** Constant data accessed by the shader.  This will be uploaded
 145          * into a constant buffer. */
 146         unsigned char *rodata;
 147         unsigned rodata_size;
 148
 149         /** List of symbol offsets for the shader */
 150         uint64_t *global_symbol_offsets;
 151         unsigned global_symbol_count;
 152
 153         struct radeon_shader_reloc *relocs;
 154         unsigned reloc_count;
 155
 156         /** Disassembled shader in a string. */
 157         char *disasm_string;
 158         char *llvm_ir_string;
 159 };
 160
 161 void radeon_shader_binary_init(struct radeon_shader_binary *b);
 162 void radeon_shader_binary_clean(struct radeon_shader_binary *b);
 163
 164 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
 165  * at the moment.
 166  */
 167 struct r600_resource {
 168         struct u_resource               b;
 169
 170         /* Winsys objects. */
 171         struct pb_buffer                *buf;
 172         uint64_t                        gpu_address;
 173
 174         /* Resource state. */
 175         enum radeon_bo_domain           domains;
 176
 177         /* The buffer range which is initialized (with a write transfer,
 178          * streamout, DMA, or as a random access target). The rest of
 179          * the buffer is considered invalid and can be mapped unsynchronized.
 180          *
 181          * This allows unsychronized mapping of a buffer range which hasn't
 182          * been used yet. It's for applications which forget to use
 183          * the unsynchronized map flag and expect the driver to figure it out.
 184          */
 185         struct util_range               valid_buffer_range;
 186
 187         /* For buffers only. This indicates that a write operation has been
 188          * performed by TC L2, but the cache hasn't been flushed.
 189          * Any hw block which doesn't use or bypasses TC L2 should check this
 190          * flag and flush the cache before using the buffer.
 191          *
 192          * For example, TC L2 must be flushed if a buffer which has been
 193          * modified by a shader store instruction is about to be used as
 194          * an index buffer. The reason is that VGT DMA index fetching doesn't
 195          * use TC L2.
 196          */
 197         bool                            TC_L2_dirty;
 198
 199         /* Whether the resource has been exported via resource_get_handle. */
 200         bool                            is_shared;
 201         unsigned                        external_usage; /* PIPE_HANDLE_USAGE_* */
 202 };
 203
 204 struct r600_transfer {
 205         struct pipe_transfer            transfer;
 206         struct r600_resource            *staging;
 207         unsigned                        offset;
 208 };
 209
 210 struct r600_fmask_info {
 211         uint64_t offset;
 212         uint64_t size;
 213         unsigned alignment;
 214         unsigned pitch_in_pixels;
 215         unsigned bank_height;
 216         unsigned slice_tile_max;
 217         unsigned tile_mode_index;
 218 };
 219
 220 struct r600_cmask_info {
 221         uint64_t offset;
 222         uint64_t size;
 223         unsigned alignment;
 224         unsigned pitch;
 225         unsigned height;
 226         unsigned xalign;
 227         unsigned yalign;
 228         unsigned slice_tile_max;
 229         unsigned base_address_reg;
 230 };
 231
 232 struct r600_htile_info {
 233         unsigned pitch;
 234         unsigned height;
 235         unsigned xalign;
 236         unsigned yalign;
 237 };
 238
 239 struct r600_texture {
 240         struct r600_resource            resource;
 241
 242         uint64_t                        size;
 243         unsigned                        num_level0_transfers;
 244         bool                            is_depth;
 245         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 246         unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 247         struct r600_texture             *flushed_depth_texture;
 248         bool                            is_flushing_texture;
 249         struct radeon_surf              surface;
 250
 251         /* Colorbuffer compression and fast clear. */
 252         struct r600_fmask_info          fmask;
 253         struct r600_cmask_info          cmask;
 254         struct r600_resource            *cmask_buffer;
 255         uint64_t                        dcc_offset; /* 0 = disabled */
 256         unsigned                        cb_color_info; /* fast clear enable bit */
 257         unsigned                        color_clear_value[2];
 258         unsigned                        last_msaa_resolve_target_micro_mode;
 259
 260         /* Depth buffer compression and fast clear. */
 261         struct r600_htile_info          htile;
 262         struct r600_resource            *htile_buffer;
 263         bool                            depth_cleared; /* if it was cleared at least once */
 264         float                           depth_clear_value;
 265         bool                            stencil_cleared; /* if it was cleared at least once */
 266         uint8_t                         stencil_clear_value;
 267
 268         bool                            non_disp_tiling; /* R600-Cayman only */
 269
 270         /* Whether the texture is a displayable back buffer and needs DCC
 271          * decompression, which is expensive. Therefore, it's enabled only
 272          * if statistics suggest that it will pay off and it's allocated
 273          * separately. It can't be bound as a sampler by apps. Limited to
 274          * target == 2D and last_level == 0. If enabled, dcc_offset contains
 275          * the absolute GPUVM address, not the relative one.
 276          */
 277         struct r600_resource            *dcc_separate_buffer;
 278         /* When DCC is temporarily disabled, the separate buffer is here. */
 279         struct r600_resource            *last_dcc_separate_buffer;
 280         /* We need to track DCC dirtiness, because st/dri usually calls
 281          * flush_resource twice per frame (not a bug) and we don't wanna
 282          * decompress DCC twice. Also, the dirty tracking must be done even
 283          * if DCC isn't used, because it's required by the DCC usage analysis
 284          * for a possible future enablement.
 285          */
 286         bool                            separate_dcc_dirty;
 287         /* Statistics gathering for the DCC enablement heuristic. */
 288         bool                            dcc_gather_statistics;
 289         /* Estimate of how much this color buffer is written to in units of
 290          * full-screen draws: ps_invocations / (width * height)
 291          * Shader kills, late Z, and blending with trivial discards make it
 292          * inaccurate (we need to count CB updates, not PS invocations).
 293          */
 294         unsigned                        ps_draw_ratio;
 295         /* The number of clears since the last DCC usage analysis. */
 296         unsigned                        num_slow_clears;
 297
 298         /* Counter that should be non-zero if the texture is bound to a
 299          * framebuffer. Implemented in radeonsi only.
 300          */
 301         uint32_t                        framebuffers_bound;
 302 };
 303
 304 struct r600_surface {
 305         struct pipe_surface             base;
 306         const struct radeon_surf_level  *level_info;
 307
 308         bool color_initialized;
 309         bool depth_initialized;
 310
 311         /* Misc. color flags. */
 312         bool alphatest_bypass;
 313         bool export_16bpc;
 314         bool color_is_int8;
 315
 316         /* Color registers. */
 317         unsigned cb_color_info;
 318         unsigned cb_color_base;
 319         unsigned cb_color_view;
 320         unsigned cb_color_size;         /* R600 only */
 321         unsigned cb_color_dim;          /* EG only */
 322         unsigned cb_color_pitch;        /* EG and later */
 323         unsigned cb_color_slice;        /* EG and later */
 324         unsigned cb_color_attrib;       /* EG and later */
 325         unsigned cb_dcc_control;        /* VI and later */
 326         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 327         unsigned cb_color_fmask_slice;  /* EG and later */
 328         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 329         unsigned cb_color_mask;         /* R600 only */
 330         unsigned spi_shader_col_format;         /* SI+, no blending, no alpha-to-coverage. */
 331         unsigned spi_shader_col_format_alpha;   /* SI+, alpha-to-coverage */
 332         unsigned spi_shader_col_format_blend;   /* SI+, blending without alpha. */
 333         unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
 334         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 335         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 336
 337         /* DB registers. */
 338         unsigned db_depth_info;         /* R600 only, then SI and later */
 339         unsigned db_z_info;             /* EG and later */
 340         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 341         unsigned db_depth_view;
 342         unsigned db_depth_size;
 343         unsigned db_depth_slice;        /* EG and later */
 344         unsigned db_stencil_base;       /* EG and later */
 345         unsigned db_stencil_info;       /* EG and later */
 346         unsigned db_prefetch_limit;     /* R600 only */
 347         unsigned db_htile_surface;
 348         unsigned db_htile_data_base;
 349         unsigned db_preload_control;    /* EG and later */
 350 };
 351
 352 struct r600_common_screen {
 353         struct pipe_screen              b;
 354         struct radeon_winsys            *ws;
 355         enum radeon_family              family;
 356         enum chip_class                 chip_class;
 357         struct radeon_info              info;
 358         uint64_t                        debug_flags;
 359         bool                            has_cp_dma;
 360         bool                            has_streamout;
 361
 362         /* Texture filter settings. */
 363         int                             force_aniso; /* -1 = disabled */
 364
 365         /* Auxiliary context. Mainly used to initialize resources.
 366          * It must be locked prior to using and flushed before unlocking. */
 367         struct pipe_context             *aux_context;
 368         pipe_mutex                      aux_context_lock;
 369
 370         /* This must be in the screen, because UE4 uses one context for
 371          * compilation and another one for rendering.
 372          */
 373         unsigned                        num_compilations;
 374         /* Along with ST_DEBUG=precompile, this should show if applications
 375          * are loading shaders on demand. This is a monotonic counter.
 376          */
 377         unsigned                        num_shaders_created;
 378
 379         /* GPU load thread. */
 380         pipe_mutex                      gpu_load_mutex;
 381         pipe_thread                     gpu_load_thread;
 382         unsigned                        gpu_load_counter_busy;
 383         unsigned                        gpu_load_counter_idle;
 384         volatile unsigned               gpu_load_stop_thread; /* bool */
 385
 386         char                            renderer_string[64];
 387
 388         /* Performance counters. */
 389         struct r600_perfcounters        *perfcounters;
 390
 391         /* If pipe_screen wants to re-emit the framebuffer state of all
 392          * contexts, it should atomically increment this. Each context will
 393          * compare this with its own last known value of the counter before
 394          * drawing and re-emit the framebuffer state accordingly.
 395          */
 396         unsigned                        dirty_fb_counter;
 397
 398         /* Atomically increment this counter when an existing texture's
 399          * metadata is enabled or disabled in a way that requires changing
 400          * contexts' compressed texture binding masks.
 401          */
 402         unsigned                        compressed_colortex_counter;
 403
 404         /* Atomically increment this counter when an existing texture's
 405          * backing buffer or tile mode parameters have changed that requires
 406          * recomputation of shader descriptors.
 407          */
 408         unsigned                        dirty_tex_descriptor_counter;
 409
 410         void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
 411                                       struct r600_texture *rtex,
 412                                       struct radeon_bo_metadata *md);
 413
 414         void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
 415                                     struct r600_texture *rtex,
 416                                     struct radeon_bo_metadata *md);
 417 };
 418
 419 /* This encapsulates a state or an operation which can emitted into the GPU
 420  * command stream. */
 421 struct r600_atom {
 422         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 423         unsigned                num_dw;
 424         unsigned short          id;
 425 };
 426
 427 struct r600_so_target {
 428         struct pipe_stream_output_target b;
 429
 430         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 431         struct r600_resource    *buf_filled_size;
 432         unsigned                buf_filled_size_offset;
 433         bool                    buf_filled_size_valid;
 434
 435         unsigned                stride_in_dw;
 436 };
 437
 438 struct r600_streamout {
 439         struct r600_atom                begin_atom;
 440         bool                            begin_emitted;
 441         unsigned                        num_dw_for_end;
 442
 443         unsigned                        enabled_mask;
 444         unsigned                        num_targets;
 445         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 446
 447         unsigned                        append_bitmask;
 448         bool                            suspended;
 449
 450         /* External state which comes from the vertex shader,
 451          * it must be set explicitly when binding a shader. */
 452         unsigned                        *stride_in_dw;
 453         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 454
 455         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 456         unsigned                        hw_enabled_mask;
 457
 458         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 459         struct r600_atom                enable_atom;
 460         bool                            streamout_enabled;
 461         bool                            prims_gen_query_enabled;
 462         int                             num_prims_gen_queries;
 463 };
 464
 465 struct r600_signed_scissor {
 466         int minx;
 467         int miny;
 468         int maxx;
 469         int maxy;
 470 };
 471
 472 struct r600_scissors {
 473         struct r600_atom                atom;
 474         unsigned                        dirty_mask;
 475         struct pipe_scissor_state       states[R600_MAX_VIEWPORTS];
 476 };
 477
 478 struct r600_viewports {
 479         struct r600_atom                atom;
 480         unsigned                        dirty_mask;
 481         struct pipe_viewport_state      states[R600_MAX_VIEWPORTS];
 482         struct r600_signed_scissor      as_scissor[R600_MAX_VIEWPORTS];
 483 };
 484
 485 struct r600_ring {
 486         struct radeon_winsys_cs         *cs;
 487         void (*flush)(void *ctx, unsigned flags,
 488                       struct pipe_fence_handle **fence);
 489 };
 490
 491 /* Saved CS data for debugging features. */
 492 struct radeon_saved_cs {
 493         uint32_t                        *ib;
 494         unsigned                        num_dw;
 495
 496         struct radeon_bo_list_item      *bo_list;
 497         unsigned                        bo_count;
 498 };
 499
 500 struct r600_common_context {
 501         struct pipe_context b; /* base class */
 502
 503         struct r600_common_screen       *screen;
 504         struct radeon_winsys            *ws;
 505         struct radeon_winsys_ctx        *ctx;
 506         enum radeon_family              family;
 507         enum chip_class                 chip_class;
 508         struct r600_ring                gfx;
 509         struct r600_ring                dma;
 510         struct pipe_fence_handle        *last_sdma_fence;
 511         unsigned                        initial_gfx_cs_size;
 512         unsigned                        gpu_reset_counter;
 513         unsigned                        last_dirty_fb_counter;
 514         unsigned                        last_compressed_colortex_counter;
 515         unsigned                        last_dirty_tex_descriptor_counter;
 516
 517         struct u_upload_mgr             *uploader;
 518         struct u_suballocator           *allocator_zeroed_memory;
 519         struct util_slab_mempool        pool_transfers;
 520
 521         /* Current unaccounted memory usage. */
 522         uint64_t                        vram;
 523         uint64_t                        gtt;
 524
 525         /* States. */
 526         struct r600_streamout           streamout;
 527         struct r600_scissors            scissors;
 528         struct r600_viewports           viewports;
 529         bool                            scissor_enabled;
 530         bool                            vs_writes_viewport_index;
 531         bool                            vs_disables_clipping_viewport;
 532
 533         /* Additional context states. */
 534         unsigned flags; /* flush flags */
 535
 536         /* Queries. */
 537         /* Maintain the list of active queries for pausing between IBs. */
 538         int                             num_occlusion_queries;
 539         int                             num_perfect_occlusion_queries;
 540         struct list_head                active_queries;
 541         unsigned                        num_cs_dw_queries_suspend;
 542         /* Additional hardware info. */
 543         unsigned                        backend_mask;
 544         unsigned                        max_db; /* for OQ */
 545         /* Misc stats. */
 546         unsigned                        num_draw_calls;
 547         unsigned                        num_spill_draw_calls;
 548         unsigned                        num_compute_calls;
 549         unsigned                        num_spill_compute_calls;
 550         unsigned                        num_dma_calls;
 551         uint64_t                        num_alloc_tex_transfer_bytes;
 552         unsigned                        last_tex_ps_draw_ratio; /* for query */
 553
 554         /* Render condition. */
 555         struct r600_atom                render_cond_atom;
 556         struct pipe_query               *render_cond;
 557         unsigned                        render_cond_mode;
 558         bool                            render_cond_invert;
 559         bool                            render_cond_force_off; /* for u_blitter */
 560
 561         /* MSAA sample locations.
 562          * The first index is the sample index.
 563          * The second index is the coordinate: X, Y. */
 564         float                           sample_locations_1x[1][2];
 565         float                           sample_locations_2x[2][2];
 566         float                           sample_locations_4x[4][2];
 567         float                           sample_locations_8x[8][2];
 568         float                           sample_locations_16x[16][2];
 569
 570         /* Statistics gathering for the DCC enablement heuristic. It can't be
 571          * in r600_texture because r600_texture can be shared by multiple
 572          * contexts. This is for back buffers only. We shouldn't get too many
 573          * of those.
 574          *
 575          * X11 DRI3 rotates among a finite set of back buffers. They should
 576          * all fit in this array. If they don't, separate DCC might never be
 577          * enabled by DCC stat gathering.
 578          */
 579         struct {
 580                 struct r600_texture             *tex;
 581                 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
 582                 struct pipe_query               *ps_stats[3];
 583                 /* If all slots are used and another slot is needed,
 584                  * the least recently used slot is evicted based on this. */
 585                 int64_t                         last_use_timestamp;
 586                 bool                            query_active;
 587         } dcc_stats[5];
 588
 589         /* The list of all texture buffer objects in this context.
 590          * This list is walked when a buffer is invalidated/reallocated and
 591          * the GPU addresses are updated. */
 592         struct list_head                texture_buffers;
 593
 594         struct pipe_debug_callback      debug;
 595
 596         /* Copy one resource to another using async DMA. */
 597         void (*dma_copy)(struct pipe_context *ctx,
 598                          struct pipe_resource *dst,
 599                          unsigned dst_level,
 600                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 601                          struct pipe_resource *src,
 602                          unsigned src_level,
 603                          const struct pipe_box *src_box);
 604
 605         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 606                              uint64_t offset, uint64_t size, unsigned value,
 607                              enum r600_coherency coher);
 608
 609         void (*blit_decompress_depth)(struct pipe_context *ctx,
 610                                       struct r600_texture *texture,
 611                                       struct r600_texture *staging,
 612                                       unsigned first_level, unsigned last_level,
 613                                       unsigned first_layer, unsigned last_layer,
 614                                       unsigned first_sample, unsigned last_sample);
 615
 616         void (*decompress_dcc)(struct pipe_context *ctx,
 617                                struct r600_texture *rtex);
 618
 619         /* Reallocate the buffer and update all resource bindings where
 620          * the buffer is bound, including all resource descriptors. */
 621         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 622
 623         /* Enable or disable occlusion queries. */
 624         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 625
 626         /* This ensures there is enough space in the command stream. */
 627         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 628                                   bool include_draw_vbo);
 629
 630         void (*set_atom_dirty)(struct r600_common_context *ctx,
 631                                struct r600_atom *atom, bool dirty);
 632
 633         void (*check_vm_faults)(struct r600_common_context *ctx,
 634                                 struct radeon_saved_cs *saved,
 635                                 enum ring_type ring);
 636 };
 637
 638 /* r600_buffer.c */
 639 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 640                                      struct pb_buffer *buf,
 641                                      enum radeon_bo_usage usage);
 642 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 643                                       struct r600_resource *resource,
 644                                       unsigned usage);
 645 bool r600_init_resource(struct r600_common_screen *rscreen,
 646                         struct r600_resource *res,
 647                         uint64_t size, unsigned alignment);
 648 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 649                                          const struct pipe_resource *templ,
 650                                          unsigned alignment);
 651 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
 652                                                   unsigned bind,
 653                                                   unsigned usage,
 654                                                   unsigned size,
 655                                                   unsigned alignment);
 656 struct pipe_resource *
 657 r600_buffer_from_user_memory(struct pipe_screen *screen,
 658                              const struct pipe_resource *templ,
 659                              void *user_memory);
 660 void
 661 r600_invalidate_resource(struct pipe_context *ctx,
 662                          struct pipe_resource *resource);
 663
 664 /* r600_common_pipe.c */
 665 void r600_draw_rectangle(struct blitter_context *blitter,
 666                          int x1, int y1, int x2, int y2, float depth,
 667                          enum blitter_attrib_type type,
 668                          const union pipe_color_union *attrib);
 669 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 670                              struct radeon_winsys *ws);
 671 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 672 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 673 void r600_postflush_resume_features(struct r600_common_context *ctx);
 674 bool r600_common_context_init(struct r600_common_context *rctx,
 675                               struct r600_common_screen *rscreen);
 676 void r600_common_context_cleanup(struct r600_common_context *rctx);
 677 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 678 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 679                           unsigned processor);
 680 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 681                               uint64_t offset, uint64_t size, unsigned value,
 682                               enum r600_coherency coher);
 683 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 684                                                   const struct pipe_resource *templ);
 685 const char *r600_get_llvm_processor_name(enum radeon_family family);
 686 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
 687                          struct r600_resource *dst, struct r600_resource *src);
 688 void r600_dma_emit_wait_idle(struct r600_common_context *rctx);
 689 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
 690                     struct radeon_saved_cs *saved);
 691 void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
 692
 693 /* r600_gpu_load.c */
 694 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 695 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
 696 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 697
 698 /* r600_perfcounters.c */
 699 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
 700
 701 /* r600_query.c */
 702 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
 703 void r600_query_init(struct r600_common_context *rctx);
 704 void r600_suspend_queries(struct r600_common_context *ctx);
 705 void r600_resume_queries(struct r600_common_context *ctx);
 706 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 707
 708 /* r600_streamout.c */
 709 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 710 void r600_set_streamout_targets(struct pipe_context *ctx,
 711                                 unsigned num_targets,
 712                                 struct pipe_stream_output_target **targets,
 713                                 const unsigned *offset);
 714 void r600_emit_streamout_end(struct r600_common_context *rctx);
 715 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 716                                              unsigned type, int diff);
 717 void r600_streamout_init(struct r600_common_context *rctx);
 718
 719 /* r600_test_dma.c */
 720 void r600_test_dma(struct r600_common_screen *rscreen);
 721
 722 /* r600_texture.c */
 723 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
 724                                 struct r600_texture *rdst,
 725                                 unsigned dst_level, unsigned dstx,
 726                                 unsigned dsty, unsigned dstz,
 727                                 struct r600_texture *rsrc,
 728                                 unsigned src_level,
 729                                 const struct pipe_box *src_box);
 730 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 731                                  struct r600_texture *rtex,
 732                                  unsigned nr_samples,
 733                                  struct r600_fmask_info *out);
 734 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 735                                  struct r600_texture *rtex,
 736                                  struct r600_cmask_info *out);
 737 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 738                                      struct pipe_resource *texture,
 739                                      struct r600_texture **staging);
 740 void r600_print_texture_info(struct r600_texture *rtex, FILE *f);
 741 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 742                                         const struct pipe_resource *templ);
 743 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 744                                                 struct pipe_resource *texture,
 745                                                 const struct pipe_surface *templ,
 746                                                 unsigned width, unsigned height);
 747 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
 748 void vi_separate_dcc_start_query(struct pipe_context *ctx,
 749                                  struct r600_texture *tex);
 750 void vi_separate_dcc_stop_query(struct pipe_context *ctx,
 751                                 struct r600_texture *tex);
 752 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
 753                                              struct r600_texture *tex);
 754 void vi_dcc_clear_level(struct r600_common_context *rctx,
 755                         struct r600_texture *rtex,
 756                         unsigned level, unsigned clear_value);
 757 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 758                                    struct pipe_framebuffer_state *fb,
 759                                    struct r600_atom *fb_state,
 760                                    unsigned *buffers, unsigned *dirty_cbufs,
 761                                    const union pipe_color_union *color);
 762 bool r600_texture_disable_dcc(struct r600_common_screen *rscreen,
 763                               struct r600_texture *rtex);
 764 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 765 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 766
 767 /* r600_viewport.c */
 768 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
 769                                             struct pipe_scissor_state *scissor);
 770 void r600_set_scissor_enable(struct r600_common_context *rctx, bool enable);
 771 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
 772                                           struct tgsi_shader_info *info);
 773 void r600_init_viewport_functions(struct r600_common_context *rctx);
 774
 775 /* cayman_msaa.c */
 776 extern const uint32_t eg_sample_locs_2x[4];
 777 extern const unsigned eg_max_dist_2x;
 778 extern const uint32_t eg_sample_locs_4x[4];
 779 extern const unsigned eg_max_dist_4x;
 780 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 781                                 unsigned sample_index, float *out_value);
 782 void cayman_init_msaa(struct pipe_context *ctx);
 783 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 784 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 785                              int ps_iter_samples, int overrast_samples,
 786                              unsigned sc_mode_cntl_1);
 787
 788
 789 /* Inline helpers. */
 790
 791 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 792 {
 793         return (struct r600_resource*)r;
 794 }
 795
 796 static inline void
 797 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 798 {
 799         pipe_resource_reference((struct pipe_resource **)ptr,
 800                                 (struct pipe_resource *)res);
 801 }
 802
 803 static inline void
 804 r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
 805 {
 806         pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
 807 }
 808
 809 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
 810 {
 811         return rctx->streamout.streamout_enabled ||
 812                rctx->streamout.prims_gen_query_enabled;
 813 }
 814
 815 #define     SQ_TEX_XY_FILTER_POINT                         0x00
 816 #define     SQ_TEX_XY_FILTER_BILINEAR                      0x01
 817 #define     SQ_TEX_XY_FILTER_ANISO_POINT                   0x02
 818 #define     SQ_TEX_XY_FILTER_ANISO_BILINEAR                0x03
 819
 820 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
 821 {
 822         if (filter == PIPE_TEX_FILTER_LINEAR)
 823                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
 824                                      : SQ_TEX_XY_FILTER_BILINEAR;
 825         else
 826                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
 827                                      : SQ_TEX_XY_FILTER_POINT;
 828 }
 829
 830 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 831 {
 832         if (filter < 2)
 833                 return 0;
 834         if (filter < 4)
 835                 return 1;
 836         if (filter < 8)
 837                 return 2;
 838         if (filter < 16)
 839                 return 3;
 840         return 4;
 841 }
 842
 843 static inline unsigned r600_wavefront_size(enum radeon_family family)
 844 {
 845         switch (family) {
 846         case CHIP_RV610:
 847         case CHIP_RS780:
 848         case CHIP_RV620:
 849         case CHIP_RS880:
 850                 return 16;
 851         case CHIP_RV630:
 852         case CHIP_RV635:
 853         case CHIP_RV730:
 854         case CHIP_RV710:
 855         case CHIP_PALM:
 856         case CHIP_CEDAR:
 857                 return 32;
 858         default:
 859                 return 64;
 860         }
 861 }
 862
 863 static inline enum radeon_bo_priority
 864 r600_get_sampler_view_priority(struct r600_resource *res)
 865 {
 866         if (res->b.b.target == PIPE_BUFFER)
 867                 return RADEON_PRIO_SAMPLER_BUFFER;
 868
 869         if (res->b.b.nr_samples > 1)
 870                 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
 871
 872         return RADEON_PRIO_SAMPLER_TEXTURE;
 873 }
 874
 875 #define COMPUTE_DBG(rscreen, fmt, args...) \
 876         do { \
 877                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 878         } while (0);
 879
 880 #define R600_ERR(fmt, args...) \
 881         fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
 882
 883 /* For MSAA sample positions. */
 884 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 885         (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) |                  \
 886         (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) |         \
 887         (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) |        \
 888          (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
 889
 890 #endif