2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
37 #include "amd/common/ac_binary.h"
39 #include "radeon/radeon_winsys.h"
41 #include "util/disk_cache.h"
42 #include "util/u_blitter.h"
43 #include "util/list.h"
44 #include "util/u_range.h"
45 #include "util/slab.h"
46 #include "util/u_suballoc.h"
47 #include "util/u_transfer.h"
48 #include "util/u_threaded_context.h"
52 #define ATI_VENDOR_ID 0x1002
54 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
55 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
56 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
57 #define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
58 #define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
60 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
61 /* Pipeline & streamout query controls. */
62 #define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
63 #define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
64 #define R600_CONTEXT_FLUSH_FOR_RENDER_COND (1u << 3)
65 #define R600_CONTEXT_PRIVATE_FLAG (1u << 4)
67 /* special primitive types */
68 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
70 #define R600_NOT_QUERY 0xffffffff
73 #define DBG_VS (1 << PIPE_SHADER_VERTEX)
74 #define DBG_PS (1 << PIPE_SHADER_FRAGMENT)
75 #define DBG_GS (1 << PIPE_SHADER_GEOMETRY)
76 #define DBG_TCS (1 << PIPE_SHADER_TESS_CTRL)
77 #define DBG_TES (1 << PIPE_SHADER_TESS_EVAL)
78 #define DBG_CS (1 << PIPE_SHADER_COMPUTE)
79 #define DBG_ALL_SHADERS (DBG_FS - 1)
80 #define DBG_FS (1 << 6) /* fetch shader */
81 #define DBG_TEX (1 << 7)
82 #define DBG_NIR (1 << 8)
83 #define DBG_COMPUTE (1 << 9)
85 #define DBG_VM (1 << 11)
86 #define DBG_NO_IR (1 << 12)
87 #define DBG_NO_TGSI (1 << 13)
88 #define DBG_NO_ASM (1 << 14)
89 #define DBG_PREOPT_IR (1 << 15)
90 #define DBG_CHECK_IR (1 << 16)
91 #define DBG_NO_OPT_VARIANT (1 << 17)
92 #define DBG_FS_CORRECT_DERIVS_AFTER_KILL (1 << 18)
94 #define DBG_TEST_DMA (1 << 20)
95 /* Bits 21-31 are reserved for the r600g driver. */
97 #define DBG_NO_ASYNC_DMA (1ull << 32)
98 #define DBG_NO_HYPERZ (1ull << 33)
99 #define DBG_NO_DISCARD_RANGE (1ull << 34)
100 #define DBG_NO_2D_TILING (1ull << 35)
101 #define DBG_NO_TILING (1ull << 36)
102 #define DBG_SWITCH_ON_EOP (1ull << 37)
103 #define DBG_FORCE_DMA (1ull << 38)
104 #define DBG_PRECOMPILE (1ull << 39)
105 #define DBG_INFO (1ull << 40)
106 #define DBG_NO_WC (1ull << 41)
107 #define DBG_CHECK_VM (1ull << 42)
108 #define DBG_NO_DCC (1ull << 43)
109 #define DBG_NO_DCC_CLEAR (1ull << 44)
110 #define DBG_NO_RB_PLUS (1ull << 45)
111 #define DBG_SI_SCHED (1ull << 46)
112 #define DBG_MONOLITHIC_SHADERS (1ull << 47)
113 #define DBG_NO_OUT_OF_ORDER (1ull << 48)
114 #define DBG_UNSAFE_MATH (1ull << 49)
115 #define DBG_NO_DCC_FB (1ull << 50)
116 #define DBG_TEST_VMFAULT_CP (1ull << 51)
117 #define DBG_TEST_VMFAULT_SDMA (1ull << 52)
118 #define DBG_TEST_VMFAULT_SHADER (1ull << 53)
119 #define DBG_NO_DPBB (1ull << 54)
120 #define DBG_NO_DFSM (1ull << 55)
122 #define R600_MAP_BUFFER_ALIGNMENT 64
123 #define R600_MAX_VIEWPORTS 16
125 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
127 enum r600_coherency
{
128 R600_COHERENCY_NONE
, /* no cache flushes needed */
129 R600_COHERENCY_SHADER
,
130 R600_COHERENCY_CB_META
,
133 #ifdef PIPE_ARCH_BIG_ENDIAN
134 #define R600_BIG_ENDIAN 1
136 #define R600_BIG_ENDIAN 0
139 struct r600_common_context
;
140 struct r600_perfcounters
;
141 struct tgsi_shader_info
;
142 struct r600_qbo_state
;
144 void si_radeon_shader_binary_init(struct ac_shader_binary
*b
);
145 void si_radeon_shader_binary_clean(struct ac_shader_binary
*b
);
147 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
150 struct r600_resource
{
151 struct threaded_resource b
;
153 /* Winsys objects. */
154 struct pb_buffer
*buf
;
155 uint64_t gpu_address
;
156 /* Memory usage if the buffer placement is optimal. */
160 /* Resource properties. */
162 unsigned bo_alignment
;
163 enum radeon_bo_domain domains
;
164 enum radeon_bo_flag flags
;
165 unsigned bind_history
;
167 /* The buffer range which is initialized (with a write transfer,
168 * streamout, DMA, or as a random access target). The rest of
169 * the buffer is considered invalid and can be mapped unsynchronized.
171 * This allows unsychronized mapping of a buffer range which hasn't
172 * been used yet. It's for applications which forget to use
173 * the unsynchronized map flag and expect the driver to figure it out.
175 struct util_range valid_buffer_range
;
177 /* For buffers only. This indicates that a write operation has been
178 * performed by TC L2, but the cache hasn't been flushed.
179 * Any hw block which doesn't use or bypasses TC L2 should check this
180 * flag and flush the cache before using the buffer.
182 * For example, TC L2 must be flushed if a buffer which has been
183 * modified by a shader store instruction is about to be used as
184 * an index buffer. The reason is that VGT DMA index fetching doesn't
189 /* Whether the resource has been exported via resource_get_handle. */
190 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
192 /* Whether this resource is referenced by bindless handles. */
193 bool texture_handle_allocated
;
194 bool image_handle_allocated
;
197 struct r600_transfer
{
198 struct threaded_transfer b
;
199 struct r600_resource
*staging
;
203 struct r600_fmask_info
{
207 unsigned pitch_in_pixels
;
208 unsigned bank_height
;
209 unsigned slice_tile_max
;
210 unsigned tile_mode_index
;
211 unsigned tile_swizzle
;
214 struct r600_cmask_info
{
218 unsigned slice_tile_max
;
219 uint64_t base_address_reg
;
222 struct r600_texture
{
223 struct r600_resource resource
;
226 unsigned num_level0_transfers
;
227 enum pipe_format db_render_format
;
232 unsigned dirty_level_mask
; /* each bit says if that mipmap is compressed */
233 unsigned stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
234 struct r600_texture
*flushed_depth_texture
;
235 struct radeon_surf surface
;
237 /* Colorbuffer compression and fast clear. */
238 struct r600_fmask_info fmask
;
239 struct r600_cmask_info cmask
;
240 struct r600_resource
*cmask_buffer
;
241 uint64_t dcc_offset
; /* 0 = disabled */
242 unsigned cb_color_info
; /* fast clear enable bit */
243 unsigned color_clear_value
[2];
244 unsigned last_msaa_resolve_target_micro_mode
;
246 /* Depth buffer compression and fast clear. */
247 uint64_t htile_offset
;
248 bool tc_compatible_htile
;
249 bool depth_cleared
; /* if it was cleared at least once */
250 float depth_clear_value
;
251 bool stencil_cleared
; /* if it was cleared at least once */
252 uint8_t stencil_clear_value
;
254 bool non_disp_tiling
; /* R600-Cayman only */
256 /* Whether the texture is a displayable back buffer and needs DCC
257 * decompression, which is expensive. Therefore, it's enabled only
258 * if statistics suggest that it will pay off and it's allocated
259 * separately. It can't be bound as a sampler by apps. Limited to
260 * target == 2D and last_level == 0. If enabled, dcc_offset contains
261 * the absolute GPUVM address, not the relative one.
263 struct r600_resource
*dcc_separate_buffer
;
264 /* When DCC is temporarily disabled, the separate buffer is here. */
265 struct r600_resource
*last_dcc_separate_buffer
;
266 /* We need to track DCC dirtiness, because st/dri usually calls
267 * flush_resource twice per frame (not a bug) and we don't wanna
268 * decompress DCC twice. Also, the dirty tracking must be done even
269 * if DCC isn't used, because it's required by the DCC usage analysis
270 * for a possible future enablement.
272 bool separate_dcc_dirty
;
273 /* Statistics gathering for the DCC enablement heuristic. */
274 bool dcc_gather_statistics
;
275 /* Estimate of how much this color buffer is written to in units of
276 * full-screen draws: ps_invocations / (width * height)
277 * Shader kills, late Z, and blending with trivial discards make it
278 * inaccurate (we need to count CB updates, not PS invocations).
280 unsigned ps_draw_ratio
;
281 /* The number of clears since the last DCC usage analysis. */
282 unsigned num_slow_clears
;
284 /* Counter that should be non-zero if the texture is bound to a
285 * framebuffer. Implemented in radeonsi only.
287 uint32_t framebuffers_bound
;
290 struct r600_surface
{
291 struct pipe_surface base
;
293 /* These can vary with block-compressed textures. */
297 bool color_initialized
;
298 bool depth_initialized
;
300 /* Misc. color flags. */
301 bool alphatest_bypass
;
305 bool dcc_incompatible
;
307 /* Color registers. */
308 unsigned cb_color_info
;
309 unsigned cb_color_base
;
310 unsigned cb_color_view
;
311 unsigned cb_color_size
; /* R600 only */
312 unsigned cb_color_dim
; /* EG only */
313 unsigned cb_color_pitch
; /* EG and later */
314 unsigned cb_color_slice
; /* EG and later */
315 unsigned cb_color_attrib
; /* EG and later */
316 unsigned cb_color_attrib2
; /* GFX9 and later */
317 unsigned cb_dcc_control
; /* VI and later */
318 unsigned cb_color_fmask
; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
319 unsigned cb_color_fmask_slice
; /* EG and later */
320 unsigned cb_color_cmask
; /* CB_COLORn_TILE (r600 only) */
321 unsigned cb_color_mask
; /* R600 only */
322 unsigned spi_shader_col_format
; /* SI+, no blending, no alpha-to-coverage. */
323 unsigned spi_shader_col_format_alpha
; /* SI+, alpha-to-coverage */
324 unsigned spi_shader_col_format_blend
; /* SI+, blending without alpha. */
325 unsigned spi_shader_col_format_blend_alpha
; /* SI+, blending with alpha. */
326 struct r600_resource
*cb_buffer_fmask
; /* Used for FMASK relocations. R600 only */
327 struct r600_resource
*cb_buffer_cmask
; /* Used for CMASK relocations. R600 only */
330 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
331 uint64_t db_stencil_base
; /* EG and later */
332 uint64_t db_htile_data_base
;
333 unsigned db_depth_info
; /* R600 only, then SI and later */
334 unsigned db_z_info
; /* EG and later */
335 unsigned db_z_info2
; /* GFX9+ */
336 unsigned db_depth_view
;
337 unsigned db_depth_size
;
338 unsigned db_depth_slice
; /* EG and later */
339 unsigned db_stencil_info
; /* EG and later */
340 unsigned db_stencil_info2
; /* GFX9+ */
341 unsigned db_prefetch_limit
; /* R600 only */
342 unsigned db_htile_surface
;
343 unsigned db_preload_control
; /* EG and later */
346 struct r600_mmio_counter
{
351 union r600_mmio_counters
{
353 /* For global GPU load including SDMA. */
354 struct r600_mmio_counter gpu
;
357 struct r600_mmio_counter spi
;
358 struct r600_mmio_counter gui
;
359 struct r600_mmio_counter ta
;
360 struct r600_mmio_counter gds
;
361 struct r600_mmio_counter vgt
;
362 struct r600_mmio_counter ia
;
363 struct r600_mmio_counter sx
;
364 struct r600_mmio_counter wd
;
365 struct r600_mmio_counter bci
;
366 struct r600_mmio_counter sc
;
367 struct r600_mmio_counter pa
;
368 struct r600_mmio_counter db
;
369 struct r600_mmio_counter cp
;
370 struct r600_mmio_counter cb
;
373 struct r600_mmio_counter sdma
;
376 struct r600_mmio_counter pfp
;
377 struct r600_mmio_counter meq
;
378 struct r600_mmio_counter me
;
379 struct r600_mmio_counter surf_sync
;
380 struct r600_mmio_counter cp_dma
;
381 struct r600_mmio_counter scratch_ram
;
386 struct r600_memory_object
{
387 struct pipe_memory_object b
;
388 struct pb_buffer
*buf
;
393 struct r600_common_screen
{
394 struct pipe_screen b
;
395 struct radeon_winsys
*ws
;
396 enum radeon_family family
;
397 enum chip_class chip_class
;
398 struct radeon_info info
;
399 uint64_t debug_flags
;
402 bool has_rbplus
; /* if RB+ registers exist */
403 bool rbplus_allowed
; /* if RB+ is allowed */
405 struct disk_cache
*disk_shader_cache
;
407 struct slab_parent_pool pool_transfers
;
409 /* Texture filter settings. */
410 int force_aniso
; /* -1 = disabled */
412 /* Auxiliary context. Mainly used to initialize resources.
413 * It must be locked prior to using and flushed before unlocking. */
414 struct pipe_context
*aux_context
;
415 mtx_t aux_context_lock
;
417 /* This must be in the screen, because UE4 uses one context for
418 * compilation and another one for rendering.
420 unsigned num_compilations
;
421 /* Along with ST_DEBUG=precompile, this should show if applications
422 * are loading shaders on demand. This is a monotonic counter.
424 unsigned num_shaders_created
;
425 unsigned num_shader_cache_hits
;
427 /* GPU load thread. */
428 mtx_t gpu_load_mutex
;
429 thrd_t gpu_load_thread
;
430 union r600_mmio_counters mmio_counters
;
431 volatile unsigned gpu_load_stop_thread
; /* bool */
433 char renderer_string
[100];
435 /* Performance counters. */
436 struct r600_perfcounters
*perfcounters
;
438 /* If pipe_screen wants to recompute and re-emit the framebuffer,
439 * sampler, and image states of all contexts, it should atomically
442 * Each context will compare this with its own last known value of
443 * the counter before drawing and re-emit the states accordingly.
445 unsigned dirty_tex_counter
;
447 /* Atomically increment this counter when an existing texture's
448 * metadata is enabled or disabled in a way that requires changing
449 * contexts' compressed texture binding masks.
451 unsigned compressed_colortex_counter
;
454 /* Context flags to set so that all writes from earlier jobs
455 * in the CP are seen by L2 clients.
459 /* Context flags to set so that all writes from earlier jobs
460 * that end in L2 are seen by CP.
464 /* Context flags to set so that all writes from earlier
465 * compute jobs are seen by L2 clients.
467 unsigned compute_to_L2
;
470 void (*query_opaque_metadata
)(struct r600_common_screen
*rscreen
,
471 struct r600_texture
*rtex
,
472 struct radeon_bo_metadata
*md
);
474 void (*apply_opaque_metadata
)(struct r600_common_screen
*rscreen
,
475 struct r600_texture
*rtex
,
476 struct radeon_bo_metadata
*md
);
479 /* This encapsulates a state or an operation which can emitted into the GPU
482 void (*emit
)(struct r600_common_context
*ctx
, struct r600_atom
*state
);
487 struct r600_so_target
{
488 struct pipe_stream_output_target b
;
490 /* The buffer where BUFFER_FILLED_SIZE is stored. */
491 struct r600_resource
*buf_filled_size
;
492 unsigned buf_filled_size_offset
;
493 bool buf_filled_size_valid
;
495 unsigned stride_in_dw
;
498 struct r600_streamout
{
499 struct r600_atom begin_atom
;
501 unsigned num_dw_for_end
;
503 unsigned enabled_mask
;
504 unsigned num_targets
;
505 struct r600_so_target
*targets
[PIPE_MAX_SO_BUFFERS
];
507 unsigned append_bitmask
;
510 /* External state which comes from the vertex shader,
511 * it must be set explicitly when binding a shader. */
512 uint16_t *stride_in_dw
;
513 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
515 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
516 unsigned hw_enabled_mask
;
518 /* The state of VGT_STRMOUT_(CONFIG|EN). */
519 struct r600_atom enable_atom
;
520 bool streamout_enabled
;
521 bool prims_gen_query_enabled
;
522 int num_prims_gen_queries
;
525 struct r600_signed_scissor
{
532 struct r600_scissors
{
533 struct r600_atom atom
;
535 struct pipe_scissor_state states
[R600_MAX_VIEWPORTS
];
538 struct r600_viewports
{
539 struct r600_atom atom
;
541 unsigned depth_range_dirty_mask
;
542 struct pipe_viewport_state states
[R600_MAX_VIEWPORTS
];
543 struct r600_signed_scissor as_scissor
[R600_MAX_VIEWPORTS
];
547 struct radeon_winsys_cs
*cs
;
548 void (*flush
)(void *ctx
, unsigned flags
,
549 struct pipe_fence_handle
**fence
);
552 /* Saved CS data for debugging features. */
553 struct radeon_saved_cs
{
557 struct radeon_bo_list_item
*bo_list
;
561 struct r600_common_context
{
562 struct pipe_context b
; /* base class */
564 struct r600_common_screen
*screen
;
565 struct radeon_winsys
*ws
;
566 struct radeon_winsys_ctx
*ctx
;
567 enum radeon_family family
;
568 enum chip_class chip_class
;
569 struct r600_ring gfx
;
570 struct r600_ring dma
;
571 struct pipe_fence_handle
*last_gfx_fence
;
572 struct pipe_fence_handle
*last_sdma_fence
;
573 struct r600_resource
*eop_bug_scratch
;
574 unsigned num_gfx_cs_flushes
;
575 unsigned initial_gfx_cs_size
;
576 unsigned gpu_reset_counter
;
577 unsigned last_dirty_tex_counter
;
578 unsigned last_compressed_colortex_counter
;
579 unsigned last_num_draw_calls
;
581 struct threaded_context
*tc
;
582 struct u_suballocator
*allocator_zeroed_memory
;
583 struct slab_child_pool pool_transfers
;
584 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
586 /* Current unaccounted memory usage. */
591 struct r600_streamout streamout
;
592 struct r600_scissors scissors
;
593 struct r600_viewports viewports
;
594 bool scissor_enabled
;
596 bool vs_writes_viewport_index
;
597 bool vs_disables_clipping_viewport
;
599 /* Additional context states. */
600 unsigned flags
; /* flush flags */
603 /* Maintain the list of active queries for pausing between IBs. */
604 int num_occlusion_queries
;
605 int num_perfect_occlusion_queries
;
606 struct list_head active_queries
;
607 unsigned num_cs_dw_queries_suspend
;
609 unsigned num_draw_calls
;
610 unsigned num_decompress_calls
;
611 unsigned num_mrt_draw_calls
;
612 unsigned num_prim_restart_calls
;
613 unsigned num_spill_draw_calls
;
614 unsigned num_compute_calls
;
615 unsigned num_spill_compute_calls
;
616 unsigned num_dma_calls
;
617 unsigned num_cp_dma_calls
;
618 unsigned num_vs_flushes
;
619 unsigned num_ps_flushes
;
620 unsigned num_cs_flushes
;
621 unsigned num_cb_cache_flushes
;
622 unsigned num_db_cache_flushes
;
623 unsigned num_L2_invalidates
;
624 unsigned num_L2_writebacks
;
625 unsigned num_resident_handles
;
626 uint64_t num_alloc_tex_transfer_bytes
;
627 unsigned last_tex_ps_draw_ratio
; /* for query */
629 /* Render condition. */
630 struct r600_atom render_cond_atom
;
631 struct pipe_query
*render_cond
;
632 unsigned render_cond_mode
;
633 bool render_cond_invert
;
634 bool render_cond_force_off
; /* for u_blitter */
636 /* MSAA sample locations.
637 * The first index is the sample index.
638 * The second index is the coordinate: X, Y. */
639 float sample_locations_1x
[1][2];
640 float sample_locations_2x
[2][2];
641 float sample_locations_4x
[4][2];
642 float sample_locations_8x
[8][2];
643 float sample_locations_16x
[16][2];
645 /* Statistics gathering for the DCC enablement heuristic. It can't be
646 * in r600_texture because r600_texture can be shared by multiple
647 * contexts. This is for back buffers only. We shouldn't get too many
650 * X11 DRI3 rotates among a finite set of back buffers. They should
651 * all fit in this array. If they don't, separate DCC might never be
652 * enabled by DCC stat gathering.
655 struct r600_texture
*tex
;
656 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
657 struct pipe_query
*ps_stats
[3];
658 /* If all slots are used and another slot is needed,
659 * the least recently used slot is evicted based on this. */
660 int64_t last_use_timestamp
;
664 struct pipe_debug_callback debug
;
665 struct pipe_device_reset_callback device_reset_callback
;
666 struct u_log_context
*log
;
668 void *query_result_shader
;
670 /* Copy one resource to another using async DMA. */
671 void (*dma_copy
)(struct pipe_context
*ctx
,
672 struct pipe_resource
*dst
,
674 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
675 struct pipe_resource
*src
,
677 const struct pipe_box
*src_box
);
679 void (*dma_clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
680 uint64_t offset
, uint64_t size
, unsigned value
);
682 void (*clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
683 uint64_t offset
, uint64_t size
, unsigned value
,
684 enum r600_coherency coher
);
686 void (*blit_decompress_depth
)(struct pipe_context
*ctx
,
687 struct r600_texture
*texture
,
688 struct r600_texture
*staging
,
689 unsigned first_level
, unsigned last_level
,
690 unsigned first_layer
, unsigned last_layer
,
691 unsigned first_sample
, unsigned last_sample
);
693 void (*decompress_dcc
)(struct pipe_context
*ctx
,
694 struct r600_texture
*rtex
);
696 /* Reallocate the buffer and update all resource bindings where
697 * the buffer is bound, including all resource descriptors. */
698 void (*invalidate_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
);
700 /* Update all resource bindings where the buffer is bound, including
701 * all resource descriptors. This is invalidate_buffer without
702 * the invalidation. */
703 void (*rebind_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
704 uint64_t old_gpu_address
);
706 /* Enable or disable occlusion queries. */
707 void (*set_occlusion_query_state
)(struct pipe_context
*ctx
,
709 bool old_perfect_enable
);
711 void (*save_qbo_state
)(struct pipe_context
*ctx
, struct r600_qbo_state
*st
);
713 /* This ensures there is enough space in the command stream. */
714 void (*need_gfx_cs_space
)(struct pipe_context
*ctx
, unsigned num_dw
,
715 bool include_draw_vbo
);
717 void (*set_atom_dirty
)(struct r600_common_context
*ctx
,
718 struct r600_atom
*atom
, bool dirty
);
720 void (*check_vm_faults
)(struct r600_common_context
*ctx
,
721 struct radeon_saved_cs
*saved
,
722 enum ring_type ring
);
725 /* r600_buffer_common.c */
726 bool si_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
727 struct pb_buffer
*buf
,
728 enum radeon_bo_usage usage
);
729 void *si_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
730 struct r600_resource
*resource
,
732 void si_buffer_subdata(struct pipe_context
*ctx
,
733 struct pipe_resource
*buffer
,
734 unsigned usage
, unsigned offset
,
735 unsigned size
, const void *data
);
736 void si_init_resource_fields(struct r600_common_screen
*rscreen
,
737 struct r600_resource
*res
,
738 uint64_t size
, unsigned alignment
);
739 bool si_alloc_resource(struct r600_common_screen
*rscreen
,
740 struct r600_resource
*res
);
741 struct pipe_resource
*si_buffer_create(struct pipe_screen
*screen
,
742 const struct pipe_resource
*templ
,
744 struct pipe_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
749 struct pipe_resource
*
750 si_buffer_from_user_memory(struct pipe_screen
*screen
,
751 const struct pipe_resource
*templ
,
753 void si_invalidate_resource(struct pipe_context
*ctx
,
754 struct pipe_resource
*resource
);
755 void si_replace_buffer_storage(struct pipe_context
*ctx
,
756 struct pipe_resource
*dst
,
757 struct pipe_resource
*src
);
759 /* r600_common_pipe.c */
760 void si_gfx_write_event_eop(struct r600_common_context
*ctx
,
761 unsigned event
, unsigned event_flags
,
763 struct r600_resource
*buf
, uint64_t va
,
764 uint32_t new_fence
, unsigned query_type
);
765 unsigned si_gfx_write_fence_dwords(struct r600_common_screen
*screen
);
766 void si_gfx_wait_fence(struct r600_common_context
*ctx
,
767 uint64_t va
, uint32_t ref
, uint32_t mask
);
768 void si_draw_rectangle(struct blitter_context
*blitter
,
769 int x1
, int y1
, int x2
, int y2
,
770 float depth
, unsigned num_instances
,
771 enum blitter_attrib_type type
,
772 const union blitter_attrib
*attrib
);
773 bool si_common_screen_init(struct r600_common_screen
*rscreen
,
774 struct radeon_winsys
*ws
);
775 void si_destroy_common_screen(struct r600_common_screen
*rscreen
);
776 void si_preflush_suspend_features(struct r600_common_context
*ctx
);
777 void si_postflush_resume_features(struct r600_common_context
*ctx
);
778 bool si_common_context_init(struct r600_common_context
*rctx
,
779 struct r600_common_screen
*rscreen
,
780 unsigned context_flags
);
781 void si_common_context_cleanup(struct r600_common_context
*rctx
);
782 bool si_can_dump_shader(struct r600_common_screen
*rscreen
,
784 bool si_extra_shader_checks(struct r600_common_screen
*rscreen
,
786 void si_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
787 uint64_t offset
, uint64_t size
, unsigned value
);
788 struct pipe_resource
*si_resource_create_common(struct pipe_screen
*screen
,
789 const struct pipe_resource
*templ
);
790 const char *si_get_llvm_processor_name(enum radeon_family family
);
791 void si_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
,
792 struct r600_resource
*dst
, struct r600_resource
*src
);
793 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_winsys_cs
*cs
,
794 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
795 void si_clear_saved_cs(struct radeon_saved_cs
*saved
);
796 bool si_check_device_reset(struct r600_common_context
*rctx
);
798 /* r600_gpu_load.c */
799 void si_gpu_load_kill_thread(struct r600_common_screen
*rscreen
);
800 uint64_t si_begin_counter(struct r600_common_screen
*rscreen
, unsigned type
);
801 unsigned si_end_counter(struct r600_common_screen
*rscreen
, unsigned type
,
804 /* r600_perfcounters.c */
805 void si_perfcounters_destroy(struct r600_common_screen
*rscreen
);
808 void si_init_screen_query_functions(struct r600_common_screen
*rscreen
);
809 void si_init_query_functions(struct r600_common_context
*rctx
);
810 void si_suspend_queries(struct r600_common_context
*ctx
);
811 void si_resume_queries(struct r600_common_context
*ctx
);
813 /* r600_streamout.c */
814 void si_streamout_buffers_dirty(struct r600_common_context
*rctx
);
815 void si_common_set_streamout_targets(struct pipe_context
*ctx
,
816 unsigned num_targets
,
817 struct pipe_stream_output_target
**targets
,
818 const unsigned *offset
);
819 void si_emit_streamout_end(struct r600_common_context
*rctx
);
820 void si_update_prims_generated_query_state(struct r600_common_context
*rctx
,
821 unsigned type
, int diff
);
822 void si_streamout_init(struct r600_common_context
*rctx
);
824 /* r600_test_dma.c */
825 void si_test_dma(struct r600_common_screen
*rscreen
);
828 bool si_prepare_for_dma_blit(struct r600_common_context
*rctx
,
829 struct r600_texture
*rdst
,
830 unsigned dst_level
, unsigned dstx
,
831 unsigned dsty
, unsigned dstz
,
832 struct r600_texture
*rsrc
,
834 const struct pipe_box
*src_box
);
835 void si_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
836 struct r600_texture
*rtex
,
838 struct r600_fmask_info
*out
);
839 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
840 struct pipe_resource
*texture
,
841 struct r600_texture
**staging
);
842 void si_print_texture_info(struct r600_common_screen
*rscreen
,
843 struct r600_texture
*rtex
, struct u_log_context
*log
);
844 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
845 const struct pipe_resource
*templ
);
846 bool vi_dcc_formats_compatible(enum pipe_format format1
,
847 enum pipe_format format2
);
848 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
850 enum pipe_format view_format
);
851 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
852 struct pipe_resource
*tex
,
854 enum pipe_format view_format
);
855 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
856 struct pipe_resource
*texture
,
857 const struct pipe_surface
*templ
,
858 unsigned width0
, unsigned height0
,
859 unsigned width
, unsigned height
);
860 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
861 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
862 struct r600_texture
*tex
);
863 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
864 struct r600_texture
*tex
);
865 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
866 struct r600_texture
*tex
);
867 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
868 struct r600_texture
*rtex
,
869 unsigned level
, unsigned clear_value
);
870 void si_do_fast_color_clear(struct r600_common_context
*rctx
,
871 struct pipe_framebuffer_state
*fb
,
872 struct r600_atom
*fb_state
,
873 unsigned *buffers
, ubyte
*dirty_cbufs
,
874 const union pipe_color_union
*color
);
875 bool si_texture_disable_dcc(struct r600_common_context
*rctx
,
876 struct r600_texture
*rtex
);
877 void si_init_screen_texture_functions(struct r600_common_screen
*rscreen
);
878 void si_init_context_texture_functions(struct r600_common_context
*rctx
);
880 /* r600_viewport.c */
881 void si_apply_scissor_bug_workaround(struct r600_common_context
*rctx
,
882 struct pipe_scissor_state
*scissor
);
883 void si_viewport_set_rast_deps(struct r600_common_context
*rctx
,
884 bool scissor_enable
, bool clip_halfz
);
885 void si_update_vs_writes_viewport_index(struct r600_common_context
*rctx
,
886 struct tgsi_shader_info
*info
);
887 void si_init_viewport_functions(struct r600_common_context
*rctx
);
890 void si_get_sample_position(struct pipe_context
*ctx
, unsigned sample_count
,
891 unsigned sample_index
, float *out_value
);
892 void si_init_msaa(struct pipe_context
*ctx
);
893 void si_common_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
894 void si_common_emit_msaa_config(struct radeon_winsys_cs
*cs
, int nr_samples
,
895 int ps_iter_samples
, int overrast_samples
,
896 unsigned sc_mode_cntl_1
);
899 /* Inline helpers. */
901 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
903 return (struct r600_resource
*)r
;
907 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
909 pipe_resource_reference((struct pipe_resource
**)ptr
,
910 (struct pipe_resource
*)res
);
914 r600_texture_reference(struct r600_texture
**ptr
, struct r600_texture
*res
)
916 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->resource
.b
.b
);
920 r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
922 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
923 struct r600_resource
*res
= (struct r600_resource
*)r
;
926 /* Add memory usage for need_gfx_cs_space */
927 rctx
->vram
+= res
->vram_usage
;
928 rctx
->gtt
+= res
->gart_usage
;
932 static inline bool r600_get_strmout_en(struct r600_common_context
*rctx
)
934 return rctx
->streamout
.streamout_enabled
||
935 rctx
->streamout
.prims_gen_query_enabled
;
938 #define SQ_TEX_XY_FILTER_POINT 0x00
939 #define SQ_TEX_XY_FILTER_BILINEAR 0x01
940 #define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
941 #define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03
943 static inline unsigned eg_tex_filter(unsigned filter
, unsigned max_aniso
)
945 if (filter
== PIPE_TEX_FILTER_LINEAR
)
946 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
947 : SQ_TEX_XY_FILTER_BILINEAR
;
949 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
950 : SQ_TEX_XY_FILTER_POINT
;
953 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
966 static inline unsigned r600_wavefront_size(enum radeon_family family
)
986 static inline enum radeon_bo_priority
987 r600_get_sampler_view_priority(struct r600_resource
*res
)
989 if (res
->b
.b
.target
== PIPE_BUFFER
)
990 return RADEON_PRIO_SAMPLER_BUFFER
;
992 if (res
->b
.b
.nr_samples
> 1)
993 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
995 return RADEON_PRIO_SAMPLER_TEXTURE
;
999 r600_can_sample_zs(struct r600_texture
*tex
, bool stencil_sampler
)
1001 return (stencil_sampler
&& tex
->can_sample_s
) ||
1002 (!stencil_sampler
&& tex
->can_sample_z
);
1006 vi_dcc_enabled(struct r600_texture
*tex
, unsigned level
)
1008 return tex
->dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
1012 r600_htile_enabled(struct r600_texture
*tex
, unsigned level
)
1014 return tex
->htile_offset
&& level
== 0;
1018 vi_tc_compat_htile_enabled(struct r600_texture
*tex
, unsigned level
)
1020 assert(!tex
->tc_compatible_htile
|| tex
->htile_offset
);
1021 return tex
->tc_compatible_htile
&& level
== 0;
1024 #define COMPUTE_DBG(rscreen, fmt, args...) \
1026 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
1029 #define R600_ERR(fmt, args...) \
1030 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1032 /* For MSAA sample positions. */
1033 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1034 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1035 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1036 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1037 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1039 static inline int S_FIXED(float value
, unsigned frac_bits
)
1041 return value
* (1 << frac_bits
);