2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
37 #include "../../winsys/radeon/drm/radeon_winsys.h"
39 #include "util/u_double_list.h"
40 #include "util/u_range.h"
41 #include "util/u_slab.h"
42 #include "util/u_suballoc.h"
43 #include "util/u_transfer.h"
45 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
46 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
47 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
49 #define R600_QUERY_DRAW_CALLS (PIPE_QUERY_DRIVER_SPECIFIC + 0)
50 #define R600_QUERY_REQUESTED_VRAM (PIPE_QUERY_DRIVER_SPECIFIC + 1)
51 #define R600_QUERY_REQUESTED_GTT (PIPE_QUERY_DRIVER_SPECIFIC + 2)
52 #define R600_QUERY_BUFFER_WAIT_TIME (PIPE_QUERY_DRIVER_SPECIFIC + 3)
53 #define R600_QUERY_NUM_CS_FLUSHES (PIPE_QUERY_DRIVER_SPECIFIC + 4)
54 #define R600_QUERY_NUM_BYTES_MOVED (PIPE_QUERY_DRIVER_SPECIFIC + 5)
55 #define R600_QUERY_VRAM_USAGE (PIPE_QUERY_DRIVER_SPECIFIC + 6)
56 #define R600_QUERY_GTT_USAGE (PIPE_QUERY_DRIVER_SPECIFIC + 7)
59 #define R600_CONTEXT_INV_VERTEX_CACHE (1 << 0)
60 #define R600_CONTEXT_INV_TEX_CACHE (1 << 1)
61 #define R600_CONTEXT_INV_CONST_CACHE (1 << 2)
62 #define R600_CONTEXT_INV_SHADER_CACHE (1 << 3)
63 /* read-write caches */
64 #define R600_CONTEXT_STREAMOUT_FLUSH (1 << 8)
65 #define R600_CONTEXT_FLUSH_AND_INV (1 << 9)
66 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (1 << 10)
67 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (1 << 11)
68 #define R600_CONTEXT_FLUSH_AND_INV_DB (1 << 12)
69 #define R600_CONTEXT_FLUSH_AND_INV_CB (1 << 13)
70 /* engine synchronization */
71 #define R600_CONTEXT_PS_PARTIAL_FLUSH (1 << 16)
72 #define R600_CONTEXT_WAIT_3D_IDLE (1 << 17)
73 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (1 << 18)
74 #define R600_CONTEXT_VGT_FLUSH (1 << 19)
75 #define R600_CONTEXT_VGT_STREAMOUT_SYNC (1 << 20)
79 #define DBG_TEX (1 << 0)
80 #define DBG_TEXMIP (1 << 1)
81 #define DBG_COMPUTE (1 << 2)
82 #define DBG_VM (1 << 3)
83 #define DBG_TRACE_CS (1 << 4)
85 #define DBG_FS (1 << 5)
86 #define DBG_VS (1 << 6)
87 #define DBG_GS (1 << 7)
88 #define DBG_PS (1 << 8)
89 #define DBG_CS (1 << 9)
91 #define DBG_NO_ASYNC_DMA (1 << 10)
92 #define DBG_HYPERZ (1 << 11)
93 #define DBG_NO_DISCARD_RANGE (1 << 12)
94 #define DBG_NO_2D_TILING (1 << 13)
95 #define DBG_NO_TILING (1 << 14)
96 #define DBG_SWITCH_ON_EOP (1 << 15)
97 /* The maximum allowed bit is 15. */
99 #define R600_MAP_BUFFER_ALIGNMENT 64
101 struct r600_common_context
;
103 struct radeon_shader_binary
{
108 /** Config/Context register state that accompanies this shader.
109 * This is a stream of dword pairs. First dword contains the
110 * register address, the second dword contains the value.*/
111 unsigned char *config
;
112 unsigned config_size
;
114 /** Constant data accessed by the shader. This will be uploaded
115 * into a constant buffer. */
116 unsigned char *rodata
;
117 unsigned rodata_size
;
119 /** Set to 1 if the disassembly for this binary has been dumped to
124 struct r600_resource
{
127 /* Winsys objects. */
128 struct pb_buffer
*buf
;
129 struct radeon_winsys_cs_handle
*cs_buf
;
131 /* Resource state. */
132 enum radeon_bo_domain domains
;
134 /* The buffer range which is initialized (with a write transfer,
135 * streamout, DMA, or as a random access target). The rest of
136 * the buffer is considered invalid and can be mapped unsynchronized.
138 * This allows unsychronized mapping of a buffer range which hasn't
139 * been used yet. It's for applications which forget to use
140 * the unsynchronized map flag and expect the driver to figure it out.
142 struct util_range valid_buffer_range
;
145 struct r600_transfer
{
146 struct pipe_transfer transfer
;
147 struct r600_resource
*staging
;
151 struct r600_fmask_info
{
156 unsigned bank_height
;
157 unsigned slice_tile_max
;
158 unsigned tile_mode_index
;
161 struct r600_cmask_info
{
165 unsigned slice_tile_max
;
166 unsigned base_address_reg
;
169 struct r600_texture
{
170 struct r600_resource resource
;
173 unsigned pitch_override
;
175 unsigned dirty_level_mask
; /* each bit says if that mipmap is compressed */
176 struct r600_texture
*flushed_depth_texture
;
177 boolean is_flushing_texture
;
178 struct radeon_surface surface
;
180 /* Colorbuffer compression and fast clear. */
181 struct r600_fmask_info fmask
;
182 struct r600_cmask_info cmask
;
183 struct r600_resource
*cmask_buffer
;
184 unsigned cb_color_info
; /* fast clear enable bit */
185 unsigned color_clear_value
[2];
187 /* Depth buffer compression and fast clear. */
188 struct r600_resource
*htile_buffer
;
189 float depth_clear_value
;
191 bool non_disp_tiling
; /* R600-Cayman only */
192 unsigned mipmap_shift
;
195 struct r600_surface
{
196 struct pipe_surface base
;
198 bool color_initialized
;
199 bool depth_initialized
;
201 /* Misc. color flags. */
202 bool alphatest_bypass
;
205 /* Color registers. */
206 unsigned cb_color_info
;
207 unsigned cb_color_base
;
208 unsigned cb_color_view
;
209 unsigned cb_color_size
; /* R600 only */
210 unsigned cb_color_dim
; /* EG only */
211 unsigned cb_color_pitch
; /* EG and later */
212 unsigned cb_color_slice
; /* EG and later */
213 unsigned cb_color_attrib
; /* EG and later */
214 unsigned cb_color_fmask
; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
215 unsigned cb_color_fmask_slice
; /* EG and later */
216 unsigned cb_color_cmask
; /* CB_COLORn_TILE (r600 only) */
217 unsigned cb_color_mask
; /* R600 only */
218 struct r600_resource
*cb_buffer_fmask
; /* Used for FMASK relocations. R600 only */
219 struct r600_resource
*cb_buffer_cmask
; /* Used for CMASK relocations. R600 only */
222 unsigned db_depth_info
; /* R600 only, then SI and later */
223 unsigned db_z_info
; /* EG and later */
224 unsigned db_depth_base
; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
225 unsigned db_depth_view
;
226 unsigned db_depth_size
;
227 unsigned db_depth_slice
; /* EG and later */
228 unsigned db_stencil_base
; /* EG and later */
229 unsigned db_stencil_info
; /* EG and later */
230 unsigned db_prefetch_limit
; /* R600 only */
231 unsigned db_htile_surface
;
232 unsigned db_htile_data_base
;
233 unsigned db_preload_control
; /* EG and later */
234 unsigned pa_su_poly_offset_db_fmt_cntl
;
237 struct r600_tiling_info
{
238 unsigned num_channels
;
240 unsigned group_bytes
;
243 struct r600_common_screen
{
244 struct pipe_screen b
;
245 struct radeon_winsys
*ws
;
246 enum radeon_family family
;
247 enum chip_class chip_class
;
248 struct radeon_info info
;
249 struct r600_tiling_info tiling_info
;
250 unsigned debug_flags
;
254 /* Auxiliary context. Mainly used to initialize resources.
255 * It must be locked prior to using and flushed before unlocking. */
256 struct pipe_context
*aux_context
;
257 pipe_mutex aux_context_lock
;
259 struct r600_resource
*trace_bo
;
264 /* This encapsulates a state or an operation which can emitted into the GPU
267 void (*emit
)(struct r600_common_context
*ctx
, struct r600_atom
*state
);
272 struct r600_so_target
{
273 struct pipe_stream_output_target b
;
275 /* The buffer where BUFFER_FILLED_SIZE is stored. */
276 struct r600_resource
*buf_filled_size
;
277 unsigned buf_filled_size_offset
;
279 unsigned stride_in_dw
;
282 struct r600_streamout
{
283 struct r600_atom begin_atom
;
285 unsigned num_dw_for_end
;
287 unsigned enabled_mask
;
288 unsigned num_targets
;
289 struct r600_so_target
*targets
[PIPE_MAX_SO_BUFFERS
];
291 unsigned append_bitmask
;
294 /* External state which comes from the vertex shader,
295 * it must be set explicitly when binding a shader. */
296 unsigned *stride_in_dw
;
298 /* The state of VGT_STRMOUT_(CONFIG|EN). */
299 struct r600_atom enable_atom
;
300 bool streamout_enabled
;
301 bool prims_gen_query_enabled
;
302 int num_prims_gen_queries
;
306 struct radeon_winsys_cs
*cs
;
308 void (*flush
)(void *ctx
, unsigned flags
,
309 struct pipe_fence_handle
**fence
);
313 struct r600_ring gfx
;
314 struct r600_ring dma
;
317 struct r600_common_context
{
318 struct pipe_context b
; /* base class */
320 struct r600_common_screen
*screen
;
321 struct radeon_winsys
*ws
;
322 enum radeon_family family
;
323 enum chip_class chip_class
;
324 struct r600_rings rings
;
325 unsigned initial_gfx_cs_size
;
327 struct u_upload_mgr
*uploader
;
328 struct u_suballocator
*allocator_so_filled_size
;
329 struct util_slab_mempool pool_transfers
;
331 /* Current unaccounted memory usage. */
336 struct r600_streamout streamout
;
338 /* Additional context states. */
339 unsigned flags
; /* flush flags */
342 /* The list of active queries. Only one query of each type can be active. */
343 int num_occlusion_queries
;
344 int num_pipelinestat_queries
;
345 /* Keep track of non-timer queries, because they should be suspended
346 * during context flushing.
347 * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
348 struct list_head active_nontimer_queries
;
349 unsigned num_cs_dw_nontimer_queries_suspend
;
350 /* If queries have been suspended. */
351 bool nontimer_queries_suspended
;
352 /* Additional hardware info. */
353 unsigned backend_mask
;
354 unsigned max_db
; /* for OQ */
356 unsigned num_draw_calls
;
358 /* Render condition. */
359 struct pipe_query
*current_render_cond
;
360 unsigned current_render_cond_mode
;
361 boolean current_render_cond_cond
;
362 boolean predicate_drawing
;
363 /* For context flushing. */
364 struct pipe_query
*saved_render_cond
;
365 boolean saved_render_cond_cond
;
366 unsigned saved_render_cond_mode
;
368 /* MSAA sample locations.
369 * The first index is the sample index.
370 * The second index is the coordinate: X, Y. */
371 float sample_locations_1x
[1][2];
372 float sample_locations_2x
[2][2];
373 float sample_locations_4x
[4][2];
374 float sample_locations_8x
[8][2];
375 float sample_locations_16x
[16][2];
377 /* Copy one resource to another using async DMA. */
378 void (*dma_copy
)(struct pipe_context
*ctx
,
379 struct pipe_resource
*dst
,
381 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
382 struct pipe_resource
*src
,
384 const struct pipe_box
*src_box
);
386 void (*clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
387 unsigned offset
, unsigned size
, unsigned value
);
389 void (*blit_decompress_depth
)(struct pipe_context
*ctx
,
390 struct r600_texture
*texture
,
391 struct r600_texture
*staging
,
392 unsigned first_level
, unsigned last_level
,
393 unsigned first_layer
, unsigned last_layer
,
394 unsigned first_sample
, unsigned last_sample
);
396 /* Reallocate the buffer and update all resource bindings where
397 * the buffer is bound, including all resource descriptors. */
398 void (*invalidate_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
);
400 /* Enable or disable occlusion queries. */
401 void (*set_occlusion_query_state
)(struct pipe_context
*ctx
, bool enable
);
403 /* This ensures there is enough space in the command stream. */
404 void (*need_gfx_cs_space
)(struct pipe_context
*ctx
, unsigned num_dw
,
405 bool include_draw_vbo
);
409 boolean
r600_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
410 struct radeon_winsys_cs_handle
*buf
,
411 enum radeon_bo_usage usage
);
412 void *r600_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
413 struct r600_resource
*resource
,
415 bool r600_init_resource(struct r600_common_screen
*rscreen
,
416 struct r600_resource
*res
,
417 unsigned size
, unsigned alignment
,
418 bool use_reusable_pool
);
419 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
420 const struct pipe_resource
*templ
,
423 /* r600_common_pipe.c */
424 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
425 struct radeon_winsys
*ws
);
426 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
);
427 void r600_preflush_suspend_features(struct r600_common_context
*ctx
);
428 void r600_postflush_resume_features(struct r600_common_context
*ctx
);
429 bool r600_common_context_init(struct r600_common_context
*rctx
,
430 struct r600_common_screen
*rscreen
);
431 void r600_common_context_cleanup(struct r600_common_context
*rctx
);
432 void r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
);
433 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
434 const struct tgsi_token
*tokens
);
435 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
436 unsigned offset
, unsigned size
, unsigned value
);
437 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
438 const struct pipe_resource
*templ
);
439 const char *r600_get_llvm_processor_name(enum radeon_family family
);
440 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
);
443 void r600_query_init(struct r600_common_context
*rctx
);
444 void r600_suspend_nontimer_queries(struct r600_common_context
*ctx
);
445 void r600_resume_nontimer_queries(struct r600_common_context
*ctx
);
446 void r600_query_init_backend_mask(struct r600_common_context
*ctx
);
448 /* r600_streamout.c */
449 void r600_streamout_buffers_dirty(struct r600_common_context
*rctx
);
450 void r600_set_streamout_targets(struct pipe_context
*ctx
,
451 unsigned num_targets
,
452 struct pipe_stream_output_target
**targets
,
453 const unsigned *offset
);
454 void r600_emit_streamout_end(struct r600_common_context
*rctx
);
455 void r600_update_prims_generated_query_state(struct r600_common_context
*rctx
,
456 unsigned type
, int diff
);
457 void r600_streamout_init(struct r600_common_context
*rctx
);
460 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
461 struct r600_texture
*rtex
,
463 struct r600_fmask_info
*out
);
464 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
465 struct r600_texture
*rtex
,
466 struct r600_cmask_info
*out
);
467 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
468 struct pipe_resource
*texture
,
469 struct r600_texture
**staging
);
470 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
471 const struct pipe_resource
*templ
);
472 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
473 struct pipe_resource
*texture
,
474 const struct pipe_surface
*templ
,
475 unsigned width
, unsigned height
);
476 unsigned r600_translate_colorswap(enum pipe_format format
);
477 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
478 struct pipe_framebuffer_state
*fb
,
479 struct r600_atom
*fb_state
,
481 const union pipe_color_union
*color
);
482 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
);
483 void r600_init_context_texture_functions(struct r600_common_context
*rctx
);
486 extern const uint32_t eg_sample_locs_2x
[4];
487 extern const unsigned eg_max_dist_2x
;
488 extern const uint32_t eg_sample_locs_4x
[4];
489 extern const unsigned eg_max_dist_4x
;
490 void cayman_get_sample_position(struct pipe_context
*ctx
, unsigned sample_count
,
491 unsigned sample_index
, float *out_value
);
492 void cayman_init_msaa(struct pipe_context
*ctx
);
493 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
494 void cayman_emit_msaa_config(struct radeon_winsys_cs
*cs
, int nr_samples
,
495 int ps_iter_samples
);
498 /* Inline helpers. */
500 static INLINE
struct r600_resource
*r600_resource(struct pipe_resource
*r
)
502 return (struct r600_resource
*)r
;
506 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
508 pipe_resource_reference((struct pipe_resource
**)ptr
,
509 (struct pipe_resource
*)res
);
512 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
514 if (filter
<= 1) return 0;
515 if (filter
<= 2) return 1;
516 if (filter
<= 4) return 2;
517 if (filter
<= 8) return 3;
521 #define COMPUTE_DBG(rscreen, fmt, args...) \
523 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
526 #define R600_ERR(fmt, args...) \
527 fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
529 /* For MSAA sample positions. */
530 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
531 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
532 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
533 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
534 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))