2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
37 #include "radeon/radeon_winsys.h"
39 #include "util/u_blitter.h"
40 #include "util/list.h"
41 #include "util/u_range.h"
42 #include "util/u_slab.h"
43 #include "util/u_suballoc.h"
44 #include "util/u_transfer.h"
46 #define ATI_VENDOR_ID 0x1002
48 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
49 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
50 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
52 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
53 /* Pipeline & streamout query controls. */
54 #define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
55 #define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
56 #define R600_CONTEXT_PRIVATE_FLAG (1u << 3)
58 /* special primitive types */
59 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
63 #define DBG_TEX (1 << 0)
65 #define DBG_COMPUTE (1 << 2)
66 #define DBG_VM (1 << 3)
69 #define DBG_FS (1 << 5)
70 #define DBG_VS (1 << 6)
71 #define DBG_GS (1 << 7)
72 #define DBG_PS (1 << 8)
73 #define DBG_CS (1 << 9)
74 #define DBG_TCS (1 << 10)
75 #define DBG_TES (1 << 11)
76 #define DBG_NO_IR (1 << 12)
77 #define DBG_NO_TGSI (1 << 13)
78 #define DBG_NO_ASM (1 << 14)
79 #define DBG_PREOPT_IR (1 << 15)
80 /* Bits 21-31 are reserved for the r600g driver. */
82 #define DBG_NO_ASYNC_DMA (1llu << 32)
83 #define DBG_NO_HYPERZ (1llu << 33)
84 #define DBG_NO_DISCARD_RANGE (1llu << 34)
85 #define DBG_NO_2D_TILING (1llu << 35)
86 #define DBG_NO_TILING (1llu << 36)
87 #define DBG_SWITCH_ON_EOP (1llu << 37)
88 #define DBG_FORCE_DMA (1llu << 38)
89 #define DBG_PRECOMPILE (1llu << 39)
90 #define DBG_INFO (1llu << 40)
91 #define DBG_NO_WC (1llu << 41)
92 #define DBG_CHECK_VM (1llu << 42)
93 #define DBG_NO_DCC (1llu << 43)
94 #define DBG_NO_DCC_CLEAR (1llu << 44)
95 #define DBG_NO_RB_PLUS (1llu << 45)
96 #define DBG_SI_SCHED (1llu << 46)
97 #define DBG_MONOLITHIC_SHADERS (1llu << 47)
98 #define DBG_NO_CE (1llu << 48)
100 #define R600_MAP_BUFFER_ALIGNMENT 64
101 #define R600_MAX_VIEWPORTS 16
103 #ifdef PIPE_ARCH_BIG_ENDIAN
104 #define R600_BIG_ENDIAN 1
106 #define R600_BIG_ENDIAN 0
109 struct r600_common_context
;
110 struct r600_perfcounters
;
111 struct tgsi_shader_info
;
113 struct radeon_shader_reloc
{
118 struct radeon_shader_binary
{
123 /** Config/Context register state that accompanies this shader.
124 * This is a stream of dword pairs. First dword contains the
125 * register address, the second dword contains the value.*/
126 unsigned char *config
;
127 unsigned config_size
;
129 /** The number of bytes of config information for each global symbol.
131 unsigned config_size_per_symbol
;
133 /** Constant data accessed by the shader. This will be uploaded
134 * into a constant buffer. */
135 unsigned char *rodata
;
136 unsigned rodata_size
;
138 /** List of symbol offsets for the shader */
139 uint64_t *global_symbol_offsets
;
140 unsigned global_symbol_count
;
142 struct radeon_shader_reloc
*relocs
;
143 unsigned reloc_count
;
145 /** Disassembled shader in a string. */
149 void radeon_shader_binary_init(struct radeon_shader_binary
*b
);
150 void radeon_shader_binary_clean(struct radeon_shader_binary
*b
);
152 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
155 struct r600_resource
{
158 /* Winsys objects. */
159 struct pb_buffer
*buf
;
160 uint64_t gpu_address
;
162 /* Resource state. */
163 enum radeon_bo_domain domains
;
165 /* The buffer range which is initialized (with a write transfer,
166 * streamout, DMA, or as a random access target). The rest of
167 * the buffer is considered invalid and can be mapped unsynchronized.
169 * This allows unsychronized mapping of a buffer range which hasn't
170 * been used yet. It's for applications which forget to use
171 * the unsynchronized map flag and expect the driver to figure it out.
173 struct util_range valid_buffer_range
;
175 /* For buffers only. This indicates that a write operation has been
176 * performed by TC L2, but the cache hasn't been flushed.
177 * Any hw block which doesn't use or bypasses TC L2 should check this
178 * flag and flush the cache before using the buffer.
180 * For example, TC L2 must be flushed if a buffer which has been
181 * modified by a shader store instruction is about to be used as
182 * an index buffer. The reason is that VGT DMA index fetching doesn't
187 /* Whether the resource has been exported via resource_get_handle. */
189 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
192 struct r600_transfer
{
193 struct pipe_transfer transfer
;
194 struct r600_resource
*staging
;
198 struct r600_fmask_info
{
202 unsigned pitch_in_pixels
;
203 unsigned bank_height
;
204 unsigned slice_tile_max
;
205 unsigned tile_mode_index
;
208 struct r600_cmask_info
{
216 unsigned slice_tile_max
;
217 unsigned base_address_reg
;
220 struct r600_htile_info
{
227 struct r600_texture
{
228 struct r600_resource resource
;
232 unsigned dirty_level_mask
; /* each bit says if that mipmap is compressed */
233 unsigned stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
234 struct r600_texture
*flushed_depth_texture
;
235 boolean is_flushing_texture
;
236 struct radeon_surf surface
;
238 /* Colorbuffer compression and fast clear. */
239 struct r600_fmask_info fmask
;
240 struct r600_cmask_info cmask
;
241 struct r600_resource
*cmask_buffer
;
242 uint64_t dcc_offset
; /* 0 = disabled */
243 unsigned cb_color_info
; /* fast clear enable bit */
244 unsigned color_clear_value
[2];
246 /* Depth buffer compression and fast clear. */
247 struct r600_htile_info htile
;
248 struct r600_resource
*htile_buffer
;
249 bool depth_cleared
; /* if it was cleared at least once */
250 float depth_clear_value
;
251 bool stencil_cleared
; /* if it was cleared at least once */
252 uint8_t stencil_clear_value
;
254 bool non_disp_tiling
; /* R600-Cayman only */
257 struct r600_surface
{
258 struct pipe_surface base
;
260 bool color_initialized
;
261 bool depth_initialized
;
263 /* Misc. color flags. */
264 bool alphatest_bypass
;
268 /* Color registers. */
269 unsigned cb_color_info
;
270 unsigned cb_color_base
;
271 unsigned cb_color_view
;
272 unsigned cb_color_size
; /* R600 only */
273 unsigned cb_color_dim
; /* EG only */
274 unsigned cb_color_pitch
; /* EG and later */
275 unsigned cb_color_slice
; /* EG and later */
276 unsigned cb_dcc_base
; /* VI and later */
277 unsigned cb_color_attrib
; /* EG and later */
278 unsigned cb_dcc_control
; /* VI and later */
279 unsigned cb_color_fmask
; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
280 unsigned cb_color_fmask_slice
; /* EG and later */
281 unsigned cb_color_cmask
; /* CB_COLORn_TILE (r600 only) */
282 unsigned cb_color_mask
; /* R600 only */
283 unsigned spi_shader_col_format
; /* SI+, no blending, no alpha-to-coverage. */
284 unsigned spi_shader_col_format_alpha
; /* SI+, alpha-to-coverage */
285 unsigned spi_shader_col_format_blend
; /* SI+, blending without alpha. */
286 unsigned spi_shader_col_format_blend_alpha
; /* SI+, blending with alpha. */
287 struct r600_resource
*cb_buffer_fmask
; /* Used for FMASK relocations. R600 only */
288 struct r600_resource
*cb_buffer_cmask
; /* Used for CMASK relocations. R600 only */
291 unsigned db_depth_info
; /* R600 only, then SI and later */
292 unsigned db_z_info
; /* EG and later */
293 unsigned db_depth_base
; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
294 unsigned db_depth_view
;
295 unsigned db_depth_size
;
296 unsigned db_depth_slice
; /* EG and later */
297 unsigned db_stencil_base
; /* EG and later */
298 unsigned db_stencil_info
; /* EG and later */
299 unsigned db_prefetch_limit
; /* R600 only */
300 unsigned db_htile_surface
;
301 unsigned db_htile_data_base
;
302 unsigned db_preload_control
; /* EG and later */
303 unsigned pa_su_poly_offset_db_fmt_cntl
;
306 struct r600_common_screen
{
307 struct pipe_screen b
;
308 struct radeon_winsys
*ws
;
309 enum radeon_family family
;
310 enum chip_class chip_class
;
311 struct radeon_info info
;
312 uint64_t debug_flags
;
316 /* Texture filter settings. */
317 int force_aniso
; /* -1 = disabled */
319 /* Auxiliary context. Mainly used to initialize resources.
320 * It must be locked prior to using and flushed before unlocking. */
321 struct pipe_context
*aux_context
;
322 pipe_mutex aux_context_lock
;
324 /* This must be in the screen, because UE4 uses one context for
325 * compilation and another one for rendering.
327 unsigned num_compilations
;
328 /* Along with ST_DEBUG=precompile, this should show if applications
329 * are loading shaders on demand. This is a monotonic counter.
331 unsigned num_shaders_created
;
333 /* GPU load thread. */
334 pipe_mutex gpu_load_mutex
;
335 pipe_thread gpu_load_thread
;
336 unsigned gpu_load_counter_busy
;
337 unsigned gpu_load_counter_idle
;
338 volatile unsigned gpu_load_stop_thread
; /* bool */
340 char renderer_string
[64];
342 /* Performance counters. */
343 struct r600_perfcounters
*perfcounters
;
345 /* If pipe_screen wants to re-emit the framebuffer state of all
346 * contexts, it should atomically increment this. Each context will
347 * compare this with its own last known value of the counter before
348 * drawing and re-emit the framebuffer state accordingly.
350 unsigned dirty_fb_counter
;
352 /* Atomically increment this counter when an existing texture's
353 * metadata is enabled or disabled in a way that requires changing
354 * contexts' compressed texture binding masks.
356 unsigned compressed_colortex_counter
;
358 void (*query_opaque_metadata
)(struct r600_common_screen
*rscreen
,
359 struct r600_texture
*rtex
,
360 struct radeon_bo_metadata
*md
);
363 /* This encapsulates a state or an operation which can emitted into the GPU
366 void (*emit
)(struct r600_common_context
*ctx
, struct r600_atom
*state
);
371 struct r600_so_target
{
372 struct pipe_stream_output_target b
;
374 /* The buffer where BUFFER_FILLED_SIZE is stored. */
375 struct r600_resource
*buf_filled_size
;
376 unsigned buf_filled_size_offset
;
377 bool buf_filled_size_valid
;
379 unsigned stride_in_dw
;
382 struct r600_streamout
{
383 struct r600_atom begin_atom
;
385 unsigned num_dw_for_end
;
387 unsigned enabled_mask
;
388 unsigned num_targets
;
389 struct r600_so_target
*targets
[PIPE_MAX_SO_BUFFERS
];
391 unsigned append_bitmask
;
394 /* External state which comes from the vertex shader,
395 * it must be set explicitly when binding a shader. */
396 unsigned *stride_in_dw
;
397 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
399 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
400 unsigned hw_enabled_mask
;
402 /* The state of VGT_STRMOUT_(CONFIG|EN). */
403 struct r600_atom enable_atom
;
404 bool streamout_enabled
;
405 bool prims_gen_query_enabled
;
406 int num_prims_gen_queries
;
409 struct r600_signed_scissor
{
416 struct r600_scissors
{
417 struct r600_atom atom
;
419 struct pipe_scissor_state states
[R600_MAX_VIEWPORTS
];
422 struct r600_viewports
{
423 struct r600_atom atom
;
425 struct pipe_viewport_state states
[R600_MAX_VIEWPORTS
];
426 struct r600_signed_scissor as_scissor
[R600_MAX_VIEWPORTS
];
430 struct radeon_winsys_cs
*cs
;
431 void (*flush
)(void *ctx
, unsigned flags
,
432 struct pipe_fence_handle
**fence
);
435 struct r600_common_context
{
436 struct pipe_context b
; /* base class */
438 struct r600_common_screen
*screen
;
439 struct radeon_winsys
*ws
;
440 struct radeon_winsys_ctx
*ctx
;
441 enum radeon_family family
;
442 enum chip_class chip_class
;
443 struct r600_ring gfx
;
444 struct r600_ring dma
;
445 struct pipe_fence_handle
*last_sdma_fence
;
446 unsigned initial_gfx_cs_size
;
447 unsigned gpu_reset_counter
;
448 unsigned last_dirty_fb_counter
;
449 unsigned last_compressed_colortex_counter
;
451 struct u_upload_mgr
*uploader
;
452 struct u_suballocator
*allocator_so_filled_size
;
453 struct util_slab_mempool pool_transfers
;
455 /* Current unaccounted memory usage. */
460 struct r600_streamout streamout
;
461 struct r600_scissors scissors
;
462 struct r600_viewports viewports
;
463 bool scissor_enabled
;
464 bool vs_writes_viewport_index
;
465 bool vs_disables_clipping_viewport
;
467 /* Additional context states. */
468 unsigned flags
; /* flush flags */
471 /* Maintain the list of active queries for pausing between IBs. */
472 int num_occlusion_queries
;
473 int num_perfect_occlusion_queries
;
474 struct list_head active_queries
;
475 unsigned num_cs_dw_queries_suspend
;
476 /* Additional hardware info. */
477 unsigned backend_mask
;
478 unsigned max_db
; /* for OQ */
480 unsigned num_draw_calls
;
482 /* Render condition. */
483 struct r600_atom render_cond_atom
;
484 struct pipe_query
*render_cond
;
485 unsigned render_cond_mode
;
486 boolean render_cond_invert
;
487 bool render_cond_force_off
; /* for u_blitter */
489 /* MSAA sample locations.
490 * The first index is the sample index.
491 * The second index is the coordinate: X, Y. */
492 float sample_locations_1x
[1][2];
493 float sample_locations_2x
[2][2];
494 float sample_locations_4x
[4][2];
495 float sample_locations_8x
[8][2];
496 float sample_locations_16x
[16][2];
498 /* The list of all texture buffer objects in this context.
499 * This list is walked when a buffer is invalidated/reallocated and
500 * the GPU addresses are updated. */
501 struct list_head texture_buffers
;
503 struct pipe_debug_callback debug
;
505 /* Copy one resource to another using async DMA. */
506 void (*dma_copy
)(struct pipe_context
*ctx
,
507 struct pipe_resource
*dst
,
509 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
510 struct pipe_resource
*src
,
512 const struct pipe_box
*src_box
);
514 void (*clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
515 uint64_t offset
, uint64_t size
, unsigned value
,
516 bool is_framebuffer
);
518 void (*blit_decompress_depth
)(struct pipe_context
*ctx
,
519 struct r600_texture
*texture
,
520 struct r600_texture
*staging
,
521 unsigned first_level
, unsigned last_level
,
522 unsigned first_layer
, unsigned last_layer
,
523 unsigned first_sample
, unsigned last_sample
);
525 void (*decompress_dcc
)(struct pipe_context
*ctx
,
526 struct r600_texture
*rtex
);
528 /* Reallocate the buffer and update all resource bindings where
529 * the buffer is bound, including all resource descriptors. */
530 void (*invalidate_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
);
532 /* Enable or disable occlusion queries. */
533 void (*set_occlusion_query_state
)(struct pipe_context
*ctx
, bool enable
);
535 /* This ensures there is enough space in the command stream. */
536 void (*need_gfx_cs_space
)(struct pipe_context
*ctx
, unsigned num_dw
,
537 bool include_draw_vbo
);
539 void (*set_atom_dirty
)(struct r600_common_context
*ctx
,
540 struct r600_atom
*atom
, bool dirty
);
544 boolean
r600_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
545 struct pb_buffer
*buf
,
546 enum radeon_bo_usage usage
);
547 void *r600_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
548 struct r600_resource
*resource
,
550 bool r600_init_resource(struct r600_common_screen
*rscreen
,
551 struct r600_resource
*res
,
552 uint64_t size
, unsigned alignment
,
553 bool use_reusable_pool
);
554 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
555 const struct pipe_resource
*templ
,
557 struct pipe_resource
* r600_aligned_buffer_create(struct pipe_screen
*screen
,
562 struct pipe_resource
*
563 r600_buffer_from_user_memory(struct pipe_screen
*screen
,
564 const struct pipe_resource
*templ
,
567 r600_invalidate_resource(struct pipe_context
*ctx
,
568 struct pipe_resource
*resource
);
570 /* r600_common_pipe.c */
571 void r600_draw_rectangle(struct blitter_context
*blitter
,
572 int x1
, int y1
, int x2
, int y2
, float depth
,
573 enum blitter_attrib_type type
,
574 const union pipe_color_union
*attrib
);
575 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
576 struct radeon_winsys
*ws
);
577 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
);
578 void r600_preflush_suspend_features(struct r600_common_context
*ctx
);
579 void r600_postflush_resume_features(struct r600_common_context
*ctx
);
580 bool r600_common_context_init(struct r600_common_context
*rctx
,
581 struct r600_common_screen
*rscreen
);
582 void r600_common_context_cleanup(struct r600_common_context
*rctx
);
583 void r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
);
584 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
586 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
587 uint64_t offset
, uint64_t size
, unsigned value
,
588 bool is_framebuffer
);
589 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
590 const struct pipe_resource
*templ
);
591 const char *r600_get_llvm_processor_name(enum radeon_family family
);
592 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
);
594 /* r600_gpu_load.c */
595 void r600_gpu_load_kill_thread(struct r600_common_screen
*rscreen
);
596 uint64_t r600_gpu_load_begin(struct r600_common_screen
*rscreen
);
597 unsigned r600_gpu_load_end(struct r600_common_screen
*rscreen
, uint64_t begin
);
599 /* r600_perfcounters.c */
600 void r600_perfcounters_destroy(struct r600_common_screen
*rscreen
);
603 void r600_init_screen_query_functions(struct r600_common_screen
*rscreen
);
604 void r600_query_init(struct r600_common_context
*rctx
);
605 void r600_suspend_queries(struct r600_common_context
*ctx
);
606 void r600_resume_queries(struct r600_common_context
*ctx
);
607 void r600_query_init_backend_mask(struct r600_common_context
*ctx
);
609 /* r600_streamout.c */
610 void r600_streamout_buffers_dirty(struct r600_common_context
*rctx
);
611 void r600_set_streamout_targets(struct pipe_context
*ctx
,
612 unsigned num_targets
,
613 struct pipe_stream_output_target
**targets
,
614 const unsigned *offset
);
615 void r600_emit_streamout_end(struct r600_common_context
*rctx
);
616 void r600_update_prims_generated_query_state(struct r600_common_context
*rctx
,
617 unsigned type
, int diff
);
618 void r600_streamout_init(struct r600_common_context
*rctx
);
621 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
622 struct r600_texture
*rtex
,
624 struct r600_fmask_info
*out
);
625 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
626 struct r600_texture
*rtex
,
627 struct r600_cmask_info
*out
);
628 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
629 struct pipe_resource
*texture
,
630 struct r600_texture
**staging
);
631 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
);
632 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
633 const struct pipe_resource
*templ
);
634 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
635 struct pipe_resource
*texture
,
636 const struct pipe_surface
*templ
,
637 unsigned width
, unsigned height
);
638 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
639 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
640 struct pipe_framebuffer_state
*fb
,
641 struct r600_atom
*fb_state
,
642 unsigned *buffers
, unsigned *dirty_cbufs
,
643 const union pipe_color_union
*color
);
644 void r600_texture_disable_dcc(struct r600_common_screen
*rscreen
,
645 struct r600_texture
*rtex
);
646 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
);
647 void r600_init_context_texture_functions(struct r600_common_context
*rctx
);
649 /* r600_viewport.c */
650 void evergreen_apply_scissor_bug_workaround(struct r600_common_context
*rctx
,
651 struct pipe_scissor_state
*scissor
);
652 void r600_set_scissor_enable(struct r600_common_context
*rctx
, bool enable
);
653 void r600_update_vs_writes_viewport_index(struct r600_common_context
*rctx
,
654 struct tgsi_shader_info
*info
);
655 void r600_init_viewport_functions(struct r600_common_context
*rctx
);
658 extern const uint32_t eg_sample_locs_2x
[4];
659 extern const unsigned eg_max_dist_2x
;
660 extern const uint32_t eg_sample_locs_4x
[4];
661 extern const unsigned eg_max_dist_4x
;
662 void cayman_get_sample_position(struct pipe_context
*ctx
, unsigned sample_count
,
663 unsigned sample_index
, float *out_value
);
664 void cayman_init_msaa(struct pipe_context
*ctx
);
665 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
666 void cayman_emit_msaa_config(struct radeon_winsys_cs
*cs
, int nr_samples
,
667 int ps_iter_samples
, int overrast_samples
);
670 /* Inline helpers. */
672 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
674 return (struct r600_resource
*)r
;
678 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
680 pipe_resource_reference((struct pipe_resource
**)ptr
,
681 (struct pipe_resource
*)res
);
684 static inline bool r600_get_strmout_en(struct r600_common_context
*rctx
)
686 return rctx
->streamout
.streamout_enabled
||
687 rctx
->streamout
.prims_gen_query_enabled
;
690 #define SQ_TEX_XY_FILTER_POINT 0x00
691 #define SQ_TEX_XY_FILTER_BILINEAR 0x01
692 #define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
693 #define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03
695 static inline unsigned eg_tex_filter(unsigned filter
, unsigned max_aniso
)
697 if (filter
== PIPE_TEX_FILTER_LINEAR
)
698 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
699 : SQ_TEX_XY_FILTER_BILINEAR
;
701 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
702 : SQ_TEX_XY_FILTER_POINT
;
705 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
718 static inline unsigned r600_wavefront_size(enum radeon_family family
)
738 static inline enum radeon_bo_priority
739 r600_get_sampler_view_priority(struct r600_resource
*res
)
741 if (res
->b
.b
.target
== PIPE_BUFFER
)
742 return RADEON_PRIO_SAMPLER_BUFFER
;
744 if (res
->b
.b
.nr_samples
> 1)
745 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
747 return RADEON_PRIO_SAMPLER_TEXTURE
;
750 #define COMPUTE_DBG(rscreen, fmt, args...) \
752 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
755 #define R600_ERR(fmt, args...) \
756 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
758 /* For MSAA sample positions. */
759 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
760 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
761 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
762 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
763 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))