src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/u_slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  47 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  48 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  49
  50 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  51 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 1)
  52
  53 /* special primitive types */
  54 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  55
  56 /* Debug flags. */
  57 /* logging */
  58 #define DBG_TEX                 (1 << 0)
  59 /* gap - reuse */
  60 #define DBG_COMPUTE             (1 << 2)
  61 #define DBG_VM                  (1 << 3)
  62 #define DBG_TRACE_CS            (1 << 4)
  63 /* shader logging */
  64 #define DBG_FS                  (1 << 5)
  65 #define DBG_VS                  (1 << 6)
  66 #define DBG_GS                  (1 << 7)
  67 #define DBG_PS                  (1 << 8)
  68 #define DBG_CS                  (1 << 9)
  69 #define DBG_TCS                 (1 << 10)
  70 #define DBG_TES                 (1 << 11)
  71 #define DBG_NO_IR               (1 << 12)
  72 #define DBG_NO_TGSI             (1 << 13)
  73 #define DBG_NO_ASM              (1 << 14)
  74 #define DBG_PREOPT_IR           (1 << 15)
  75 /* Bits 21-31 are reserved for the r600g driver. */
  76 /* features */
  77 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  78 #define DBG_NO_HYPERZ           (1llu << 33)
  79 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  80 #define DBG_NO_2D_TILING        (1llu << 35)
  81 #define DBG_NO_TILING           (1llu << 36)
  82 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  83 #define DBG_FORCE_DMA           (1llu << 38)
  84 #define DBG_PRECOMPILE          (1llu << 39)
  85 #define DBG_INFO                (1llu << 40)
  86 #define DBG_NO_WC               (1llu << 41)
  87 #define DBG_CHECK_VM            (1llu << 42)
  88 #define DBG_NO_DCC              (1llu << 43)
  89 #define DBG_NO_DCC_CLEAR        (1llu << 44)
  90 #define DBG_NO_RB_PLUS          (1llu << 45)
  91 #define DBG_SI_SCHED            (1llu << 46)
  92
  93 #define R600_MAP_BUFFER_ALIGNMENT 64
  94
  95 struct r600_common_context;
  96 struct r600_perfcounters;
  97
  98 struct radeon_shader_reloc {
  99         char *name;
 100         uint64_t offset;
 101 };
 102
 103 struct radeon_shader_binary {
 104         /** Shader code */
 105         unsigned char *code;
 106         unsigned code_size;
 107
 108         /** Config/Context register state that accompanies this shader.
 109          * This is a stream of dword pairs.  First dword contains the
 110          * register address, the second dword contains the value.*/
 111         unsigned char *config;
 112         unsigned config_size;
 113
 114         /** The number of bytes of config information for each global symbol.
 115          */
 116         unsigned config_size_per_symbol;
 117
 118         /** Constant data accessed by the shader.  This will be uploaded
 119          * into a constant buffer. */
 120         unsigned char *rodata;
 121         unsigned rodata_size;
 122
 123         /** List of symbol offsets for the shader */
 124         uint64_t *global_symbol_offsets;
 125         unsigned global_symbol_count;
 126
 127         struct radeon_shader_reloc *relocs;
 128         unsigned reloc_count;
 129
 130         /** Disassembled shader in a string. */
 131         char *disasm_string;
 132 };
 133
 134 void radeon_shader_binary_init(struct radeon_shader_binary *b);
 135 void radeon_shader_binary_clean(struct radeon_shader_binary *b);
 136
 137 struct r600_resource {
 138         struct u_resource               b;
 139
 140         /* Winsys objects. */
 141         struct pb_buffer                *buf;
 142         uint64_t                        gpu_address;
 143
 144         /* Resource state. */
 145         enum radeon_bo_domain           domains;
 146
 147         /* The buffer range which is initialized (with a write transfer,
 148          * streamout, DMA, or as a random access target). The rest of
 149          * the buffer is considered invalid and can be mapped unsynchronized.
 150          *
 151          * This allows unsychronized mapping of a buffer range which hasn't
 152          * been used yet. It's for applications which forget to use
 153          * the unsynchronized map flag and expect the driver to figure it out.
 154          */
 155         struct util_range               valid_buffer_range;
 156
 157         /* For buffers only. This indicates that a write operation has been
 158          * performed by TC L2, but the cache hasn't been flushed.
 159          * Any hw block which doesn't use or bypasses TC L2 should check this
 160          * flag and flush the cache before using the buffer.
 161          *
 162          * For example, TC L2 must be flushed if a buffer which has been
 163          * modified by a shader store instruction is about to be used as
 164          * an index buffer. The reason is that VGT DMA index fetching doesn't
 165          * use TC L2.
 166          */
 167         bool                            TC_L2_dirty;
 168 };
 169
 170 struct r600_transfer {
 171         struct pipe_transfer            transfer;
 172         struct r600_resource            *staging;
 173         unsigned                        offset;
 174 };
 175
 176 struct r600_fmask_info {
 177         unsigned offset;
 178         unsigned size;
 179         unsigned alignment;
 180         unsigned pitch_in_pixels;
 181         unsigned bank_height;
 182         unsigned slice_tile_max;
 183         unsigned tile_mode_index;
 184 };
 185
 186 struct r600_cmask_info {
 187         unsigned offset;
 188         unsigned size;
 189         unsigned alignment;
 190         unsigned pitch;
 191         unsigned height;
 192         unsigned xalign;
 193         unsigned yalign;
 194         unsigned slice_tile_max;
 195         unsigned base_address_reg;
 196 };
 197
 198 struct r600_htile_info {
 199         unsigned pitch;
 200         unsigned height;
 201         unsigned xalign;
 202         unsigned yalign;
 203 };
 204
 205 struct r600_texture {
 206         struct r600_resource            resource;
 207
 208         unsigned                        size;
 209         bool                            is_depth;
 210         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 211         unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 212         struct r600_texture             *flushed_depth_texture;
 213         boolean                         is_flushing_texture;
 214         struct radeon_surf              surface;
 215
 216         /* Colorbuffer compression and fast clear. */
 217         struct r600_fmask_info          fmask;
 218         struct r600_cmask_info          cmask;
 219         struct r600_resource            *cmask_buffer;
 220         struct r600_resource            *dcc_buffer;
 221         unsigned                        cb_color_info; /* fast clear enable bit */
 222         unsigned                        color_clear_value[2];
 223
 224         /* Depth buffer compression and fast clear. */
 225         struct r600_htile_info          htile;
 226         struct r600_resource            *htile_buffer;
 227         bool                            depth_cleared; /* if it was cleared at least once */
 228         float                           depth_clear_value;
 229         bool                            stencil_cleared; /* if it was cleared at least once */
 230         uint8_t                         stencil_clear_value;
 231
 232         bool                            non_disp_tiling; /* R600-Cayman only */
 233 };
 234
 235 struct r600_surface {
 236         struct pipe_surface             base;
 237
 238         bool color_initialized;
 239         bool depth_initialized;
 240
 241         /* Misc. color flags. */
 242         bool alphatest_bypass;
 243         bool export_16bpc;
 244         bool color_is_int8;
 245
 246         /* Color registers. */
 247         unsigned cb_color_info;
 248         unsigned cb_color_base;
 249         unsigned cb_color_view;
 250         unsigned cb_color_size;         /* R600 only */
 251         unsigned cb_color_dim;          /* EG only */
 252         unsigned cb_color_pitch;        /* EG and later */
 253         unsigned cb_color_slice;        /* EG and later */
 254         unsigned cb_dcc_base;           /* VI and later */
 255         unsigned cb_color_attrib;       /* EG and later */
 256         unsigned cb_dcc_control;        /* VI and later */
 257         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 258         unsigned cb_color_fmask_slice;  /* EG and later */
 259         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 260         unsigned cb_color_mask;         /* R600 only */
 261         unsigned spi_shader_col_format;         /* SI+, no blending, no alpha-to-coverage. */
 262         unsigned spi_shader_col_format_alpha;   /* SI+, alpha-to-coverage */
 263         unsigned spi_shader_col_format_blend;   /* SI+, blending without alpha. */
 264         unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
 265         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 266         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 267
 268         /* DB registers. */
 269         unsigned db_depth_info;         /* R600 only, then SI and later */
 270         unsigned db_z_info;             /* EG and later */
 271         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 272         unsigned db_depth_view;
 273         unsigned db_depth_size;
 274         unsigned db_depth_slice;        /* EG and later */
 275         unsigned db_stencil_base;       /* EG and later */
 276         unsigned db_stencil_info;       /* EG and later */
 277         unsigned db_prefetch_limit;     /* R600 only */
 278         unsigned db_htile_surface;
 279         unsigned db_htile_data_base;
 280         unsigned db_preload_control;    /* EG and later */
 281         unsigned pa_su_poly_offset_db_fmt_cntl;
 282 };
 283
 284 struct r600_tiling_info {
 285         unsigned group_bytes;
 286 };
 287
 288 struct r600_common_screen {
 289         struct pipe_screen              b;
 290         struct radeon_winsys            *ws;
 291         enum radeon_family              family;
 292         enum chip_class                 chip_class;
 293         struct radeon_info              info;
 294         struct r600_tiling_info         tiling_info;
 295         uint64_t                        debug_flags;
 296         bool                            has_cp_dma;
 297         bool                            has_streamout;
 298
 299         /* Auxiliary context. Mainly used to initialize resources.
 300          * It must be locked prior to using and flushed before unlocking. */
 301         struct pipe_context             *aux_context;
 302         pipe_mutex                      aux_context_lock;
 303
 304         struct r600_resource            *trace_bo;
 305         uint32_t                        *trace_ptr;
 306         unsigned                        cs_count;
 307
 308         /* This must be in the screen, because UE4 uses one context for
 309          * compilation and another one for rendering.
 310          */
 311         unsigned                        num_compilations;
 312         /* Along with ST_DEBUG=precompile, this should show if applications
 313          * are loading shaders on demand. This is a monotonic counter.
 314          */
 315         unsigned                        num_shaders_created;
 316
 317         /* GPU load thread. */
 318         pipe_mutex                      gpu_load_mutex;
 319         pipe_thread                     gpu_load_thread;
 320         unsigned                        gpu_load_counter_busy;
 321         unsigned                        gpu_load_counter_idle;
 322         volatile unsigned               gpu_load_stop_thread; /* bool */
 323
 324         char                            renderer_string[64];
 325
 326         /* Performance counters. */
 327         struct r600_perfcounters        *perfcounters;
 328 };
 329
 330 /* This encapsulates a state or an operation which can emitted into the GPU
 331  * command stream. */
 332 struct r600_atom {
 333         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 334         unsigned                num_dw;
 335         unsigned short          id;
 336 };
 337
 338 struct r600_so_target {
 339         struct pipe_stream_output_target b;
 340
 341         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 342         struct r600_resource    *buf_filled_size;
 343         unsigned                buf_filled_size_offset;
 344         bool                    buf_filled_size_valid;
 345
 346         unsigned                stride_in_dw;
 347 };
 348
 349 struct r600_streamout {
 350         struct r600_atom                begin_atom;
 351         bool                            begin_emitted;
 352         unsigned                        num_dw_for_end;
 353
 354         unsigned                        enabled_mask;
 355         unsigned                        num_targets;
 356         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 357
 358         unsigned                        append_bitmask;
 359         bool                            suspended;
 360
 361         /* External state which comes from the vertex shader,
 362          * it must be set explicitly when binding a shader. */
 363         unsigned                        *stride_in_dw;
 364         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 365
 366         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 367         unsigned                        hw_enabled_mask;
 368
 369         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 370         struct r600_atom                enable_atom;
 371         bool                            streamout_enabled;
 372         bool                            prims_gen_query_enabled;
 373         int                             num_prims_gen_queries;
 374 };
 375
 376 struct r600_ring {
 377         struct radeon_winsys_cs         *cs;
 378         void (*flush)(void *ctx, unsigned flags,
 379                       struct pipe_fence_handle **fence);
 380 };
 381
 382 struct r600_common_context {
 383         struct pipe_context b; /* base class */
 384
 385         struct r600_common_screen       *screen;
 386         struct radeon_winsys            *ws;
 387         struct radeon_winsys_ctx        *ctx;
 388         enum radeon_family              family;
 389         enum chip_class                 chip_class;
 390         struct r600_ring                gfx;
 391         struct r600_ring                dma;
 392         struct pipe_fence_handle        *last_sdma_fence;
 393         unsigned                        initial_gfx_cs_size;
 394         unsigned                        gpu_reset_counter;
 395
 396         struct u_upload_mgr             *uploader;
 397         struct u_suballocator           *allocator_so_filled_size;
 398         struct util_slab_mempool        pool_transfers;
 399
 400         /* Current unaccounted memory usage. */
 401         uint64_t                        vram;
 402         uint64_t                        gtt;
 403
 404         /* States. */
 405         struct r600_streamout           streamout;
 406
 407         /* Additional context states. */
 408         unsigned flags; /* flush flags */
 409
 410         /* Queries. */
 411         /* The list of active queries. Only one query of each type can be active. */
 412         int                             num_occlusion_queries;
 413         /* Keep track of non-timer queries, because they should be suspended
 414          * during context flushing.
 415          * The timer queries (TIME_ELAPSED) shouldn't be suspended for blits,
 416          * but they should be suspended between IBs. */
 417         struct list_head                active_nontimer_queries;
 418         struct list_head                active_timer_queries;
 419         unsigned                        num_cs_dw_nontimer_queries_suspend;
 420         bool                            nontimer_queries_suspended_by_flush;
 421         unsigned                        num_cs_dw_timer_queries_suspend;
 422         /* Additional hardware info. */
 423         unsigned                        backend_mask;
 424         unsigned                        max_db; /* for OQ */
 425         /* Misc stats. */
 426         unsigned                        num_draw_calls;
 427
 428         /* Render condition. */
 429         struct r600_atom                render_cond_atom;
 430         struct pipe_query               *render_cond;
 431         unsigned                        render_cond_mode;
 432         boolean                         render_cond_invert;
 433         bool                            render_cond_force_off; /* for u_blitter */
 434
 435         /* MSAA sample locations.
 436          * The first index is the sample index.
 437          * The second index is the coordinate: X, Y. */
 438         float                           sample_locations_1x[1][2];
 439         float                           sample_locations_2x[2][2];
 440         float                           sample_locations_4x[4][2];
 441         float                           sample_locations_8x[8][2];
 442         float                           sample_locations_16x[16][2];
 443
 444         /* The list of all texture buffer objects in this context.
 445          * This list is walked when a buffer is invalidated/reallocated and
 446          * the GPU addresses are updated. */
 447         struct list_head                texture_buffers;
 448
 449         struct pipe_debug_callback      debug;
 450
 451         /* Copy one resource to another using async DMA. */
 452         void (*dma_copy)(struct pipe_context *ctx,
 453                          struct pipe_resource *dst,
 454                          unsigned dst_level,
 455                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 456                          struct pipe_resource *src,
 457                          unsigned src_level,
 458                          const struct pipe_box *src_box);
 459
 460         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 461                              unsigned offset, unsigned size, unsigned value,
 462                              bool is_framebuffer);
 463
 464         void (*blit_decompress_depth)(struct pipe_context *ctx,
 465                                       struct r600_texture *texture,
 466                                       struct r600_texture *staging,
 467                                       unsigned first_level, unsigned last_level,
 468                                       unsigned first_layer, unsigned last_layer,
 469                                       unsigned first_sample, unsigned last_sample);
 470
 471         /* Reallocate the buffer and update all resource bindings where
 472          * the buffer is bound, including all resource descriptors. */
 473         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 474
 475         /* Enable or disable occlusion queries. */
 476         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 477
 478         /* This ensures there is enough space in the command stream. */
 479         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 480                                   bool include_draw_vbo);
 481
 482         void (*set_atom_dirty)(struct r600_common_context *ctx,
 483                                struct r600_atom *atom, bool dirty);
 484 };
 485
 486 /* r600_buffer.c */
 487 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 488                                         struct pb_buffer *buf,
 489                                         enum radeon_bo_usage usage);
 490 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 491                                       struct r600_resource *resource,
 492                                       unsigned usage);
 493 bool r600_init_resource(struct r600_common_screen *rscreen,
 494                         struct r600_resource *res,
 495                         unsigned size, unsigned alignment,
 496                         bool use_reusable_pool);
 497 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 498                                          const struct pipe_resource *templ,
 499                                          unsigned alignment);
 500 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
 501                                                   unsigned bind,
 502                                                   unsigned usage,
 503                                                   unsigned size,
 504                                                   unsigned alignment);
 505 struct pipe_resource *
 506 r600_buffer_from_user_memory(struct pipe_screen *screen,
 507                              const struct pipe_resource *templ,
 508                              void *user_memory);
 509 void
 510 r600_invalidate_resource(struct pipe_context *ctx,
 511                          struct pipe_resource *resource);
 512
 513 /* r600_common_pipe.c */
 514 void r600_draw_rectangle(struct blitter_context *blitter,
 515                          int x1, int y1, int x2, int y2, float depth,
 516                          enum blitter_attrib_type type,
 517                          const union pipe_color_union *attrib);
 518 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 519                              struct radeon_winsys *ws);
 520 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 521 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 522 void r600_postflush_resume_features(struct r600_common_context *ctx);
 523 bool r600_common_context_init(struct r600_common_context *rctx,
 524                               struct r600_common_screen *rscreen);
 525 void r600_common_context_cleanup(struct r600_common_context *rctx);
 526 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 527 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 528                           unsigned processor);
 529 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 530                               unsigned offset, unsigned size, unsigned value,
 531                               bool is_framebuffer);
 532 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 533                                                   const struct pipe_resource *templ);
 534 const char *r600_get_llvm_processor_name(enum radeon_family family);
 535 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw);
 536
 537 /* r600_gpu_load.c */
 538 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 539 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
 540 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 541
 542 /* r600_perfcounters.c */
 543 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
 544
 545 /* r600_query.c */
 546 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
 547 void r600_query_init(struct r600_common_context *rctx);
 548 void r600_suspend_nontimer_queries(struct r600_common_context *ctx);
 549 void r600_resume_nontimer_queries(struct r600_common_context *ctx);
 550 void r600_suspend_timer_queries(struct r600_common_context *ctx);
 551 void r600_resume_timer_queries(struct r600_common_context *ctx);
 552 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 553
 554 /* r600_streamout.c */
 555 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 556 void r600_set_streamout_targets(struct pipe_context *ctx,
 557                                 unsigned num_targets,
 558                                 struct pipe_stream_output_target **targets,
 559                                 const unsigned *offset);
 560 void r600_emit_streamout_end(struct r600_common_context *rctx);
 561 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 562                                              unsigned type, int diff);
 563 void r600_streamout_init(struct r600_common_context *rctx);
 564
 565 /* r600_texture.c */
 566 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 567                                  struct r600_texture *rtex,
 568                                  unsigned nr_samples,
 569                                  struct r600_fmask_info *out);
 570 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 571                                  struct r600_texture *rtex,
 572                                  struct r600_cmask_info *out);
 573 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 574                                      struct pipe_resource *texture,
 575                                      struct r600_texture **staging);
 576 void r600_print_texture_info(struct r600_texture *rtex, FILE *f);
 577 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 578                                         const struct pipe_resource *templ);
 579 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 580                                                 struct pipe_resource *texture,
 581                                                 const struct pipe_surface *templ,
 582                                                 unsigned width, unsigned height);
 583 unsigned r600_translate_colorswap(enum pipe_format format);
 584 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 585                                    struct pipe_framebuffer_state *fb,
 586                                    struct r600_atom *fb_state,
 587                                    unsigned *buffers, unsigned *dirty_cbufs,
 588                                    const union pipe_color_union *color);
 589 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 590 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 591
 592 /* cayman_msaa.c */
 593 extern const uint32_t eg_sample_locs_2x[4];
 594 extern const unsigned eg_max_dist_2x;
 595 extern const uint32_t eg_sample_locs_4x[4];
 596 extern const unsigned eg_max_dist_4x;
 597 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 598                                 unsigned sample_index, float *out_value);
 599 void cayman_init_msaa(struct pipe_context *ctx);
 600 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 601 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 602                              int ps_iter_samples, int overrast_samples);
 603
 604
 605 /* Inline helpers. */
 606
 607 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 608 {
 609         return (struct r600_resource*)r;
 610 }
 611
 612 static inline void
 613 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 614 {
 615         pipe_resource_reference((struct pipe_resource **)ptr,
 616                                 (struct pipe_resource *)res);
 617 }
 618
 619 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 620 {
 621         if (filter <= 1)   return 0;
 622         if (filter <= 2)   return 1;
 623         if (filter <= 4)   return 2;
 624         if (filter <= 8)   return 3;
 625          /* else */        return 4;
 626 }
 627
 628 static inline unsigned r600_wavefront_size(enum radeon_family family)
 629 {
 630         switch (family) {
 631         case CHIP_RV610:
 632         case CHIP_RS780:
 633         case CHIP_RV620:
 634         case CHIP_RS880:
 635                 return 16;
 636         case CHIP_RV630:
 637         case CHIP_RV635:
 638         case CHIP_RV730:
 639         case CHIP_RV710:
 640         case CHIP_PALM:
 641         case CHIP_CEDAR:
 642                 return 32;
 643         default:
 644                 return 64;
 645         }
 646 }
 647
 648 static inline enum radeon_bo_priority
 649 r600_get_sampler_view_priority(struct r600_resource *res)
 650 {
 651         if (res->b.b.target == PIPE_BUFFER)
 652                 return RADEON_PRIO_SAMPLER_BUFFER;
 653
 654         if (res->b.b.nr_samples > 1)
 655                 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
 656
 657         return RADEON_PRIO_SAMPLER_TEXTURE;
 658 }
 659
 660 #define COMPUTE_DBG(rscreen, fmt, args...) \
 661         do { \
 662                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 663         } while (0);
 664
 665 #define R600_ERR(fmt, args...) \
 666         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
 667
 668 /* For MSAA sample positions. */
 669 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 670         (((s0x) & 0xf) | (((s0y) & 0xf) << 4) |            \
 671         (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |     \
 672         (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |    \
 673          (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
 674
 675 #endif