2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
37 #include "radeon/radeon_winsys.h"
39 #include "util/u_blitter.h"
40 #include "util/list.h"
41 #include "util/u_range.h"
42 #include "util/u_slab.h"
43 #include "util/u_suballoc.h"
44 #include "util/u_transfer.h"
46 #define ATI_VENDOR_ID 0x1002
48 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
49 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
50 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
52 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
53 #define R600_CONTEXT_PRIVATE_FLAG (1u << 1)
55 /* special primitive types */
56 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
60 #define DBG_TEX (1 << 0)
62 #define DBG_COMPUTE (1 << 2)
63 #define DBG_VM (1 << 3)
66 #define DBG_FS (1 << 5)
67 #define DBG_VS (1 << 6)
68 #define DBG_GS (1 << 7)
69 #define DBG_PS (1 << 8)
70 #define DBG_CS (1 << 9)
71 #define DBG_TCS (1 << 10)
72 #define DBG_TES (1 << 11)
73 #define DBG_NO_IR (1 << 12)
74 #define DBG_NO_TGSI (1 << 13)
75 #define DBG_NO_ASM (1 << 14)
76 #define DBG_PREOPT_IR (1 << 15)
77 /* Bits 21-31 are reserved for the r600g driver. */
79 #define DBG_NO_ASYNC_DMA (1llu << 32)
80 #define DBG_NO_HYPERZ (1llu << 33)
81 #define DBG_NO_DISCARD_RANGE (1llu << 34)
82 #define DBG_NO_2D_TILING (1llu << 35)
83 #define DBG_NO_TILING (1llu << 36)
84 #define DBG_SWITCH_ON_EOP (1llu << 37)
85 #define DBG_FORCE_DMA (1llu << 38)
86 #define DBG_PRECOMPILE (1llu << 39)
87 #define DBG_INFO (1llu << 40)
88 #define DBG_NO_WC (1llu << 41)
89 #define DBG_CHECK_VM (1llu << 42)
90 #define DBG_NO_DCC (1llu << 43)
91 #define DBG_NO_DCC_CLEAR (1llu << 44)
92 #define DBG_NO_RB_PLUS (1llu << 45)
93 #define DBG_SI_SCHED (1llu << 46)
94 #define DBG_MONOLITHIC_SHADERS (1llu << 47)
96 #define R600_MAP_BUFFER_ALIGNMENT 64
98 struct r600_common_context
;
99 struct r600_perfcounters
;
101 struct radeon_shader_reloc
{
106 struct radeon_shader_binary
{
111 /** Config/Context register state that accompanies this shader.
112 * This is a stream of dword pairs. First dword contains the
113 * register address, the second dword contains the value.*/
114 unsigned char *config
;
115 unsigned config_size
;
117 /** The number of bytes of config information for each global symbol.
119 unsigned config_size_per_symbol
;
121 /** Constant data accessed by the shader. This will be uploaded
122 * into a constant buffer. */
123 unsigned char *rodata
;
124 unsigned rodata_size
;
126 /** List of symbol offsets for the shader */
127 uint64_t *global_symbol_offsets
;
128 unsigned global_symbol_count
;
130 struct radeon_shader_reloc
*relocs
;
131 unsigned reloc_count
;
133 /** Disassembled shader in a string. */
137 void radeon_shader_binary_init(struct radeon_shader_binary
*b
);
138 void radeon_shader_binary_clean(struct radeon_shader_binary
*b
);
140 struct r600_resource
{
143 /* Winsys objects. */
144 struct pb_buffer
*buf
;
145 uint64_t gpu_address
;
147 /* Resource state. */
148 enum radeon_bo_domain domains
;
150 /* The buffer range which is initialized (with a write transfer,
151 * streamout, DMA, or as a random access target). The rest of
152 * the buffer is considered invalid and can be mapped unsynchronized.
154 * This allows unsychronized mapping of a buffer range which hasn't
155 * been used yet. It's for applications which forget to use
156 * the unsynchronized map flag and expect the driver to figure it out.
158 struct util_range valid_buffer_range
;
160 /* For buffers only. This indicates that a write operation has been
161 * performed by TC L2, but the cache hasn't been flushed.
162 * Any hw block which doesn't use or bypasses TC L2 should check this
163 * flag and flush the cache before using the buffer.
165 * For example, TC L2 must be flushed if a buffer which has been
166 * modified by a shader store instruction is about to be used as
167 * an index buffer. The reason is that VGT DMA index fetching doesn't
172 /* Whether the resource has been exported via resource_get_handle. */
174 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
177 struct r600_transfer
{
178 struct pipe_transfer transfer
;
179 struct r600_resource
*staging
;
183 struct r600_fmask_info
{
187 unsigned pitch_in_pixels
;
188 unsigned bank_height
;
189 unsigned slice_tile_max
;
190 unsigned tile_mode_index
;
193 struct r600_cmask_info
{
201 unsigned slice_tile_max
;
202 unsigned base_address_reg
;
205 struct r600_htile_info
{
212 struct r600_texture
{
213 struct r600_resource resource
;
217 unsigned dirty_level_mask
; /* each bit says if that mipmap is compressed */
218 unsigned stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
219 struct r600_texture
*flushed_depth_texture
;
220 boolean is_flushing_texture
;
221 struct radeon_surf surface
;
223 /* Colorbuffer compression and fast clear. */
224 struct r600_fmask_info fmask
;
225 struct r600_cmask_info cmask
;
226 struct r600_resource
*cmask_buffer
;
227 unsigned dcc_offset
; /* 0 = disabled */
228 unsigned cb_color_info
; /* fast clear enable bit */
229 unsigned color_clear_value
[2];
231 /* Depth buffer compression and fast clear. */
232 struct r600_htile_info htile
;
233 struct r600_resource
*htile_buffer
;
234 bool depth_cleared
; /* if it was cleared at least once */
235 float depth_clear_value
;
236 bool stencil_cleared
; /* if it was cleared at least once */
237 uint8_t stencil_clear_value
;
239 bool non_disp_tiling
; /* R600-Cayman only */
242 struct r600_surface
{
243 struct pipe_surface base
;
245 bool color_initialized
;
246 bool depth_initialized
;
248 /* Misc. color flags. */
249 bool alphatest_bypass
;
253 /* Color registers. */
254 unsigned cb_color_info
;
255 unsigned cb_color_base
;
256 unsigned cb_color_view
;
257 unsigned cb_color_size
; /* R600 only */
258 unsigned cb_color_dim
; /* EG only */
259 unsigned cb_color_pitch
; /* EG and later */
260 unsigned cb_color_slice
; /* EG and later */
261 unsigned cb_dcc_base
; /* VI and later */
262 unsigned cb_color_attrib
; /* EG and later */
263 unsigned cb_dcc_control
; /* VI and later */
264 unsigned cb_color_fmask
; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
265 unsigned cb_color_fmask_slice
; /* EG and later */
266 unsigned cb_color_cmask
; /* CB_COLORn_TILE (r600 only) */
267 unsigned cb_color_mask
; /* R600 only */
268 unsigned spi_shader_col_format
; /* SI+, no blending, no alpha-to-coverage. */
269 unsigned spi_shader_col_format_alpha
; /* SI+, alpha-to-coverage */
270 unsigned spi_shader_col_format_blend
; /* SI+, blending without alpha. */
271 unsigned spi_shader_col_format_blend_alpha
; /* SI+, blending with alpha. */
272 struct r600_resource
*cb_buffer_fmask
; /* Used for FMASK relocations. R600 only */
273 struct r600_resource
*cb_buffer_cmask
; /* Used for CMASK relocations. R600 only */
276 unsigned db_depth_info
; /* R600 only, then SI and later */
277 unsigned db_z_info
; /* EG and later */
278 unsigned db_depth_base
; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
279 unsigned db_depth_view
;
280 unsigned db_depth_size
;
281 unsigned db_depth_slice
; /* EG and later */
282 unsigned db_stencil_base
; /* EG and later */
283 unsigned db_stencil_info
; /* EG and later */
284 unsigned db_prefetch_limit
; /* R600 only */
285 unsigned db_htile_surface
;
286 unsigned db_htile_data_base
;
287 unsigned db_preload_control
; /* EG and later */
288 unsigned pa_su_poly_offset_db_fmt_cntl
;
291 struct r600_common_screen
{
292 struct pipe_screen b
;
293 struct radeon_winsys
*ws
;
294 enum radeon_family family
;
295 enum chip_class chip_class
;
296 struct radeon_info info
;
297 uint64_t debug_flags
;
301 /* Auxiliary context. Mainly used to initialize resources.
302 * It must be locked prior to using and flushed before unlocking. */
303 struct pipe_context
*aux_context
;
304 pipe_mutex aux_context_lock
;
306 /* This must be in the screen, because UE4 uses one context for
307 * compilation and another one for rendering.
309 unsigned num_compilations
;
310 /* Along with ST_DEBUG=precompile, this should show if applications
311 * are loading shaders on demand. This is a monotonic counter.
313 unsigned num_shaders_created
;
315 /* GPU load thread. */
316 pipe_mutex gpu_load_mutex
;
317 pipe_thread gpu_load_thread
;
318 unsigned gpu_load_counter_busy
;
319 unsigned gpu_load_counter_idle
;
320 volatile unsigned gpu_load_stop_thread
; /* bool */
322 char renderer_string
[64];
324 /* Performance counters. */
325 struct r600_perfcounters
*perfcounters
;
327 /* If pipe_screen wants to re-emit the framebuffer state of all
328 * contexts, it should atomically increment this. Each context will
329 * compare this with its own last known value of the counter before
330 * drawing and re-emit the framebuffer state accordingly.
332 unsigned dirty_fb_counter
;
334 /* Atomically increment this counter when an existing texture's
335 * metadata is enabled or disabled in a way that requires changing
336 * contexts' compressed texture binding masks.
338 unsigned compressed_colortex_counter
;
340 void (*query_opaque_metadata
)(struct r600_common_screen
*rscreen
,
341 struct r600_texture
*rtex
,
342 struct radeon_bo_metadata
*md
);
345 /* This encapsulates a state or an operation which can emitted into the GPU
348 void (*emit
)(struct r600_common_context
*ctx
, struct r600_atom
*state
);
353 struct r600_so_target
{
354 struct pipe_stream_output_target b
;
356 /* The buffer where BUFFER_FILLED_SIZE is stored. */
357 struct r600_resource
*buf_filled_size
;
358 unsigned buf_filled_size_offset
;
359 bool buf_filled_size_valid
;
361 unsigned stride_in_dw
;
364 struct r600_streamout
{
365 struct r600_atom begin_atom
;
367 unsigned num_dw_for_end
;
369 unsigned enabled_mask
;
370 unsigned num_targets
;
371 struct r600_so_target
*targets
[PIPE_MAX_SO_BUFFERS
];
373 unsigned append_bitmask
;
376 /* External state which comes from the vertex shader,
377 * it must be set explicitly when binding a shader. */
378 unsigned *stride_in_dw
;
379 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
381 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
382 unsigned hw_enabled_mask
;
384 /* The state of VGT_STRMOUT_(CONFIG|EN). */
385 struct r600_atom enable_atom
;
386 bool streamout_enabled
;
387 bool prims_gen_query_enabled
;
388 int num_prims_gen_queries
;
392 struct radeon_winsys_cs
*cs
;
393 void (*flush
)(void *ctx
, unsigned flags
,
394 struct pipe_fence_handle
**fence
);
397 struct r600_common_context
{
398 struct pipe_context b
; /* base class */
400 struct r600_common_screen
*screen
;
401 struct radeon_winsys
*ws
;
402 struct radeon_winsys_ctx
*ctx
;
403 enum radeon_family family
;
404 enum chip_class chip_class
;
405 struct r600_ring gfx
;
406 struct r600_ring dma
;
407 struct pipe_fence_handle
*last_sdma_fence
;
408 unsigned initial_gfx_cs_size
;
409 unsigned gpu_reset_counter
;
410 unsigned last_dirty_fb_counter
;
411 unsigned last_compressed_colortex_counter
;
413 struct u_upload_mgr
*uploader
;
414 struct u_suballocator
*allocator_so_filled_size
;
415 struct util_slab_mempool pool_transfers
;
417 /* Current unaccounted memory usage. */
422 struct r600_streamout streamout
;
424 /* Additional context states. */
425 unsigned flags
; /* flush flags */
428 /* The list of active queries. Only one query of each type can be active. */
429 int num_occlusion_queries
;
430 /* Keep track of non-timer queries, because they should be suspended
431 * during context flushing.
432 * The timer queries (TIME_ELAPSED) shouldn't be suspended for blits,
433 * but they should be suspended between IBs. */
434 struct list_head active_nontimer_queries
;
435 struct list_head active_timer_queries
;
436 unsigned num_cs_dw_nontimer_queries_suspend
;
437 bool nontimer_queries_suspended_by_flush
;
438 unsigned num_cs_dw_timer_queries_suspend
;
439 /* Additional hardware info. */
440 unsigned backend_mask
;
441 unsigned max_db
; /* for OQ */
443 unsigned num_draw_calls
;
445 /* Render condition. */
446 struct r600_atom render_cond_atom
;
447 struct pipe_query
*render_cond
;
448 unsigned render_cond_mode
;
449 boolean render_cond_invert
;
450 bool render_cond_force_off
; /* for u_blitter */
452 /* MSAA sample locations.
453 * The first index is the sample index.
454 * The second index is the coordinate: X, Y. */
455 float sample_locations_1x
[1][2];
456 float sample_locations_2x
[2][2];
457 float sample_locations_4x
[4][2];
458 float sample_locations_8x
[8][2];
459 float sample_locations_16x
[16][2];
461 /* The list of all texture buffer objects in this context.
462 * This list is walked when a buffer is invalidated/reallocated and
463 * the GPU addresses are updated. */
464 struct list_head texture_buffers
;
466 struct pipe_debug_callback debug
;
468 /* Copy one resource to another using async DMA. */
469 void (*dma_copy
)(struct pipe_context
*ctx
,
470 struct pipe_resource
*dst
,
472 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
473 struct pipe_resource
*src
,
475 const struct pipe_box
*src_box
);
477 void (*clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
478 unsigned offset
, unsigned size
, unsigned value
,
479 bool is_framebuffer
);
481 void (*blit_decompress_depth
)(struct pipe_context
*ctx
,
482 struct r600_texture
*texture
,
483 struct r600_texture
*staging
,
484 unsigned first_level
, unsigned last_level
,
485 unsigned first_layer
, unsigned last_layer
,
486 unsigned first_sample
, unsigned last_sample
);
488 void (*decompress_dcc
)(struct pipe_context
*ctx
,
489 struct r600_texture
*rtex
);
491 /* Reallocate the buffer and update all resource bindings where
492 * the buffer is bound, including all resource descriptors. */
493 void (*invalidate_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
);
495 /* Enable or disable occlusion queries. */
496 void (*set_occlusion_query_state
)(struct pipe_context
*ctx
, bool enable
);
498 /* This ensures there is enough space in the command stream. */
499 void (*need_gfx_cs_space
)(struct pipe_context
*ctx
, unsigned num_dw
,
500 bool include_draw_vbo
);
502 void (*set_atom_dirty
)(struct r600_common_context
*ctx
,
503 struct r600_atom
*atom
, bool dirty
);
507 boolean
r600_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
508 struct pb_buffer
*buf
,
509 enum radeon_bo_usage usage
);
510 void *r600_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
511 struct r600_resource
*resource
,
513 bool r600_init_resource(struct r600_common_screen
*rscreen
,
514 struct r600_resource
*res
,
515 unsigned size
, unsigned alignment
,
516 bool use_reusable_pool
);
517 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
518 const struct pipe_resource
*templ
,
520 struct pipe_resource
* r600_aligned_buffer_create(struct pipe_screen
*screen
,
525 struct pipe_resource
*
526 r600_buffer_from_user_memory(struct pipe_screen
*screen
,
527 const struct pipe_resource
*templ
,
530 r600_invalidate_resource(struct pipe_context
*ctx
,
531 struct pipe_resource
*resource
);
533 /* r600_common_pipe.c */
534 void r600_draw_rectangle(struct blitter_context
*blitter
,
535 int x1
, int y1
, int x2
, int y2
, float depth
,
536 enum blitter_attrib_type type
,
537 const union pipe_color_union
*attrib
);
538 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
539 struct radeon_winsys
*ws
);
540 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
);
541 void r600_preflush_suspend_features(struct r600_common_context
*ctx
);
542 void r600_postflush_resume_features(struct r600_common_context
*ctx
);
543 bool r600_common_context_init(struct r600_common_context
*rctx
,
544 struct r600_common_screen
*rscreen
);
545 void r600_common_context_cleanup(struct r600_common_context
*rctx
);
546 void r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
);
547 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
549 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
550 unsigned offset
, unsigned size
, unsigned value
,
551 bool is_framebuffer
);
552 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
553 const struct pipe_resource
*templ
);
554 const char *r600_get_llvm_processor_name(enum radeon_family family
);
555 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
);
557 /* r600_gpu_load.c */
558 void r600_gpu_load_kill_thread(struct r600_common_screen
*rscreen
);
559 uint64_t r600_gpu_load_begin(struct r600_common_screen
*rscreen
);
560 unsigned r600_gpu_load_end(struct r600_common_screen
*rscreen
, uint64_t begin
);
562 /* r600_perfcounters.c */
563 void r600_perfcounters_destroy(struct r600_common_screen
*rscreen
);
566 void r600_init_screen_query_functions(struct r600_common_screen
*rscreen
);
567 void r600_query_init(struct r600_common_context
*rctx
);
568 void r600_suspend_nontimer_queries(struct r600_common_context
*ctx
);
569 void r600_resume_nontimer_queries(struct r600_common_context
*ctx
);
570 void r600_suspend_timer_queries(struct r600_common_context
*ctx
);
571 void r600_resume_timer_queries(struct r600_common_context
*ctx
);
572 void r600_query_init_backend_mask(struct r600_common_context
*ctx
);
574 /* r600_streamout.c */
575 void r600_streamout_buffers_dirty(struct r600_common_context
*rctx
);
576 void r600_set_streamout_targets(struct pipe_context
*ctx
,
577 unsigned num_targets
,
578 struct pipe_stream_output_target
**targets
,
579 const unsigned *offset
);
580 void r600_emit_streamout_end(struct r600_common_context
*rctx
);
581 void r600_update_prims_generated_query_state(struct r600_common_context
*rctx
,
582 unsigned type
, int diff
);
583 void r600_streamout_init(struct r600_common_context
*rctx
);
586 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
587 struct r600_texture
*rtex
,
589 struct r600_fmask_info
*out
);
590 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
591 struct r600_texture
*rtex
,
592 struct r600_cmask_info
*out
);
593 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
594 struct pipe_resource
*texture
,
595 struct r600_texture
**staging
);
596 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
);
597 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
598 const struct pipe_resource
*templ
);
599 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
600 struct pipe_resource
*texture
,
601 const struct pipe_surface
*templ
,
602 unsigned width
, unsigned height
);
603 unsigned r600_translate_colorswap(enum pipe_format format
);
604 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
605 struct pipe_framebuffer_state
*fb
,
606 struct r600_atom
*fb_state
,
607 unsigned *buffers
, unsigned *dirty_cbufs
,
608 const union pipe_color_union
*color
);
609 void r600_texture_disable_dcc(struct r600_common_screen
*rscreen
,
610 struct r600_texture
*rtex
);
611 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
);
612 void r600_init_context_texture_functions(struct r600_common_context
*rctx
);
615 extern const uint32_t eg_sample_locs_2x
[4];
616 extern const unsigned eg_max_dist_2x
;
617 extern const uint32_t eg_sample_locs_4x
[4];
618 extern const unsigned eg_max_dist_4x
;
619 void cayman_get_sample_position(struct pipe_context
*ctx
, unsigned sample_count
,
620 unsigned sample_index
, float *out_value
);
621 void cayman_init_msaa(struct pipe_context
*ctx
);
622 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
623 void cayman_emit_msaa_config(struct radeon_winsys_cs
*cs
, int nr_samples
,
624 int ps_iter_samples
, int overrast_samples
);
627 /* Inline helpers. */
629 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
631 return (struct r600_resource
*)r
;
635 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
637 pipe_resource_reference((struct pipe_resource
**)ptr
,
638 (struct pipe_resource
*)res
);
641 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
643 if (filter
<= 1) return 0;
644 if (filter
<= 2) return 1;
645 if (filter
<= 4) return 2;
646 if (filter
<= 8) return 3;
650 static inline unsigned r600_wavefront_size(enum radeon_family family
)
670 static inline enum radeon_bo_priority
671 r600_get_sampler_view_priority(struct r600_resource
*res
)
673 if (res
->b
.b
.target
== PIPE_BUFFER
)
674 return RADEON_PRIO_SAMPLER_BUFFER
;
676 if (res
->b
.b
.nr_samples
> 1)
677 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
679 return RADEON_PRIO_SAMPLER_TEXTURE
;
682 #define COMPUTE_DBG(rscreen, fmt, args...) \
684 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
687 #define R600_ERR(fmt, args...) \
688 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
690 /* For MSAA sample positions. */
691 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
692 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
693 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
694 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
695 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))