src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 /**
  25  * This file contains common screen and context structures and functions
  26  * for r600g and radeonsi.
  27  */
  28
  29 #ifndef R600_PIPE_COMMON_H
  30 #define R600_PIPE_COMMON_H
  31
  32 #include <stdio.h>
  33
  34 #include "amd/common/ac_binary.h"
  35
  36 #include "radeon/radeon_winsys.h"
  37
  38 #include "util/disk_cache.h"
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45 #include "util/u_threaded_context.h"
  46
  47 struct u_log_context;
  48
  49 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  50 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  51 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  52 #define R600_RESOURCE_FLAG_DISABLE_DCC          (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
  53 #define R600_RESOURCE_FLAG_UNMAPPABLE           (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
  54
  55 /* Debug flags. */
  56 enum {
  57         /* Shader logging options: */
  58         DBG_VS = PIPE_SHADER_VERTEX,
  59         DBG_PS = PIPE_SHADER_FRAGMENT,
  60         DBG_GS = PIPE_SHADER_GEOMETRY,
  61         DBG_TCS = PIPE_SHADER_TESS_CTRL,
  62         DBG_TES = PIPE_SHADER_TESS_EVAL,
  63         DBG_CS = PIPE_SHADER_COMPUTE,
  64         DBG_NO_IR,
  65         DBG_NO_TGSI,
  66         DBG_NO_ASM,
  67         DBG_PREOPT_IR,
  68
  69         /* Shader compiler options the shader cache should be aware of: */
  70         DBG_FS_CORRECT_DERIVS_AFTER_KILL,
  71         DBG_UNSAFE_MATH,
  72         DBG_SI_SCHED,
  73
  74         /* Shader compiler options (with no effect on the shader cache): */
  75         DBG_CHECK_IR,
  76         DBG_PRECOMPILE,
  77         DBG_NIR,
  78         DBG_MONOLITHIC_SHADERS,
  79         DBG_NO_OPT_VARIANT,
  80
  81         /* Information logging options: */
  82         DBG_INFO,
  83         DBG_TEX,
  84         DBG_COMPUTE,
  85         DBG_VM,
  86
  87         /* Driver options: */
  88         DBG_FORCE_DMA,
  89         DBG_NO_ASYNC_DMA,
  90         DBG_NO_WC,
  91         DBG_CHECK_VM,
  92         DBG_RESERVE_VMID,
  93
  94         /* 3D engine options: */
  95         DBG_SWITCH_ON_EOP,
  96         DBG_NO_OUT_OF_ORDER,
  97         DBG_NO_DPBB,
  98         DBG_NO_DFSM,
  99         DBG_DPBB,
 100         DBG_DFSM,
 101         DBG_NO_HYPERZ,
 102         DBG_NO_RB_PLUS,
 103         DBG_NO_2D_TILING,
 104         DBG_NO_TILING,
 105         DBG_NO_DCC,
 106         DBG_NO_DCC_CLEAR,
 107         DBG_NO_DCC_FB,
 108         DBG_NO_DCC_MSAA,
 109         DBG_DCC_MSAA,
 110
 111         /* Tests: */
 112         DBG_TEST_DMA,
 113         DBG_TEST_VMFAULT_CP,
 114         DBG_TEST_VMFAULT_SDMA,
 115         DBG_TEST_VMFAULT_SHADER,
 116 };
 117
 118 #define DBG_ALL_SHADERS         (((1 << (DBG_CS + 1)) - 1))
 119 #define DBG(name)               (1ull << DBG_##name)
 120
 121 #define R600_MAP_BUFFER_ALIGNMENT 64
 122
 123 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
 124
 125 struct r600_common_context;
 126 struct r600_perfcounters;
 127 struct tgsi_shader_info;
 128 struct r600_qbo_state;
 129
 130 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
 131  * at the moment.
 132  */
 133 struct r600_resource {
 134         struct threaded_resource        b;
 135
 136         /* Winsys objects. */
 137         struct pb_buffer                *buf;
 138         uint64_t                        gpu_address;
 139         /* Memory usage if the buffer placement is optimal. */
 140         uint64_t                        vram_usage;
 141         uint64_t                        gart_usage;
 142
 143         /* Resource properties. */
 144         uint64_t                        bo_size;
 145         unsigned                        bo_alignment;
 146         enum radeon_bo_domain           domains;
 147         enum radeon_bo_flag             flags;
 148         unsigned                        bind_history;
 149         int                             max_forced_staging_uploads;
 150
 151         /* The buffer range which is initialized (with a write transfer,
 152          * streamout, DMA, or as a random access target). The rest of
 153          * the buffer is considered invalid and can be mapped unsynchronized.
 154          *
 155          * This allows unsychronized mapping of a buffer range which hasn't
 156          * been used yet. It's for applications which forget to use
 157          * the unsynchronized map flag and expect the driver to figure it out.
 158          */
 159         struct util_range               valid_buffer_range;
 160
 161         /* For buffers only. This indicates that a write operation has been
 162          * performed by TC L2, but the cache hasn't been flushed.
 163          * Any hw block which doesn't use or bypasses TC L2 should check this
 164          * flag and flush the cache before using the buffer.
 165          *
 166          * For example, TC L2 must be flushed if a buffer which has been
 167          * modified by a shader store instruction is about to be used as
 168          * an index buffer. The reason is that VGT DMA index fetching doesn't
 169          * use TC L2.
 170          */
 171         bool                            TC_L2_dirty;
 172
 173         /* Whether the resource has been exported via resource_get_handle. */
 174         unsigned                        external_usage; /* PIPE_HANDLE_USAGE_* */
 175
 176         /* Whether this resource is referenced by bindless handles. */
 177         bool                            texture_handle_allocated;
 178         bool                            image_handle_allocated;
 179 };
 180
 181 struct r600_transfer {
 182         struct threaded_transfer        b;
 183         struct r600_resource            *staging;
 184         unsigned                        offset;
 185 };
 186
 187 struct r600_fmask_info {
 188         uint64_t offset;
 189         uint64_t size;
 190         unsigned alignment;
 191         unsigned pitch_in_pixels;
 192         unsigned bank_height;
 193         unsigned slice_tile_max;
 194         unsigned tile_mode_index;
 195         unsigned tile_swizzle;
 196 };
 197
 198 struct r600_cmask_info {
 199         uint64_t offset;
 200         uint64_t size;
 201         unsigned alignment;
 202         unsigned slice_tile_max;
 203         uint64_t base_address_reg;
 204 };
 205
 206 struct r600_texture {
 207         struct r600_resource            resource;
 208
 209         struct radeon_surf              surface;
 210         uint64_t                        size;
 211         struct r600_texture             *flushed_depth_texture;
 212
 213         /* Colorbuffer compression and fast clear. */
 214         struct r600_fmask_info          fmask;
 215         struct r600_cmask_info          cmask;
 216         struct r600_resource            *cmask_buffer;
 217         uint64_t                        dcc_offset; /* 0 = disabled */
 218         unsigned                        cb_color_info; /* fast clear enable bit */
 219         unsigned                        color_clear_value[2];
 220         unsigned                        last_msaa_resolve_target_micro_mode;
 221         unsigned                        num_level0_transfers;
 222
 223         /* Depth buffer compression and fast clear. */
 224         uint64_t                        htile_offset;
 225         float                           depth_clear_value;
 226         uint16_t                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 227         uint16_t                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 228         enum pipe_format                db_render_format:16;
 229         uint8_t                         stencil_clear_value;
 230         bool                            tc_compatible_htile:1;
 231         bool                            depth_cleared:1; /* if it was cleared at least once */
 232         bool                            stencil_cleared:1; /* if it was cleared at least once */
 233         bool                            upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
 234         bool                            is_depth:1;
 235         bool                            db_compatible:1;
 236         bool                            can_sample_z:1;
 237         bool                            can_sample_s:1;
 238
 239         /* We need to track DCC dirtiness, because st/dri usually calls
 240          * flush_resource twice per frame (not a bug) and we don't wanna
 241          * decompress DCC twice. Also, the dirty tracking must be done even
 242          * if DCC isn't used, because it's required by the DCC usage analysis
 243          * for a possible future enablement.
 244          */
 245         bool                            separate_dcc_dirty:1;
 246         /* Statistics gathering for the DCC enablement heuristic. */
 247         bool                            dcc_gather_statistics:1;
 248         /* Counter that should be non-zero if the texture is bound to a
 249          * framebuffer.
 250          */
 251         unsigned                        framebuffers_bound;
 252         /* Whether the texture is a displayable back buffer and needs DCC
 253          * decompression, which is expensive. Therefore, it's enabled only
 254          * if statistics suggest that it will pay off and it's allocated
 255          * separately. It can't be bound as a sampler by apps. Limited to
 256          * target == 2D and last_level == 0. If enabled, dcc_offset contains
 257          * the absolute GPUVM address, not the relative one.
 258          */
 259         struct r600_resource            *dcc_separate_buffer;
 260         /* When DCC is temporarily disabled, the separate buffer is here. */
 261         struct r600_resource            *last_dcc_separate_buffer;
 262         /* Estimate of how much this color buffer is written to in units of
 263          * full-screen draws: ps_invocations / (width * height)
 264          * Shader kills, late Z, and blending with trivial discards make it
 265          * inaccurate (we need to count CB updates, not PS invocations).
 266          */
 267         unsigned                        ps_draw_ratio;
 268         /* The number of clears since the last DCC usage analysis. */
 269         unsigned                        num_slow_clears;
 270 };
 271
 272 struct r600_surface {
 273         struct pipe_surface             base;
 274
 275         /* These can vary with block-compressed textures. */
 276         uint16_t width0;
 277         uint16_t height0;
 278
 279         bool color_initialized:1;
 280         bool depth_initialized:1;
 281
 282         /* Misc. color flags. */
 283         bool color_is_int8:1;
 284         bool color_is_int10:1;
 285         bool dcc_incompatible:1;
 286
 287         /* Color registers. */
 288         unsigned cb_color_info;
 289         unsigned cb_color_view;
 290         unsigned cb_color_attrib;
 291         unsigned cb_color_attrib2;      /* GFX9 and later */
 292         unsigned cb_dcc_control;        /* VI and later */
 293         unsigned spi_shader_col_format:8;       /* no blending, no alpha-to-coverage. */
 294         unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
 295         unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
 296         unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
 297
 298         /* DB registers. */
 299         uint64_t db_depth_base;         /* DB_Z_READ/WRITE_BASE */
 300         uint64_t db_stencil_base;
 301         uint64_t db_htile_data_base;
 302         unsigned db_depth_info;
 303         unsigned db_z_info;
 304         unsigned db_z_info2;            /* GFX9+ */
 305         unsigned db_depth_view;
 306         unsigned db_depth_size;
 307         unsigned db_depth_slice;
 308         unsigned db_stencil_info;
 309         unsigned db_stencil_info2;      /* GFX9+ */
 310         unsigned db_htile_surface;
 311 };
 312
 313 struct r600_mmio_counter {
 314         unsigned busy;
 315         unsigned idle;
 316 };
 317
 318 union r600_mmio_counters {
 319         struct {
 320                 /* For global GPU load including SDMA. */
 321                 struct r600_mmio_counter gpu;
 322
 323                 /* GRBM_STATUS */
 324                 struct r600_mmio_counter spi;
 325                 struct r600_mmio_counter gui;
 326                 struct r600_mmio_counter ta;
 327                 struct r600_mmio_counter gds;
 328                 struct r600_mmio_counter vgt;
 329                 struct r600_mmio_counter ia;
 330                 struct r600_mmio_counter sx;
 331                 struct r600_mmio_counter wd;
 332                 struct r600_mmio_counter bci;
 333                 struct r600_mmio_counter sc;
 334                 struct r600_mmio_counter pa;
 335                 struct r600_mmio_counter db;
 336                 struct r600_mmio_counter cp;
 337                 struct r600_mmio_counter cb;
 338
 339                 /* SRBM_STATUS2 */
 340                 struct r600_mmio_counter sdma;
 341
 342                 /* CP_STAT */
 343                 struct r600_mmio_counter pfp;
 344                 struct r600_mmio_counter meq;
 345                 struct r600_mmio_counter me;
 346                 struct r600_mmio_counter surf_sync;
 347                 struct r600_mmio_counter cp_dma;
 348                 struct r600_mmio_counter scratch_ram;
 349         } named;
 350         unsigned array[0];
 351 };
 352
 353 struct r600_memory_object {
 354         struct pipe_memory_object       b;
 355         struct pb_buffer                *buf;
 356         uint32_t                        stride;
 357         uint32_t                        offset;
 358 };
 359
 360 struct r600_common_screen {
 361         struct pipe_screen              b;
 362         struct radeon_winsys            *ws;
 363         enum radeon_family              family;
 364         enum chip_class                 chip_class;
 365         struct radeon_info              info;
 366         uint64_t                        debug_flags;
 367         bool                            has_rbplus;     /* if RB+ registers exist */
 368         bool                            rbplus_allowed; /* if RB+ is allowed */
 369         bool                            dcc_msaa_allowed;
 370
 371         struct disk_cache               *disk_shader_cache;
 372
 373         struct slab_parent_pool         pool_transfers;
 374
 375         /* Texture filter settings. */
 376         int                             force_aniso; /* -1 = disabled */
 377
 378         /* Auxiliary context. Mainly used to initialize resources.
 379          * It must be locked prior to using and flushed before unlocking. */
 380         struct pipe_context             *aux_context;
 381         mtx_t                           aux_context_lock;
 382
 383         /* This must be in the screen, because UE4 uses one context for
 384          * compilation and another one for rendering.
 385          */
 386         unsigned                        num_compilations;
 387         /* Along with ST_DEBUG=precompile, this should show if applications
 388          * are loading shaders on demand. This is a monotonic counter.
 389          */
 390         unsigned                        num_shaders_created;
 391         unsigned                        num_shader_cache_hits;
 392
 393         /* GPU load thread. */
 394         mtx_t                           gpu_load_mutex;
 395         thrd_t                          gpu_load_thread;
 396         union r600_mmio_counters        mmio_counters;
 397         volatile unsigned               gpu_load_stop_thread; /* bool */
 398
 399         char                            renderer_string[100];
 400
 401         /* Performance counters. */
 402         struct r600_perfcounters        *perfcounters;
 403
 404         /* If pipe_screen wants to recompute and re-emit the framebuffer,
 405          * sampler, and image states of all contexts, it should atomically
 406          * increment this.
 407          *
 408          * Each context will compare this with its own last known value of
 409          * the counter before drawing and re-emit the states accordingly.
 410          */
 411         unsigned                        dirty_tex_counter;
 412
 413         /* Atomically increment this counter when an existing texture's
 414          * metadata is enabled or disabled in a way that requires changing
 415          * contexts' compressed texture binding masks.
 416          */
 417         unsigned                        compressed_colortex_counter;
 418
 419         struct {
 420                 /* Context flags to set so that all writes from earlier jobs
 421                  * in the CP are seen by L2 clients.
 422                  */
 423                 unsigned cp_to_L2;
 424
 425                 /* Context flags to set so that all writes from earlier jobs
 426                  * that end in L2 are seen by CP.
 427                  */
 428                 unsigned L2_to_cp;
 429
 430                 /* Context flags to set so that all writes from earlier
 431                  * compute jobs are seen by L2 clients.
 432                  */
 433                 unsigned compute_to_L2;
 434         } barrier_flags;
 435
 436         void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
 437                                       struct r600_texture *rtex,
 438                                       struct radeon_bo_metadata *md);
 439
 440         void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
 441                                     struct r600_texture *rtex,
 442                                     struct radeon_bo_metadata *md);
 443 };
 444
 445 /* This encapsulates a state or an operation which can emitted into the GPU
 446  * command stream. */
 447 struct r600_atom {
 448         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 449         unsigned short          id;
 450 };
 451
 452 struct r600_ring {
 453         struct radeon_winsys_cs         *cs;
 454         void (*flush)(void *ctx, unsigned flags,
 455                       struct pipe_fence_handle **fence);
 456 };
 457
 458 /* Saved CS data for debugging features. */
 459 struct radeon_saved_cs {
 460         uint32_t                        *ib;
 461         unsigned                        num_dw;
 462
 463         struct radeon_bo_list_item      *bo_list;
 464         unsigned                        bo_count;
 465 };
 466
 467 struct r600_common_context {
 468         struct pipe_context b; /* base class */
 469
 470         struct r600_common_screen       *screen;
 471         struct radeon_winsys            *ws;
 472         struct radeon_winsys_ctx        *ctx;
 473         enum radeon_family              family;
 474         enum chip_class                 chip_class;
 475         struct r600_ring                gfx;
 476         struct r600_ring                dma;
 477         struct pipe_fence_handle        *last_gfx_fence;
 478         struct pipe_fence_handle        *last_sdma_fence;
 479         struct r600_resource            *eop_bug_scratch;
 480         unsigned                        num_gfx_cs_flushes;
 481         unsigned                        initial_gfx_cs_size;
 482         unsigned                        gpu_reset_counter;
 483         unsigned                        last_dirty_tex_counter;
 484         unsigned                        last_compressed_colortex_counter;
 485         unsigned                        last_num_draw_calls;
 486
 487         struct threaded_context         *tc;
 488         struct u_suballocator           *allocator_zeroed_memory;
 489         struct slab_child_pool          pool_transfers;
 490         struct slab_child_pool          pool_transfers_unsync; /* for threaded_context */
 491
 492         /* Current unaccounted memory usage. */
 493         uint64_t                        vram;
 494         uint64_t                        gtt;
 495
 496         /* Additional context states. */
 497         unsigned flags; /* flush flags */
 498
 499         /* Queries. */
 500         /* Maintain the list of active queries for pausing between IBs. */
 501         int                             num_occlusion_queries;
 502         int                             num_perfect_occlusion_queries;
 503         struct list_head                active_queries;
 504         unsigned                        num_cs_dw_queries_suspend;
 505         /* Misc stats. */
 506         unsigned                        num_draw_calls;
 507         unsigned                        num_decompress_calls;
 508         unsigned                        num_mrt_draw_calls;
 509         unsigned                        num_prim_restart_calls;
 510         unsigned                        num_spill_draw_calls;
 511         unsigned                        num_compute_calls;
 512         unsigned                        num_spill_compute_calls;
 513         unsigned                        num_dma_calls;
 514         unsigned                        num_cp_dma_calls;
 515         unsigned                        num_vs_flushes;
 516         unsigned                        num_ps_flushes;
 517         unsigned                        num_cs_flushes;
 518         unsigned                        num_cb_cache_flushes;
 519         unsigned                        num_db_cache_flushes;
 520         unsigned                        num_L2_invalidates;
 521         unsigned                        num_L2_writebacks;
 522         unsigned                        num_resident_handles;
 523         uint64_t                        num_alloc_tex_transfer_bytes;
 524         unsigned                        last_tex_ps_draw_ratio; /* for query */
 525
 526         /* Render condition. */
 527         struct r600_atom                render_cond_atom;
 528         struct pipe_query               *render_cond;
 529         unsigned                        render_cond_mode;
 530         bool                            render_cond_invert;
 531         bool                            render_cond_force_off; /* for u_blitter */
 532
 533         /* Statistics gathering for the DCC enablement heuristic. It can't be
 534          * in r600_texture because r600_texture can be shared by multiple
 535          * contexts. This is for back buffers only. We shouldn't get too many
 536          * of those.
 537          *
 538          * X11 DRI3 rotates among a finite set of back buffers. They should
 539          * all fit in this array. If they don't, separate DCC might never be
 540          * enabled by DCC stat gathering.
 541          */
 542         struct {
 543                 struct r600_texture             *tex;
 544                 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
 545                 struct pipe_query               *ps_stats[3];
 546                 /* If all slots are used and another slot is needed,
 547                  * the least recently used slot is evicted based on this. */
 548                 int64_t                         last_use_timestamp;
 549                 bool                            query_active;
 550         } dcc_stats[5];
 551
 552         struct pipe_device_reset_callback device_reset_callback;
 553         struct u_log_context            *log;
 554
 555         void                            *query_result_shader;
 556
 557         /* Copy one resource to another using async DMA. */
 558         void (*dma_copy)(struct pipe_context *ctx,
 559                          struct pipe_resource *dst,
 560                          unsigned dst_level,
 561                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 562                          struct pipe_resource *src,
 563                          unsigned src_level,
 564                          const struct pipe_box *src_box);
 565
 566         void (*dma_clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 567                                  uint64_t offset, uint64_t size, unsigned value);
 568
 569         void (*blit_decompress_depth)(struct pipe_context *ctx,
 570                                       struct r600_texture *texture,
 571                                       struct r600_texture *staging,
 572                                       unsigned first_level, unsigned last_level,
 573                                       unsigned first_layer, unsigned last_layer,
 574                                       unsigned first_sample, unsigned last_sample);
 575
 576         void (*decompress_dcc)(struct pipe_context *ctx,
 577                                struct r600_texture *rtex);
 578
 579         /* Reallocate the buffer and update all resource bindings where
 580          * the buffer is bound, including all resource descriptors. */
 581         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 582
 583         /* Update all resource bindings where the buffer is bound, including
 584          * all resource descriptors. This is invalidate_buffer without
 585          * the invalidation. */
 586         void (*rebind_buffer)(struct pipe_context *ctx, struct pipe_resource *buf,
 587                               uint64_t old_gpu_address);
 588
 589         /* Enable or disable occlusion queries. */
 590         void (*set_occlusion_query_state)(struct pipe_context *ctx,
 591                                           bool old_enable,
 592                                           bool old_perfect_enable);
 593
 594         void (*save_qbo_state)(struct pipe_context *ctx, struct r600_qbo_state *st);
 595
 596         /* This ensures there is enough space in the command stream. */
 597         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 598                                   bool include_draw_vbo);
 599
 600         void (*set_atom_dirty)(struct r600_common_context *ctx,
 601                                struct r600_atom *atom, bool dirty);
 602
 603         void (*check_vm_faults)(struct r600_common_context *ctx,
 604                                 struct radeon_saved_cs *saved,
 605                                 enum ring_type ring);
 606 };
 607
 608 /* r600_buffer_common.c */
 609 bool si_rings_is_buffer_referenced(struct r600_common_context *ctx,
 610                                    struct pb_buffer *buf,
 611                                    enum radeon_bo_usage usage);
 612 void *si_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 613                                     struct r600_resource *resource,
 614                                     unsigned usage);
 615 void si_buffer_subdata(struct pipe_context *ctx,
 616                        struct pipe_resource *buffer,
 617                        unsigned usage, unsigned offset,
 618                        unsigned size, const void *data);
 619 void si_init_resource_fields(struct r600_common_screen *rscreen,
 620                              struct r600_resource *res,
 621                              uint64_t size, unsigned alignment);
 622 bool si_alloc_resource(struct r600_common_screen *rscreen,
 623                        struct r600_resource *res);
 624 struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
 625                                        const struct pipe_resource *templ,
 626                                        unsigned alignment);
 627 struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
 628                                                unsigned flags,
 629                                                unsigned usage,
 630                                                unsigned size,
 631                                                unsigned alignment);
 632 struct pipe_resource *
 633 si_buffer_from_user_memory(struct pipe_screen *screen,
 634                            const struct pipe_resource *templ,
 635                            void *user_memory);
 636 void si_invalidate_resource(struct pipe_context *ctx,
 637                             struct pipe_resource *resource);
 638 void si_replace_buffer_storage(struct pipe_context *ctx,
 639                                struct pipe_resource *dst,
 640                                struct pipe_resource *src);
 641
 642 /* r600_common_pipe.c */
 643 void si_gfx_write_event_eop(struct r600_common_context *ctx,
 644                             unsigned event, unsigned event_flags,
 645                             unsigned data_sel,
 646                             struct r600_resource *buf, uint64_t va,
 647                             uint32_t new_fence, unsigned query_type);
 648 unsigned si_gfx_write_fence_dwords(struct r600_common_screen *screen);
 649 void si_gfx_wait_fence(struct r600_common_context *ctx,
 650                        uint64_t va, uint32_t ref, uint32_t mask);
 651 bool si_common_screen_init(struct r600_common_screen *rscreen,
 652                            struct radeon_winsys *ws);
 653 void si_destroy_common_screen(struct r600_common_screen *rscreen);
 654 bool si_common_context_init(struct r600_common_context *rctx,
 655                             struct r600_common_screen *rscreen,
 656                             unsigned context_flags);
 657 void si_common_context_cleanup(struct r600_common_context *rctx);
 658 bool si_can_dump_shader(struct r600_common_screen *rscreen,
 659                         unsigned processor);
 660 bool si_extra_shader_checks(struct r600_common_screen *rscreen,
 661                             unsigned processor);
 662 void si_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 663                             uint64_t offset, uint64_t size, unsigned value);
 664 struct pipe_resource *si_resource_create_common(struct pipe_screen *screen,
 665                                                 const struct pipe_resource *templ);
 666 void si_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
 667                        struct r600_resource *dst, struct r600_resource *src);
 668 void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
 669                 struct radeon_saved_cs *saved, bool get_buffer_list);
 670 void si_clear_saved_cs(struct radeon_saved_cs *saved);
 671 bool si_check_device_reset(struct r600_common_context *rctx);
 672
 673 /* r600_gpu_load.c */
 674 void si_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 675 uint64_t si_begin_counter(struct r600_common_screen *rscreen, unsigned type);
 676 unsigned si_end_counter(struct r600_common_screen *rscreen, unsigned type,
 677                         uint64_t begin);
 678
 679 /* r600_perfcounters.c */
 680 void si_perfcounters_destroy(struct r600_common_screen *rscreen);
 681
 682 /* r600_query.c */
 683 void si_init_screen_query_functions(struct r600_common_screen *rscreen);
 684 void si_init_query_functions(struct r600_common_context *rctx);
 685 void si_suspend_queries(struct r600_common_context *ctx);
 686 void si_resume_queries(struct r600_common_context *ctx);
 687
 688 /* r600_texture.c */
 689 bool si_prepare_for_dma_blit(struct r600_common_context *rctx,
 690                              struct r600_texture *rdst,
 691                              unsigned dst_level, unsigned dstx,
 692                              unsigned dsty, unsigned dstz,
 693                              struct r600_texture *rsrc,
 694                              unsigned src_level,
 695                              const struct pipe_box *src_box);
 696 void si_texture_get_fmask_info(struct r600_common_screen *rscreen,
 697                                struct r600_texture *rtex,
 698                                unsigned nr_samples,
 699                                struct r600_fmask_info *out);
 700 void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
 701                                struct r600_texture *rtex,
 702                                struct r600_cmask_info *out);
 703 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
 704                                    struct pipe_resource *texture,
 705                                    struct r600_texture **staging);
 706 void si_print_texture_info(struct r600_common_screen *rscreen,
 707                            struct r600_texture *rtex, struct u_log_context *log);
 708 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
 709                                         const struct pipe_resource *templ);
 710 bool vi_dcc_formats_compatible(enum pipe_format format1,
 711                                enum pipe_format format2);
 712 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
 713                                      unsigned level,
 714                                      enum pipe_format view_format);
 715 void vi_disable_dcc_if_incompatible_format(struct r600_common_context *rctx,
 716                                            struct pipe_resource *tex,
 717                                            unsigned level,
 718                                            enum pipe_format view_format);
 719 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
 720                                               struct pipe_resource *texture,
 721                                               const struct pipe_surface *templ,
 722                                               unsigned width0, unsigned height0,
 723                                               unsigned width, unsigned height);
 724 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
 725 void vi_separate_dcc_try_enable(struct r600_common_context *rctx,
 726                                 struct r600_texture *tex);
 727 void vi_separate_dcc_start_query(struct pipe_context *ctx,
 728                                  struct r600_texture *tex);
 729 void vi_separate_dcc_stop_query(struct pipe_context *ctx,
 730                                 struct r600_texture *tex);
 731 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
 732                                              struct r600_texture *tex);
 733 bool si_texture_disable_dcc(struct r600_common_context *rctx,
 734                             struct r600_texture *rtex);
 735 void si_init_screen_texture_functions(struct r600_common_screen *rscreen);
 736 void si_init_context_texture_functions(struct r600_common_context *rctx);
 737
 738
 739 /* Inline helpers. */
 740
 741 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 742 {
 743         return (struct r600_resource*)r;
 744 }
 745
 746 static inline void
 747 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 748 {
 749         pipe_resource_reference((struct pipe_resource **)ptr,
 750                                 (struct pipe_resource *)res);
 751 }
 752
 753 static inline void
 754 r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
 755 {
 756         pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
 757 }
 758
 759 static inline bool
 760 vi_dcc_enabled(struct r600_texture *tex, unsigned level)
 761 {
 762         return tex->dcc_offset && level < tex->surface.num_dcc_levels;
 763 }
 764
 765 #define R600_ERR(fmt, args...) \
 766         fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
 767
 768 #endif