src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/u_slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define ATI_VENDOR_ID 0x1002
  47
  48 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  49 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  50 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  51 #define R600_RESOURCE_FLAG_DISABLE_DCC          (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
  52
  53 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  54 /* Pipeline & streamout query controls. */
  55 #define R600_CONTEXT_START_PIPELINE_STATS       (1u << 1)
  56 #define R600_CONTEXT_STOP_PIPELINE_STATS        (1u << 2)
  57 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 3)
  58
  59 /* special primitive types */
  60 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  61
  62 /* Debug flags. */
  63 /* logging */
  64 #define DBG_TEX                 (1 << 0)
  65 /* gap - reuse */
  66 #define DBG_COMPUTE             (1 << 2)
  67 #define DBG_VM                  (1 << 3)
  68 /* gap - reuse */
  69 /* shader logging */
  70 #define DBG_FS                  (1 << 5)
  71 #define DBG_VS                  (1 << 6)
  72 #define DBG_GS                  (1 << 7)
  73 #define DBG_PS                  (1 << 8)
  74 #define DBG_CS                  (1 << 9)
  75 #define DBG_TCS                 (1 << 10)
  76 #define DBG_TES                 (1 << 11)
  77 #define DBG_NO_IR               (1 << 12)
  78 #define DBG_NO_TGSI             (1 << 13)
  79 #define DBG_NO_ASM              (1 << 14)
  80 #define DBG_PREOPT_IR           (1 << 15)
  81 /* gaps */
  82 #define DBG_TEST_DMA            (1 << 20)
  83 /* Bits 21-31 are reserved for the r600g driver. */
  84 /* features */
  85 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  86 #define DBG_NO_HYPERZ           (1llu << 33)
  87 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  88 #define DBG_NO_2D_TILING        (1llu << 35)
  89 #define DBG_NO_TILING           (1llu << 36)
  90 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  91 #define DBG_FORCE_DMA           (1llu << 38)
  92 #define DBG_PRECOMPILE          (1llu << 39)
  93 #define DBG_INFO                (1llu << 40)
  94 #define DBG_NO_WC               (1llu << 41)
  95 #define DBG_CHECK_VM            (1llu << 42)
  96 #define DBG_NO_DCC              (1llu << 43)
  97 #define DBG_NO_DCC_CLEAR        (1llu << 44)
  98 #define DBG_NO_RB_PLUS          (1llu << 45)
  99 #define DBG_SI_SCHED            (1llu << 46)
 100 #define DBG_MONOLITHIC_SHADERS  (1llu << 47)
 101 #define DBG_NO_CE               (1llu << 48)
 102
 103 #define R600_MAP_BUFFER_ALIGNMENT 64
 104 #define R600_MAX_VIEWPORTS        16
 105
 106 enum r600_coherency {
 107         R600_COHERENCY_NONE, /* no cache flushes needed */
 108         R600_COHERENCY_SHADER,
 109         R600_COHERENCY_CB_META,
 110 };
 111
 112 #ifdef PIPE_ARCH_BIG_ENDIAN
 113 #define R600_BIG_ENDIAN 1
 114 #else
 115 #define R600_BIG_ENDIAN 0
 116 #endif
 117
 118 struct r600_common_context;
 119 struct r600_perfcounters;
 120 struct tgsi_shader_info;
 121
 122 struct radeon_shader_reloc {
 123         char name[32];
 124         uint64_t offset;
 125 };
 126
 127 struct radeon_shader_binary {
 128         /** Shader code */
 129         unsigned char *code;
 130         unsigned code_size;
 131
 132         /** Config/Context register state that accompanies this shader.
 133          * This is a stream of dword pairs.  First dword contains the
 134          * register address, the second dword contains the value.*/
 135         unsigned char *config;
 136         unsigned config_size;
 137
 138         /** The number of bytes of config information for each global symbol.
 139          */
 140         unsigned config_size_per_symbol;
 141
 142         /** Constant data accessed by the shader.  This will be uploaded
 143          * into a constant buffer. */
 144         unsigned char *rodata;
 145         unsigned rodata_size;
 146
 147         /** List of symbol offsets for the shader */
 148         uint64_t *global_symbol_offsets;
 149         unsigned global_symbol_count;
 150
 151         struct radeon_shader_reloc *relocs;
 152         unsigned reloc_count;
 153
 154         /** Disassembled shader in a string. */
 155         char *disasm_string;
 156 };
 157
 158 void radeon_shader_binary_init(struct radeon_shader_binary *b);
 159 void radeon_shader_binary_clean(struct radeon_shader_binary *b);
 160
 161 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
 162  * at the moment.
 163  */
 164 struct r600_resource {
 165         struct u_resource               b;
 166
 167         /* Winsys objects. */
 168         struct pb_buffer                *buf;
 169         uint64_t                        gpu_address;
 170
 171         /* Resource state. */
 172         enum radeon_bo_domain           domains;
 173
 174         /* The buffer range which is initialized (with a write transfer,
 175          * streamout, DMA, or as a random access target). The rest of
 176          * the buffer is considered invalid and can be mapped unsynchronized.
 177          *
 178          * This allows unsychronized mapping of a buffer range which hasn't
 179          * been used yet. It's for applications which forget to use
 180          * the unsynchronized map flag and expect the driver to figure it out.
 181          */
 182         struct util_range               valid_buffer_range;
 183
 184         /* For buffers only. This indicates that a write operation has been
 185          * performed by TC L2, but the cache hasn't been flushed.
 186          * Any hw block which doesn't use or bypasses TC L2 should check this
 187          * flag and flush the cache before using the buffer.
 188          *
 189          * For example, TC L2 must be flushed if a buffer which has been
 190          * modified by a shader store instruction is about to be used as
 191          * an index buffer. The reason is that VGT DMA index fetching doesn't
 192          * use TC L2.
 193          */
 194         bool                            TC_L2_dirty;
 195
 196         /* Whether the resource has been exported via resource_get_handle. */
 197         bool                            is_shared;
 198         unsigned                        external_usage; /* PIPE_HANDLE_USAGE_* */
 199 };
 200
 201 struct r600_transfer {
 202         struct pipe_transfer            transfer;
 203         struct r600_resource            *staging;
 204         unsigned                        offset;
 205 };
 206
 207 struct r600_fmask_info {
 208         uint64_t offset;
 209         uint64_t size;
 210         unsigned alignment;
 211         unsigned pitch_in_pixels;
 212         unsigned bank_height;
 213         unsigned slice_tile_max;
 214         unsigned tile_mode_index;
 215 };
 216
 217 struct r600_cmask_info {
 218         uint64_t offset;
 219         uint64_t size;
 220         unsigned alignment;
 221         unsigned pitch;
 222         unsigned height;
 223         unsigned xalign;
 224         unsigned yalign;
 225         unsigned slice_tile_max;
 226         unsigned base_address_reg;
 227 };
 228
 229 struct r600_htile_info {
 230         unsigned pitch;
 231         unsigned height;
 232         unsigned xalign;
 233         unsigned yalign;
 234 };
 235
 236 struct r600_texture {
 237         struct r600_resource            resource;
 238
 239         uint64_t                        size;
 240         unsigned                        num_level0_transfers;
 241         bool                            is_depth;
 242         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 243         unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 244         struct r600_texture             *flushed_depth_texture;
 245         boolean                         is_flushing_texture;
 246         struct radeon_surf              surface;
 247
 248         /* Colorbuffer compression and fast clear. */
 249         struct r600_fmask_info          fmask;
 250         struct r600_cmask_info          cmask;
 251         struct r600_resource            *cmask_buffer;
 252         uint64_t                        dcc_offset; /* 0 = disabled */
 253         unsigned                        cb_color_info; /* fast clear enable bit */
 254         unsigned                        color_clear_value[2];
 255
 256         /* Depth buffer compression and fast clear. */
 257         struct r600_htile_info          htile;
 258         struct r600_resource            *htile_buffer;
 259         bool                            depth_cleared; /* if it was cleared at least once */
 260         float                           depth_clear_value;
 261         bool                            stencil_cleared; /* if it was cleared at least once */
 262         uint8_t                         stencil_clear_value;
 263
 264         bool                            non_disp_tiling; /* R600-Cayman only */
 265
 266         /* Counter that should be non-zero if the texture is bound to a
 267          * framebuffer. Implemented in radeonsi only.
 268          */
 269         uint32_t                        framebuffers_bound;
 270 };
 271
 272 struct r600_surface {
 273         struct pipe_surface             base;
 274         const struct radeon_surf_level  *level_info;
 275
 276         bool color_initialized;
 277         bool depth_initialized;
 278
 279         /* Misc. color flags. */
 280         bool alphatest_bypass;
 281         bool export_16bpc;
 282         bool color_is_int8;
 283
 284         /* Color registers. */
 285         unsigned cb_color_info;
 286         unsigned cb_color_base;
 287         unsigned cb_color_view;
 288         unsigned cb_color_size;         /* R600 only */
 289         unsigned cb_color_dim;          /* EG only */
 290         unsigned cb_color_pitch;        /* EG and later */
 291         unsigned cb_color_slice;        /* EG and later */
 292         unsigned cb_color_attrib;       /* EG and later */
 293         unsigned cb_dcc_control;        /* VI and later */
 294         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 295         unsigned cb_color_fmask_slice;  /* EG and later */
 296         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 297         unsigned cb_color_mask;         /* R600 only */
 298         unsigned spi_shader_col_format;         /* SI+, no blending, no alpha-to-coverage. */
 299         unsigned spi_shader_col_format_alpha;   /* SI+, alpha-to-coverage */
 300         unsigned spi_shader_col_format_blend;   /* SI+, blending without alpha. */
 301         unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
 302         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 303         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 304
 305         /* DB registers. */
 306         unsigned db_depth_info;         /* R600 only, then SI and later */
 307         unsigned db_z_info;             /* EG and later */
 308         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 309         unsigned db_depth_view;
 310         unsigned db_depth_size;
 311         unsigned db_depth_slice;        /* EG and later */
 312         unsigned db_stencil_base;       /* EG and later */
 313         unsigned db_stencil_info;       /* EG and later */
 314         unsigned db_prefetch_limit;     /* R600 only */
 315         unsigned db_htile_surface;
 316         unsigned db_htile_data_base;
 317         unsigned db_preload_control;    /* EG and later */
 318         unsigned pa_su_poly_offset_db_fmt_cntl;
 319 };
 320
 321 struct r600_common_screen {
 322         struct pipe_screen              b;
 323         struct radeon_winsys            *ws;
 324         enum radeon_family              family;
 325         enum chip_class                 chip_class;
 326         struct radeon_info              info;
 327         uint64_t                        debug_flags;
 328         bool                            has_cp_dma;
 329         bool                            has_streamout;
 330
 331         /* Texture filter settings. */
 332         int                             force_aniso; /* -1 = disabled */
 333
 334         /* Auxiliary context. Mainly used to initialize resources.
 335          * It must be locked prior to using and flushed before unlocking. */
 336         struct pipe_context             *aux_context;
 337         pipe_mutex                      aux_context_lock;
 338
 339         /* This must be in the screen, because UE4 uses one context for
 340          * compilation and another one for rendering.
 341          */
 342         unsigned                        num_compilations;
 343         /* Along with ST_DEBUG=precompile, this should show if applications
 344          * are loading shaders on demand. This is a monotonic counter.
 345          */
 346         unsigned                        num_shaders_created;
 347
 348         /* GPU load thread. */
 349         pipe_mutex                      gpu_load_mutex;
 350         pipe_thread                     gpu_load_thread;
 351         unsigned                        gpu_load_counter_busy;
 352         unsigned                        gpu_load_counter_idle;
 353         volatile unsigned               gpu_load_stop_thread; /* bool */
 354
 355         char                            renderer_string[64];
 356
 357         /* Performance counters. */
 358         struct r600_perfcounters        *perfcounters;
 359
 360         /* If pipe_screen wants to re-emit the framebuffer state of all
 361          * contexts, it should atomically increment this. Each context will
 362          * compare this with its own last known value of the counter before
 363          * drawing and re-emit the framebuffer state accordingly.
 364          */
 365         unsigned                        dirty_fb_counter;
 366
 367         /* Atomically increment this counter when an existing texture's
 368          * metadata is enabled or disabled in a way that requires changing
 369          * contexts' compressed texture binding masks.
 370          */
 371         unsigned                        compressed_colortex_counter;
 372
 373         /* Atomically increment this counter when an existing texture's
 374          * backing buffer or tile mode parameters have changed that requires
 375          * recomputation of shader descriptors.
 376          */
 377         unsigned                        dirty_tex_descriptor_counter;
 378
 379         void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
 380                                       struct r600_texture *rtex,
 381                                       struct radeon_bo_metadata *md);
 382
 383         void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
 384                                     struct r600_texture *rtex,
 385                                     struct radeon_bo_metadata *md);
 386 };
 387
 388 /* This encapsulates a state or an operation which can emitted into the GPU
 389  * command stream. */
 390 struct r600_atom {
 391         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 392         unsigned                num_dw;
 393         unsigned short          id;
 394 };
 395
 396 struct r600_so_target {
 397         struct pipe_stream_output_target b;
 398
 399         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 400         struct r600_resource    *buf_filled_size;
 401         unsigned                buf_filled_size_offset;
 402         bool                    buf_filled_size_valid;
 403
 404         unsigned                stride_in_dw;
 405 };
 406
 407 struct r600_streamout {
 408         struct r600_atom                begin_atom;
 409         bool                            begin_emitted;
 410         unsigned                        num_dw_for_end;
 411
 412         unsigned                        enabled_mask;
 413         unsigned                        num_targets;
 414         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 415
 416         unsigned                        append_bitmask;
 417         bool                            suspended;
 418
 419         /* External state which comes from the vertex shader,
 420          * it must be set explicitly when binding a shader. */
 421         unsigned                        *stride_in_dw;
 422         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 423
 424         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 425         unsigned                        hw_enabled_mask;
 426
 427         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 428         struct r600_atom                enable_atom;
 429         bool                            streamout_enabled;
 430         bool                            prims_gen_query_enabled;
 431         int                             num_prims_gen_queries;
 432 };
 433
 434 struct r600_signed_scissor {
 435         int minx;
 436         int miny;
 437         int maxx;
 438         int maxy;
 439 };
 440
 441 struct r600_scissors {
 442         struct r600_atom                atom;
 443         unsigned                        dirty_mask;
 444         struct pipe_scissor_state       states[R600_MAX_VIEWPORTS];
 445 };
 446
 447 struct r600_viewports {
 448         struct r600_atom                atom;
 449         unsigned                        dirty_mask;
 450         struct pipe_viewport_state      states[R600_MAX_VIEWPORTS];
 451         struct r600_signed_scissor      as_scissor[R600_MAX_VIEWPORTS];
 452 };
 453
 454 struct r600_ring {
 455         struct radeon_winsys_cs         *cs;
 456         void (*flush)(void *ctx, unsigned flags,
 457                       struct pipe_fence_handle **fence);
 458 };
 459
 460 struct r600_common_context {
 461         struct pipe_context b; /* base class */
 462
 463         struct r600_common_screen       *screen;
 464         struct radeon_winsys            *ws;
 465         struct radeon_winsys_ctx        *ctx;
 466         enum radeon_family              family;
 467         enum chip_class                 chip_class;
 468         struct r600_ring                gfx;
 469         struct r600_ring                dma;
 470         struct pipe_fence_handle        *last_sdma_fence;
 471         unsigned                        initial_gfx_cs_size;
 472         unsigned                        gpu_reset_counter;
 473         unsigned                        last_dirty_fb_counter;
 474         unsigned                        last_compressed_colortex_counter;
 475         unsigned                        last_dirty_tex_descriptor_counter;
 476
 477         struct u_upload_mgr             *uploader;
 478         struct u_suballocator           *allocator_zeroed_memory;
 479         struct util_slab_mempool        pool_transfers;
 480
 481         /* Current unaccounted memory usage. */
 482         uint64_t                        vram;
 483         uint64_t                        gtt;
 484
 485         /* States. */
 486         struct r600_streamout           streamout;
 487         struct r600_scissors            scissors;
 488         struct r600_viewports           viewports;
 489         bool                            scissor_enabled;
 490         bool                            vs_writes_viewport_index;
 491         bool                            vs_disables_clipping_viewport;
 492
 493         /* Additional context states. */
 494         unsigned flags; /* flush flags */
 495
 496         /* Queries. */
 497         /* Maintain the list of active queries for pausing between IBs. */
 498         int                             num_occlusion_queries;
 499         int                             num_perfect_occlusion_queries;
 500         struct list_head                active_queries;
 501         unsigned                        num_cs_dw_queries_suspend;
 502         /* Additional hardware info. */
 503         unsigned                        backend_mask;
 504         unsigned                        max_db; /* for OQ */
 505         /* Misc stats. */
 506         unsigned                        num_draw_calls;
 507         unsigned                        num_dma_calls;
 508         uint64_t                        num_alloc_tex_transfer_bytes;
 509
 510         /* Render condition. */
 511         struct r600_atom                render_cond_atom;
 512         struct pipe_query               *render_cond;
 513         unsigned                        render_cond_mode;
 514         boolean                         render_cond_invert;
 515         bool                            render_cond_force_off; /* for u_blitter */
 516
 517         /* MSAA sample locations.
 518          * The first index is the sample index.
 519          * The second index is the coordinate: X, Y. */
 520         float                           sample_locations_1x[1][2];
 521         float                           sample_locations_2x[2][2];
 522         float                           sample_locations_4x[4][2];
 523         float                           sample_locations_8x[8][2];
 524         float                           sample_locations_16x[16][2];
 525
 526         /* The list of all texture buffer objects in this context.
 527          * This list is walked when a buffer is invalidated/reallocated and
 528          * the GPU addresses are updated. */
 529         struct list_head                texture_buffers;
 530
 531         struct pipe_debug_callback      debug;
 532
 533         /* Copy one resource to another using async DMA. */
 534         void (*dma_copy)(struct pipe_context *ctx,
 535                          struct pipe_resource *dst,
 536                          unsigned dst_level,
 537                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 538                          struct pipe_resource *src,
 539                          unsigned src_level,
 540                          const struct pipe_box *src_box);
 541
 542         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 543                              uint64_t offset, uint64_t size, unsigned value,
 544                              enum r600_coherency coher);
 545
 546         void (*blit_decompress_depth)(struct pipe_context *ctx,
 547                                       struct r600_texture *texture,
 548                                       struct r600_texture *staging,
 549                                       unsigned first_level, unsigned last_level,
 550                                       unsigned first_layer, unsigned last_layer,
 551                                       unsigned first_sample, unsigned last_sample);
 552
 553         void (*decompress_dcc)(struct pipe_context *ctx,
 554                                struct r600_texture *rtex);
 555
 556         /* Reallocate the buffer and update all resource bindings where
 557          * the buffer is bound, including all resource descriptors. */
 558         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 559
 560         /* Enable or disable occlusion queries. */
 561         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 562
 563         /* This ensures there is enough space in the command stream. */
 564         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 565                                   bool include_draw_vbo);
 566
 567         void (*set_atom_dirty)(struct r600_common_context *ctx,
 568                                struct r600_atom *atom, bool dirty);
 569 };
 570
 571 /* r600_buffer.c */
 572 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 573                                         struct pb_buffer *buf,
 574                                         enum radeon_bo_usage usage);
 575 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 576                                       struct r600_resource *resource,
 577                                       unsigned usage);
 578 bool r600_init_resource(struct r600_common_screen *rscreen,
 579                         struct r600_resource *res,
 580                         uint64_t size, unsigned alignment);
 581 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 582                                          const struct pipe_resource *templ,
 583                                          unsigned alignment);
 584 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
 585                                                   unsigned bind,
 586                                                   unsigned usage,
 587                                                   unsigned size,
 588                                                   unsigned alignment);
 589 struct pipe_resource *
 590 r600_buffer_from_user_memory(struct pipe_screen *screen,
 591                              const struct pipe_resource *templ,
 592                              void *user_memory);
 593 void
 594 r600_invalidate_resource(struct pipe_context *ctx,
 595                          struct pipe_resource *resource);
 596
 597 /* r600_common_pipe.c */
 598 void r600_draw_rectangle(struct blitter_context *blitter,
 599                          int x1, int y1, int x2, int y2, float depth,
 600                          enum blitter_attrib_type type,
 601                          const union pipe_color_union *attrib);
 602 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 603                              struct radeon_winsys *ws);
 604 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 605 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 606 void r600_postflush_resume_features(struct r600_common_context *ctx);
 607 bool r600_common_context_init(struct r600_common_context *rctx,
 608                               struct r600_common_screen *rscreen);
 609 void r600_common_context_cleanup(struct r600_common_context *rctx);
 610 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 611 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 612                           unsigned processor);
 613 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 614                               uint64_t offset, uint64_t size, unsigned value,
 615                               enum r600_coherency coher);
 616 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 617                                                   const struct pipe_resource *templ);
 618 const char *r600_get_llvm_processor_name(enum radeon_family family);
 619 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
 620                          struct r600_resource *dst, struct r600_resource *src);
 621 void r600_dma_emit_wait_idle(struct r600_common_context *rctx);
 622
 623 /* r600_gpu_load.c */
 624 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 625 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
 626 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 627
 628 /* r600_perfcounters.c */
 629 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
 630
 631 /* r600_query.c */
 632 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
 633 void r600_query_init(struct r600_common_context *rctx);
 634 void r600_suspend_queries(struct r600_common_context *ctx);
 635 void r600_resume_queries(struct r600_common_context *ctx);
 636 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 637
 638 /* r600_streamout.c */
 639 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 640 void r600_set_streamout_targets(struct pipe_context *ctx,
 641                                 unsigned num_targets,
 642                                 struct pipe_stream_output_target **targets,
 643                                 const unsigned *offset);
 644 void r600_emit_streamout_end(struct r600_common_context *rctx);
 645 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 646                                              unsigned type, int diff);
 647 void r600_streamout_init(struct r600_common_context *rctx);
 648
 649 /* r600_test_dma.c */
 650 void r600_test_dma(struct r600_common_screen *rscreen);
 651
 652 /* r600_texture.c */
 653 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
 654                                 struct r600_texture *rdst,
 655                                 unsigned dst_level, unsigned dstx,
 656                                 unsigned dsty, unsigned dstz,
 657                                 struct r600_texture *rsrc,
 658                                 unsigned src_level,
 659                                 const struct pipe_box *src_box);
 660 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 661                                  struct r600_texture *rtex,
 662                                  unsigned nr_samples,
 663                                  struct r600_fmask_info *out);
 664 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 665                                  struct r600_texture *rtex,
 666                                  struct r600_cmask_info *out);
 667 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 668                                      struct pipe_resource *texture,
 669                                      struct r600_texture **staging);
 670 void r600_print_texture_info(struct r600_texture *rtex, FILE *f);
 671 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 672                                         const struct pipe_resource *templ);
 673 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 674                                                 struct pipe_resource *texture,
 675                                                 const struct pipe_surface *templ,
 676                                                 unsigned width, unsigned height);
 677 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
 678 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 679                                    struct pipe_framebuffer_state *fb,
 680                                    struct r600_atom *fb_state,
 681                                    unsigned *buffers, unsigned *dirty_cbufs,
 682                                    const union pipe_color_union *color);
 683 bool r600_texture_disable_dcc(struct r600_common_screen *rscreen,
 684                               struct r600_texture *rtex);
 685 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 686 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 687
 688 /* r600_viewport.c */
 689 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
 690                                             struct pipe_scissor_state *scissor);
 691 void r600_set_scissor_enable(struct r600_common_context *rctx, bool enable);
 692 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
 693                                           struct tgsi_shader_info *info);
 694 void r600_init_viewport_functions(struct r600_common_context *rctx);
 695
 696 /* cayman_msaa.c */
 697 extern const uint32_t eg_sample_locs_2x[4];
 698 extern const unsigned eg_max_dist_2x;
 699 extern const uint32_t eg_sample_locs_4x[4];
 700 extern const unsigned eg_max_dist_4x;
 701 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 702                                 unsigned sample_index, float *out_value);
 703 void cayman_init_msaa(struct pipe_context *ctx);
 704 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 705 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 706                              int ps_iter_samples, int overrast_samples);
 707
 708
 709 /* Inline helpers. */
 710
 711 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 712 {
 713         return (struct r600_resource*)r;
 714 }
 715
 716 static inline void
 717 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 718 {
 719         pipe_resource_reference((struct pipe_resource **)ptr,
 720                                 (struct pipe_resource *)res);
 721 }
 722
 723 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
 724 {
 725         return rctx->streamout.streamout_enabled ||
 726                rctx->streamout.prims_gen_query_enabled;
 727 }
 728
 729 #define     SQ_TEX_XY_FILTER_POINT                         0x00
 730 #define     SQ_TEX_XY_FILTER_BILINEAR                      0x01
 731 #define     SQ_TEX_XY_FILTER_ANISO_POINT                   0x02
 732 #define     SQ_TEX_XY_FILTER_ANISO_BILINEAR                0x03
 733
 734 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
 735 {
 736         if (filter == PIPE_TEX_FILTER_LINEAR)
 737                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
 738                                      : SQ_TEX_XY_FILTER_BILINEAR;
 739         else
 740                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
 741                                      : SQ_TEX_XY_FILTER_POINT;
 742 }
 743
 744 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 745 {
 746         if (filter < 2)
 747                 return 0;
 748         if (filter < 4)
 749                 return 1;
 750         if (filter < 8)
 751                 return 2;
 752         if (filter < 16)
 753                 return 3;
 754         return 4;
 755 }
 756
 757 static inline unsigned r600_wavefront_size(enum radeon_family family)
 758 {
 759         switch (family) {
 760         case CHIP_RV610:
 761         case CHIP_RS780:
 762         case CHIP_RV620:
 763         case CHIP_RS880:
 764                 return 16;
 765         case CHIP_RV630:
 766         case CHIP_RV635:
 767         case CHIP_RV730:
 768         case CHIP_RV710:
 769         case CHIP_PALM:
 770         case CHIP_CEDAR:
 771                 return 32;
 772         default:
 773                 return 64;
 774         }
 775 }
 776
 777 static inline enum radeon_bo_priority
 778 r600_get_sampler_view_priority(struct r600_resource *res)
 779 {
 780         if (res->b.b.target == PIPE_BUFFER)
 781                 return RADEON_PRIO_SAMPLER_BUFFER;
 782
 783         if (res->b.b.nr_samples > 1)
 784                 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
 785
 786         return RADEON_PRIO_SAMPLER_TEXTURE;
 787 }
 788
 789 #define COMPUTE_DBG(rscreen, fmt, args...) \
 790         do { \
 791                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 792         } while (0);
 793
 794 #define R600_ERR(fmt, args...) \
 795         fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
 796
 797 /* For MSAA sample positions. */
 798 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 799         (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) |                  \
 800         (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) |         \
 801         (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) |        \
 802          (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
 803
 804 #endif