src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define ATI_VENDOR_ID 0x1002
  47
  48 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  49 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  50 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  51 #define R600_RESOURCE_FLAG_DISABLE_DCC          (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
  52
  53 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  54 /* Pipeline & streamout query controls. */
  55 #define R600_CONTEXT_START_PIPELINE_STATS       (1u << 1)
  56 #define R600_CONTEXT_STOP_PIPELINE_STATS        (1u << 2)
  57 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 3)
  58
  59 /* special primitive types */
  60 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  61
  62 /* Debug flags. */
  63 /* logging */
  64 #define DBG_TEX                 (1 << 0)
  65 /* gap - reuse */
  66 #define DBG_COMPUTE             (1 << 2)
  67 #define DBG_VM                  (1 << 3)
  68 /* gap - reuse */
  69 /* shader logging */
  70 #define DBG_FS                  (1 << 5)
  71 #define DBG_VS                  (1 << 6)
  72 #define DBG_GS                  (1 << 7)
  73 #define DBG_PS                  (1 << 8)
  74 #define DBG_CS                  (1 << 9)
  75 #define DBG_TCS                 (1 << 10)
  76 #define DBG_TES                 (1 << 11)
  77 #define DBG_NO_IR               (1 << 12)
  78 #define DBG_NO_TGSI             (1 << 13)
  79 #define DBG_NO_ASM              (1 << 14)
  80 #define DBG_PREOPT_IR           (1 << 15)
  81 /* gaps */
  82 #define DBG_TEST_DMA            (1 << 20)
  83 /* Bits 21-31 are reserved for the r600g driver. */
  84 /* features */
  85 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  86 #define DBG_NO_HYPERZ           (1llu << 33)
  87 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  88 #define DBG_NO_2D_TILING        (1llu << 35)
  89 #define DBG_NO_TILING           (1llu << 36)
  90 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  91 #define DBG_FORCE_DMA           (1llu << 38)
  92 #define DBG_PRECOMPILE          (1llu << 39)
  93 #define DBG_INFO                (1llu << 40)
  94 #define DBG_NO_WC               (1llu << 41)
  95 #define DBG_CHECK_VM            (1llu << 42)
  96 #define DBG_NO_DCC              (1llu << 43)
  97 #define DBG_NO_DCC_CLEAR        (1llu << 44)
  98 #define DBG_NO_RB_PLUS          (1llu << 45)
  99 #define DBG_SI_SCHED            (1llu << 46)
 100 #define DBG_MONOLITHIC_SHADERS  (1llu << 47)
 101 #define DBG_NO_CE               (1llu << 48)
 102 #define DBG_UNSAFE_MATH         (1llu << 49)
 103 #define DBG_NO_DCC_FB           (1llu << 50)
 104
 105 #define R600_MAP_BUFFER_ALIGNMENT 64
 106 #define R600_MAX_VIEWPORTS        16
 107
 108 enum r600_coherency {
 109         R600_COHERENCY_NONE, /* no cache flushes needed */
 110         R600_COHERENCY_SHADER,
 111         R600_COHERENCY_CB_META,
 112 };
 113
 114 #ifdef PIPE_ARCH_BIG_ENDIAN
 115 #define R600_BIG_ENDIAN 1
 116 #else
 117 #define R600_BIG_ENDIAN 0
 118 #endif
 119
 120 struct r600_common_context;
 121 struct r600_perfcounters;
 122 struct tgsi_shader_info;
 123 struct r600_qbo_state;
 124
 125 struct radeon_shader_reloc {
 126         char name[32];
 127         uint64_t offset;
 128 };
 129
 130 struct radeon_shader_binary {
 131         /** Shader code */
 132         unsigned char *code;
 133         unsigned code_size;
 134
 135         /** Config/Context register state that accompanies this shader.
 136          * This is a stream of dword pairs.  First dword contains the
 137          * register address, the second dword contains the value.*/
 138         unsigned char *config;
 139         unsigned config_size;
 140
 141         /** The number of bytes of config information for each global symbol.
 142          */
 143         unsigned config_size_per_symbol;
 144
 145         /** Constant data accessed by the shader.  This will be uploaded
 146          * into a constant buffer. */
 147         unsigned char *rodata;
 148         unsigned rodata_size;
 149
 150         /** List of symbol offsets for the shader */
 151         uint64_t *global_symbol_offsets;
 152         unsigned global_symbol_count;
 153
 154         struct radeon_shader_reloc *relocs;
 155         unsigned reloc_count;
 156
 157         /** Disassembled shader in a string. */
 158         char *disasm_string;
 159         char *llvm_ir_string;
 160 };
 161
 162 void radeon_shader_binary_init(struct radeon_shader_binary *b);
 163 void radeon_shader_binary_clean(struct radeon_shader_binary *b);
 164
 165 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
 166  * at the moment.
 167  */
 168 struct r600_resource {
 169         struct u_resource               b;
 170
 171         /* Winsys objects. */
 172         struct pb_buffer                *buf;
 173         uint64_t                        gpu_address;
 174         /* Memory usage if the buffer placement is optimal. */
 175         uint64_t                        vram_usage;
 176         uint64_t                        gart_usage;
 177
 178         /* Resource properties. */
 179         uint64_t                        bo_size;
 180         unsigned                        bo_alignment;
 181         enum radeon_bo_domain           domains;
 182         enum radeon_bo_flag             flags;
 183
 184         /* The buffer range which is initialized (with a write transfer,
 185          * streamout, DMA, or as a random access target). The rest of
 186          * the buffer is considered invalid and can be mapped unsynchronized.
 187          *
 188          * This allows unsychronized mapping of a buffer range which hasn't
 189          * been used yet. It's for applications which forget to use
 190          * the unsynchronized map flag and expect the driver to figure it out.
 191          */
 192         struct util_range               valid_buffer_range;
 193
 194         /* For buffers only. This indicates that a write operation has been
 195          * performed by TC L2, but the cache hasn't been flushed.
 196          * Any hw block which doesn't use or bypasses TC L2 should check this
 197          * flag and flush the cache before using the buffer.
 198          *
 199          * For example, TC L2 must be flushed if a buffer which has been
 200          * modified by a shader store instruction is about to be used as
 201          * an index buffer. The reason is that VGT DMA index fetching doesn't
 202          * use TC L2.
 203          */
 204         bool                            TC_L2_dirty;
 205
 206         /* Whether the resource has been exported via resource_get_handle. */
 207         bool                            is_shared;
 208         unsigned                        external_usage; /* PIPE_HANDLE_USAGE_* */
 209 };
 210
 211 struct r600_transfer {
 212         struct pipe_transfer            transfer;
 213         struct r600_resource            *staging;
 214         unsigned                        offset;
 215 };
 216
 217 struct r600_fmask_info {
 218         uint64_t offset;
 219         uint64_t size;
 220         unsigned alignment;
 221         unsigned pitch_in_pixels;
 222         unsigned bank_height;
 223         unsigned slice_tile_max;
 224         unsigned tile_mode_index;
 225 };
 226
 227 struct r600_cmask_info {
 228         uint64_t offset;
 229         uint64_t size;
 230         unsigned alignment;
 231         unsigned pitch;
 232         unsigned height;
 233         unsigned xalign;
 234         unsigned yalign;
 235         unsigned slice_tile_max;
 236         unsigned base_address_reg;
 237 };
 238
 239 struct r600_htile_info {
 240         unsigned pitch;
 241         unsigned height;
 242         unsigned xalign;
 243         unsigned yalign;
 244 };
 245
 246 struct r600_texture {
 247         struct r600_resource            resource;
 248
 249         uint64_t                        size;
 250         unsigned                        num_level0_transfers;
 251         bool                            is_depth;
 252         bool                            db_compatible;
 253         bool                            can_sample_z;
 254         bool                            can_sample_s;
 255         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 256         unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 257         struct r600_texture             *flushed_depth_texture;
 258         struct radeon_surf              surface;
 259
 260         /* Colorbuffer compression and fast clear. */
 261         struct r600_fmask_info          fmask;
 262         struct r600_cmask_info          cmask;
 263         struct r600_resource            *cmask_buffer;
 264         uint64_t                        dcc_offset; /* 0 = disabled */
 265         unsigned                        cb_color_info; /* fast clear enable bit */
 266         unsigned                        color_clear_value[2];
 267         unsigned                        last_msaa_resolve_target_micro_mode;
 268
 269         /* Depth buffer compression and fast clear. */
 270         struct r600_htile_info          htile;
 271         struct r600_resource            *htile_buffer;
 272         bool                            depth_cleared; /* if it was cleared at least once */
 273         float                           depth_clear_value;
 274         bool                            stencil_cleared; /* if it was cleared at least once */
 275         uint8_t                         stencil_clear_value;
 276
 277         bool                            non_disp_tiling; /* R600-Cayman only */
 278
 279         /* Whether the texture is a displayable back buffer and needs DCC
 280          * decompression, which is expensive. Therefore, it's enabled only
 281          * if statistics suggest that it will pay off and it's allocated
 282          * separately. It can't be bound as a sampler by apps. Limited to
 283          * target == 2D and last_level == 0. If enabled, dcc_offset contains
 284          * the absolute GPUVM address, not the relative one.
 285          */
 286         struct r600_resource            *dcc_separate_buffer;
 287         /* When DCC is temporarily disabled, the separate buffer is here. */
 288         struct r600_resource            *last_dcc_separate_buffer;
 289         /* We need to track DCC dirtiness, because st/dri usually calls
 290          * flush_resource twice per frame (not a bug) and we don't wanna
 291          * decompress DCC twice. Also, the dirty tracking must be done even
 292          * if DCC isn't used, because it's required by the DCC usage analysis
 293          * for a possible future enablement.
 294          */
 295         bool                            separate_dcc_dirty;
 296         /* Statistics gathering for the DCC enablement heuristic. */
 297         bool                            dcc_gather_statistics;
 298         /* Estimate of how much this color buffer is written to in units of
 299          * full-screen draws: ps_invocations / (width * height)
 300          * Shader kills, late Z, and blending with trivial discards make it
 301          * inaccurate (we need to count CB updates, not PS invocations).
 302          */
 303         unsigned                        ps_draw_ratio;
 304         /* The number of clears since the last DCC usage analysis. */
 305         unsigned                        num_slow_clears;
 306
 307         /* Counter that should be non-zero if the texture is bound to a
 308          * framebuffer. Implemented in radeonsi only.
 309          */
 310         uint32_t                        framebuffers_bound;
 311 };
 312
 313 struct r600_surface {
 314         struct pipe_surface             base;
 315         const struct radeon_surf_level  *level_info;
 316
 317         bool color_initialized;
 318         bool depth_initialized;
 319
 320         /* Misc. color flags. */
 321         bool alphatest_bypass;
 322         bool export_16bpc;
 323         bool color_is_int8;
 324
 325         /* Color registers. */
 326         unsigned cb_color_info;
 327         unsigned cb_color_base;
 328         unsigned cb_color_view;
 329         unsigned cb_color_size;         /* R600 only */
 330         unsigned cb_color_dim;          /* EG only */
 331         unsigned cb_color_pitch;        /* EG and later */
 332         unsigned cb_color_slice;        /* EG and later */
 333         unsigned cb_color_attrib;       /* EG and later */
 334         unsigned cb_dcc_control;        /* VI and later */
 335         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 336         unsigned cb_color_fmask_slice;  /* EG and later */
 337         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 338         unsigned cb_color_mask;         /* R600 only */
 339         unsigned spi_shader_col_format;         /* SI+, no blending, no alpha-to-coverage. */
 340         unsigned spi_shader_col_format_alpha;   /* SI+, alpha-to-coverage */
 341         unsigned spi_shader_col_format_blend;   /* SI+, blending without alpha. */
 342         unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
 343         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 344         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 345
 346         /* DB registers. */
 347         unsigned db_depth_info;         /* R600 only, then SI and later */
 348         unsigned db_z_info;             /* EG and later */
 349         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 350         unsigned db_depth_view;
 351         unsigned db_depth_size;
 352         unsigned db_depth_slice;        /* EG and later */
 353         unsigned db_stencil_base;       /* EG and later */
 354         unsigned db_stencil_info;       /* EG and later */
 355         unsigned db_prefetch_limit;     /* R600 only */
 356         unsigned db_htile_surface;
 357         unsigned db_htile_data_base;
 358         unsigned db_preload_control;    /* EG and later */
 359 };
 360
 361 struct r600_common_screen {
 362         struct pipe_screen              b;
 363         struct radeon_winsys            *ws;
 364         enum radeon_family              family;
 365         enum chip_class                 chip_class;
 366         struct radeon_info              info;
 367         uint64_t                        debug_flags;
 368         bool                            has_cp_dma;
 369         bool                            has_streamout;
 370
 371         /* Texture filter settings. */
 372         int                             force_aniso; /* -1 = disabled */
 373
 374         /* Auxiliary context. Mainly used to initialize resources.
 375          * It must be locked prior to using and flushed before unlocking. */
 376         struct pipe_context             *aux_context;
 377         pipe_mutex                      aux_context_lock;
 378
 379         /* This must be in the screen, because UE4 uses one context for
 380          * compilation and another one for rendering.
 381          */
 382         unsigned                        num_compilations;
 383         /* Along with ST_DEBUG=precompile, this should show if applications
 384          * are loading shaders on demand. This is a monotonic counter.
 385          */
 386         unsigned                        num_shaders_created;
 387
 388         /* GPU load thread. */
 389         pipe_mutex                      gpu_load_mutex;
 390         pipe_thread                     gpu_load_thread;
 391         unsigned                        gpu_load_counter_busy;
 392         unsigned                        gpu_load_counter_idle;
 393         volatile unsigned               gpu_load_stop_thread; /* bool */
 394
 395         char                            renderer_string[100];
 396
 397         /* Performance counters. */
 398         struct r600_perfcounters        *perfcounters;
 399
 400         /* If pipe_screen wants to re-emit the framebuffer state of all
 401          * contexts, it should atomically increment this. Each context will
 402          * compare this with its own last known value of the counter before
 403          * drawing and re-emit the framebuffer state accordingly.
 404          */
 405         unsigned                        dirty_fb_counter;
 406
 407         /* Atomically increment this counter when an existing texture's
 408          * metadata is enabled or disabled in a way that requires changing
 409          * contexts' compressed texture binding masks.
 410          */
 411         unsigned                        compressed_colortex_counter;
 412
 413         /* Atomically increment this counter when an existing texture's
 414          * backing buffer or tile mode parameters have changed that requires
 415          * recomputation of shader descriptors.
 416          */
 417         unsigned                        dirty_tex_descriptor_counter;
 418
 419         struct {
 420                 /* Context flags to set so that all writes from earlier jobs
 421                  * in the CP are seen by L2 clients.
 422                  */
 423                 unsigned cp_to_L2;
 424
 425                 /* Context flags to set so that all writes from earlier
 426                  * compute jobs are seen by L2 clients.
 427                  */
 428                 unsigned compute_to_L2;
 429         } barrier_flags;
 430
 431         void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
 432                                       struct r600_texture *rtex,
 433                                       struct radeon_bo_metadata *md);
 434
 435         void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
 436                                     struct r600_texture *rtex,
 437                                     struct radeon_bo_metadata *md);
 438 };
 439
 440 /* This encapsulates a state or an operation which can emitted into the GPU
 441  * command stream. */
 442 struct r600_atom {
 443         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 444         unsigned                num_dw;
 445         unsigned short          id;
 446 };
 447
 448 struct r600_so_target {
 449         struct pipe_stream_output_target b;
 450
 451         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 452         struct r600_resource    *buf_filled_size;
 453         unsigned                buf_filled_size_offset;
 454         bool                    buf_filled_size_valid;
 455
 456         unsigned                stride_in_dw;
 457 };
 458
 459 struct r600_streamout {
 460         struct r600_atom                begin_atom;
 461         bool                            begin_emitted;
 462         unsigned                        num_dw_for_end;
 463
 464         unsigned                        enabled_mask;
 465         unsigned                        num_targets;
 466         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 467
 468         unsigned                        append_bitmask;
 469         bool                            suspended;
 470
 471         /* External state which comes from the vertex shader,
 472          * it must be set explicitly when binding a shader. */
 473         unsigned                        *stride_in_dw;
 474         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 475
 476         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 477         unsigned                        hw_enabled_mask;
 478
 479         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 480         struct r600_atom                enable_atom;
 481         bool                            streamout_enabled;
 482         bool                            prims_gen_query_enabled;
 483         int                             num_prims_gen_queries;
 484 };
 485
 486 struct r600_signed_scissor {
 487         int minx;
 488         int miny;
 489         int maxx;
 490         int maxy;
 491 };
 492
 493 struct r600_scissors {
 494         struct r600_atom                atom;
 495         unsigned                        dirty_mask;
 496         struct pipe_scissor_state       states[R600_MAX_VIEWPORTS];
 497 };
 498
 499 struct r600_viewports {
 500         struct r600_atom                atom;
 501         unsigned                        dirty_mask;
 502         unsigned                        depth_range_dirty_mask;
 503         struct pipe_viewport_state      states[R600_MAX_VIEWPORTS];
 504         struct r600_signed_scissor      as_scissor[R600_MAX_VIEWPORTS];
 505 };
 506
 507 struct r600_ring {
 508         struct radeon_winsys_cs         *cs;
 509         void (*flush)(void *ctx, unsigned flags,
 510                       struct pipe_fence_handle **fence);
 511 };
 512
 513 /* Saved CS data for debugging features. */
 514 struct radeon_saved_cs {
 515         uint32_t                        *ib;
 516         unsigned                        num_dw;
 517
 518         struct radeon_bo_list_item      *bo_list;
 519         unsigned                        bo_count;
 520 };
 521
 522 struct r600_common_context {
 523         struct pipe_context b; /* base class */
 524
 525         struct r600_common_screen       *screen;
 526         struct radeon_winsys            *ws;
 527         struct radeon_winsys_ctx        *ctx;
 528         enum radeon_family              family;
 529         enum chip_class                 chip_class;
 530         struct r600_ring                gfx;
 531         struct r600_ring                dma;
 532         struct pipe_fence_handle        *last_gfx_fence;
 533         struct pipe_fence_handle        *last_sdma_fence;
 534         unsigned                        num_gfx_cs_flushes;
 535         unsigned                        initial_gfx_cs_size;
 536         unsigned                        gpu_reset_counter;
 537         unsigned                        last_dirty_fb_counter;
 538         unsigned                        last_compressed_colortex_counter;
 539         unsigned                        last_dirty_tex_descriptor_counter;
 540
 541         struct u_upload_mgr             *uploader;
 542         struct u_suballocator           *allocator_zeroed_memory;
 543         struct slab_mempool     pool_transfers;
 544
 545         /* Current unaccounted memory usage. */
 546         uint64_t                        vram;
 547         uint64_t                        gtt;
 548
 549         /* States. */
 550         struct r600_streamout           streamout;
 551         struct r600_scissors            scissors;
 552         struct r600_viewports           viewports;
 553         bool                            scissor_enabled;
 554         bool                            clip_halfz;
 555         bool                            vs_writes_viewport_index;
 556         bool                            vs_disables_clipping_viewport;
 557
 558         /* Additional context states. */
 559         unsigned flags; /* flush flags */
 560
 561         /* Queries. */
 562         /* Maintain the list of active queries for pausing between IBs. */
 563         int                             num_occlusion_queries;
 564         int                             num_perfect_occlusion_queries;
 565         struct list_head                active_queries;
 566         unsigned                        num_cs_dw_queries_suspend;
 567         /* Additional hardware info. */
 568         unsigned                        backend_mask;
 569         unsigned                        max_db; /* for OQ */
 570         /* Misc stats. */
 571         unsigned                        num_draw_calls;
 572         unsigned                        num_spill_draw_calls;
 573         unsigned                        num_compute_calls;
 574         unsigned                        num_spill_compute_calls;
 575         unsigned                        num_dma_calls;
 576         unsigned                        num_vs_flushes;
 577         unsigned                        num_ps_flushes;
 578         unsigned                        num_cs_flushes;
 579         uint64_t                        num_alloc_tex_transfer_bytes;
 580         unsigned                        last_tex_ps_draw_ratio; /* for query */
 581
 582         /* Render condition. */
 583         struct r600_atom                render_cond_atom;
 584         struct pipe_query               *render_cond;
 585         unsigned                        render_cond_mode;
 586         bool                            render_cond_invert;
 587         bool                            render_cond_force_off; /* for u_blitter */
 588
 589         /* MSAA sample locations.
 590          * The first index is the sample index.
 591          * The second index is the coordinate: X, Y. */
 592         float                           sample_locations_1x[1][2];
 593         float                           sample_locations_2x[2][2];
 594         float                           sample_locations_4x[4][2];
 595         float                           sample_locations_8x[8][2];
 596         float                           sample_locations_16x[16][2];
 597
 598         /* Statistics gathering for the DCC enablement heuristic. It can't be
 599          * in r600_texture because r600_texture can be shared by multiple
 600          * contexts. This is for back buffers only. We shouldn't get too many
 601          * of those.
 602          *
 603          * X11 DRI3 rotates among a finite set of back buffers. They should
 604          * all fit in this array. If they don't, separate DCC might never be
 605          * enabled by DCC stat gathering.
 606          */
 607         struct {
 608                 struct r600_texture             *tex;
 609                 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
 610                 struct pipe_query               *ps_stats[3];
 611                 /* If all slots are used and another slot is needed,
 612                  * the least recently used slot is evicted based on this. */
 613                 int64_t                         last_use_timestamp;
 614                 bool                            query_active;
 615         } dcc_stats[5];
 616
 617         /* The list of all texture buffer objects in this context.
 618          * This list is walked when a buffer is invalidated/reallocated and
 619          * the GPU addresses are updated. */
 620         struct list_head                texture_buffers;
 621
 622         struct pipe_debug_callback      debug;
 623
 624         /* Copy one resource to another using async DMA. */
 625         void (*dma_copy)(struct pipe_context *ctx,
 626                          struct pipe_resource *dst,
 627                          unsigned dst_level,
 628                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 629                          struct pipe_resource *src,
 630                          unsigned src_level,
 631                          const struct pipe_box *src_box);
 632
 633         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 634                              uint64_t offset, uint64_t size, unsigned value,
 635                              enum r600_coherency coher);
 636
 637         void (*blit_decompress_depth)(struct pipe_context *ctx,
 638                                       struct r600_texture *texture,
 639                                       struct r600_texture *staging,
 640                                       unsigned first_level, unsigned last_level,
 641                                       unsigned first_layer, unsigned last_layer,
 642                                       unsigned first_sample, unsigned last_sample);
 643
 644         void (*decompress_dcc)(struct pipe_context *ctx,
 645                                struct r600_texture *rtex);
 646
 647         /* Reallocate the buffer and update all resource bindings where
 648          * the buffer is bound, including all resource descriptors. */
 649         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 650
 651         /* Enable or disable occlusion queries. */
 652         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 653
 654         void (*save_qbo_state)(struct pipe_context *ctx, struct r600_qbo_state *st);
 655
 656         /* This ensures there is enough space in the command stream. */
 657         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 658                                   bool include_draw_vbo);
 659
 660         void (*set_atom_dirty)(struct r600_common_context *ctx,
 661                                struct r600_atom *atom, bool dirty);
 662
 663         void (*check_vm_faults)(struct r600_common_context *ctx,
 664                                 struct radeon_saved_cs *saved,
 665                                 enum ring_type ring);
 666 };
 667
 668 /* r600_buffer.c */
 669 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 670                                      struct pb_buffer *buf,
 671                                      enum radeon_bo_usage usage);
 672 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 673                                       struct r600_resource *resource,
 674                                       unsigned usage);
 675 void r600_buffer_subdata(struct pipe_context *ctx,
 676                          struct pipe_resource *buffer,
 677                          unsigned usage, unsigned offset,
 678                          unsigned size, const void *data);
 679 void r600_init_resource_fields(struct r600_common_screen *rscreen,
 680                                struct r600_resource *res,
 681                                uint64_t size, unsigned alignment);
 682 bool r600_alloc_resource(struct r600_common_screen *rscreen,
 683                          struct r600_resource *res);
 684 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 685                                          const struct pipe_resource *templ,
 686                                          unsigned alignment);
 687 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
 688                                                   unsigned bind,
 689                                                   unsigned usage,
 690                                                   unsigned size,
 691                                                   unsigned alignment);
 692 struct pipe_resource *
 693 r600_buffer_from_user_memory(struct pipe_screen *screen,
 694                              const struct pipe_resource *templ,
 695                              void *user_memory);
 696 void
 697 r600_invalidate_resource(struct pipe_context *ctx,
 698                          struct pipe_resource *resource);
 699
 700 /* r600_common_pipe.c */
 701 void r600_gfx_write_fence(struct r600_common_context *ctx,
 702                           uint64_t va, uint32_t old_value, uint32_t new_value);
 703 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen);
 704 void r600_gfx_wait_fence(struct r600_common_context *ctx,
 705                          uint64_t va, uint32_t ref, uint32_t mask);
 706 void r600_draw_rectangle(struct blitter_context *blitter,
 707                          int x1, int y1, int x2, int y2, float depth,
 708                          enum blitter_attrib_type type,
 709                          const union pipe_color_union *attrib);
 710 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 711                              struct radeon_winsys *ws);
 712 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 713 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 714 void r600_postflush_resume_features(struct r600_common_context *ctx);
 715 bool r600_common_context_init(struct r600_common_context *rctx,
 716                               struct r600_common_screen *rscreen,
 717                               unsigned context_flags);
 718 void r600_common_context_cleanup(struct r600_common_context *rctx);
 719 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 720 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 721                           unsigned processor);
 722 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 723                               uint64_t offset, uint64_t size, unsigned value,
 724                               enum r600_coherency coher);
 725 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 726                                                   const struct pipe_resource *templ);
 727 const char *r600_get_llvm_processor_name(enum radeon_family family);
 728 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
 729                          struct r600_resource *dst, struct r600_resource *src);
 730 void r600_dma_emit_wait_idle(struct r600_common_context *rctx);
 731 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
 732                     struct radeon_saved_cs *saved);
 733 void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
 734
 735 /* r600_gpu_load.c */
 736 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 737 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
 738 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 739
 740 /* r600_perfcounters.c */
 741 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
 742
 743 /* r600_query.c */
 744 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
 745 void r600_query_init(struct r600_common_context *rctx);
 746 void r600_suspend_queries(struct r600_common_context *ctx);
 747 void r600_resume_queries(struct r600_common_context *ctx);
 748 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 749
 750 /* r600_streamout.c */
 751 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 752 void r600_set_streamout_targets(struct pipe_context *ctx,
 753                                 unsigned num_targets,
 754                                 struct pipe_stream_output_target **targets,
 755                                 const unsigned *offset);
 756 void r600_emit_streamout_end(struct r600_common_context *rctx);
 757 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 758                                              unsigned type, int diff);
 759 void r600_streamout_init(struct r600_common_context *rctx);
 760
 761 /* r600_test_dma.c */
 762 void r600_test_dma(struct r600_common_screen *rscreen);
 763
 764 /* r600_texture.c */
 765 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
 766                                 struct r600_texture *rdst,
 767                                 unsigned dst_level, unsigned dstx,
 768                                 unsigned dsty, unsigned dstz,
 769                                 struct r600_texture *rsrc,
 770                                 unsigned src_level,
 771                                 const struct pipe_box *src_box);
 772 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 773                                  struct r600_texture *rtex,
 774                                  unsigned nr_samples,
 775                                  struct r600_fmask_info *out);
 776 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 777                                  struct r600_texture *rtex,
 778                                  struct r600_cmask_info *out);
 779 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 780                                      struct pipe_resource *texture,
 781                                      struct r600_texture **staging);
 782 void r600_print_texture_info(struct r600_texture *rtex, FILE *f);
 783 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 784                                         const struct pipe_resource *templ);
 785 bool vi_dcc_formats_compatible(enum pipe_format format1,
 786                                enum pipe_format format2);
 787 void vi_dcc_disable_if_incompatible_format(struct r600_common_context *rctx,
 788                                            struct pipe_resource *tex,
 789                                            unsigned level,
 790                                            enum pipe_format view_format);
 791 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 792                                                 struct pipe_resource *texture,
 793                                                 const struct pipe_surface *templ,
 794                                                 unsigned width, unsigned height);
 795 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
 796 void vi_separate_dcc_start_query(struct pipe_context *ctx,
 797                                  struct r600_texture *tex);
 798 void vi_separate_dcc_stop_query(struct pipe_context *ctx,
 799                                 struct r600_texture *tex);
 800 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
 801                                              struct r600_texture *tex);
 802 void vi_dcc_clear_level(struct r600_common_context *rctx,
 803                         struct r600_texture *rtex,
 804                         unsigned level, unsigned clear_value);
 805 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 806                                    struct pipe_framebuffer_state *fb,
 807                                    struct r600_atom *fb_state,
 808                                    unsigned *buffers, unsigned *dirty_cbufs,
 809                                    const union pipe_color_union *color);
 810 bool r600_texture_disable_dcc(struct r600_common_context *rctx,
 811                               struct r600_texture *rtex);
 812 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 813 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 814
 815 /* r600_viewport.c */
 816 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
 817                                             struct pipe_scissor_state *scissor);
 818 void r600_viewport_set_rast_deps(struct r600_common_context *rctx,
 819                                  bool scissor_enable, bool clip_halfz);
 820 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
 821                                           struct tgsi_shader_info *info);
 822 void r600_init_viewport_functions(struct r600_common_context *rctx);
 823
 824 /* cayman_msaa.c */
 825 extern const uint32_t eg_sample_locs_2x[4];
 826 extern const unsigned eg_max_dist_2x;
 827 extern const uint32_t eg_sample_locs_4x[4];
 828 extern const unsigned eg_max_dist_4x;
 829 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 830                                 unsigned sample_index, float *out_value);
 831 void cayman_init_msaa(struct pipe_context *ctx);
 832 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 833 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 834                              int ps_iter_samples, int overrast_samples,
 835                              unsigned sc_mode_cntl_1);
 836
 837
 838 /* Inline helpers. */
 839
 840 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 841 {
 842         return (struct r600_resource*)r;
 843 }
 844
 845 static inline void
 846 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 847 {
 848         pipe_resource_reference((struct pipe_resource **)ptr,
 849                                 (struct pipe_resource *)res);
 850 }
 851
 852 static inline void
 853 r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
 854 {
 855         pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
 856 }
 857
 858 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
 859 {
 860         return rctx->streamout.streamout_enabled ||
 861                rctx->streamout.prims_gen_query_enabled;
 862 }
 863
 864 #define     SQ_TEX_XY_FILTER_POINT                         0x00
 865 #define     SQ_TEX_XY_FILTER_BILINEAR                      0x01
 866 #define     SQ_TEX_XY_FILTER_ANISO_POINT                   0x02
 867 #define     SQ_TEX_XY_FILTER_ANISO_BILINEAR                0x03
 868
 869 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
 870 {
 871         if (filter == PIPE_TEX_FILTER_LINEAR)
 872                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
 873                                      : SQ_TEX_XY_FILTER_BILINEAR;
 874         else
 875                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
 876                                      : SQ_TEX_XY_FILTER_POINT;
 877 }
 878
 879 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 880 {
 881         if (filter < 2)
 882                 return 0;
 883         if (filter < 4)
 884                 return 1;
 885         if (filter < 8)
 886                 return 2;
 887         if (filter < 16)
 888                 return 3;
 889         return 4;
 890 }
 891
 892 static inline unsigned r600_wavefront_size(enum radeon_family family)
 893 {
 894         switch (family) {
 895         case CHIP_RV610:
 896         case CHIP_RS780:
 897         case CHIP_RV620:
 898         case CHIP_RS880:
 899                 return 16;
 900         case CHIP_RV630:
 901         case CHIP_RV635:
 902         case CHIP_RV730:
 903         case CHIP_RV710:
 904         case CHIP_PALM:
 905         case CHIP_CEDAR:
 906                 return 32;
 907         default:
 908                 return 64;
 909         }
 910 }
 911
 912 static inline enum radeon_bo_priority
 913 r600_get_sampler_view_priority(struct r600_resource *res)
 914 {
 915         if (res->b.b.target == PIPE_BUFFER)
 916                 return RADEON_PRIO_SAMPLER_BUFFER;
 917
 918         if (res->b.b.nr_samples > 1)
 919                 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
 920
 921         return RADEON_PRIO_SAMPLER_TEXTURE;
 922 }
 923
 924 static inline bool
 925 r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
 926 {
 927         return (stencil_sampler && tex->can_sample_s) ||
 928                (!stencil_sampler && tex->can_sample_z);
 929 }
 930
 931 #define COMPUTE_DBG(rscreen, fmt, args...) \
 932         do { \
 933                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 934         } while (0);
 935
 936 #define R600_ERR(fmt, args...) \
 937         fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
 938
 939 /* For MSAA sample positions. */
 940 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 941         (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) |                  \
 942         (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) |         \
 943         (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) |        \
 944          (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
 945
 946 #endif