src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/drm/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/u_double_list.h"
  41 #include "util/u_range.h"
  42 #include "util/u_slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  47 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  48 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  49
  50 #define R600_QUERY_DRAW_CALLS           (PIPE_QUERY_DRIVER_SPECIFIC + 0)
  51 #define R600_QUERY_REQUESTED_VRAM       (PIPE_QUERY_DRIVER_SPECIFIC + 1)
  52 #define R600_QUERY_REQUESTED_GTT        (PIPE_QUERY_DRIVER_SPECIFIC + 2)
  53 #define R600_QUERY_BUFFER_WAIT_TIME     (PIPE_QUERY_DRIVER_SPECIFIC + 3)
  54 #define R600_QUERY_NUM_CS_FLUSHES       (PIPE_QUERY_DRIVER_SPECIFIC + 4)
  55 #define R600_QUERY_NUM_BYTES_MOVED      (PIPE_QUERY_DRIVER_SPECIFIC + 5)
  56 #define R600_QUERY_VRAM_USAGE           (PIPE_QUERY_DRIVER_SPECIFIC + 6)
  57 #define R600_QUERY_GTT_USAGE            (PIPE_QUERY_DRIVER_SPECIFIC + 7)
  58
  59 /* read caches */
  60 #define R600_CONTEXT_INV_VERTEX_CACHE           (1 << 0)
  61 #define R600_CONTEXT_INV_TEX_CACHE              (1 << 1)
  62 #define R600_CONTEXT_INV_CONST_CACHE            (1 << 2)
  63 #define R600_CONTEXT_INV_SHADER_CACHE           (1 << 3)
  64 /* read-write caches */
  65 #define R600_CONTEXT_STREAMOUT_FLUSH            (1 << 8)
  66 #define R600_CONTEXT_FLUSH_AND_INV              (1 << 9)
  67 #define R600_CONTEXT_FLUSH_AND_INV_CB_META      (1 << 10)
  68 #define R600_CONTEXT_FLUSH_AND_INV_DB_META      (1 << 11)
  69 #define R600_CONTEXT_FLUSH_AND_INV_DB           (1 << 12)
  70 #define R600_CONTEXT_FLUSH_AND_INV_CB           (1 << 13)
  71 #define R600_CONTEXT_FLUSH_WITH_INV_L2          (1 << 14)
  72 /* engine synchronization */
  73 #define R600_CONTEXT_PS_PARTIAL_FLUSH           (1 << 16)
  74 #define R600_CONTEXT_WAIT_3D_IDLE               (1 << 17)
  75 #define R600_CONTEXT_WAIT_CP_DMA_IDLE           (1 << 18)
  76 #define R600_CONTEXT_VGT_FLUSH                  (1 << 19)
  77 #define R600_CONTEXT_VGT_STREAMOUT_SYNC         (1 << 20)
  78 /* other flags */
  79 #define R600_CONTEXT_FLAG_COMPUTE               (1u << 31)
  80
  81 /* special primitive types */
  82 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  83
  84 /* Debug flags. */
  85 /* logging */
  86 #define DBG_TEX                 (1 << 0)
  87 #define DBG_TEXMIP              (1 << 1)
  88 #define DBG_COMPUTE             (1 << 2)
  89 #define DBG_VM                  (1 << 3)
  90 #define DBG_TRACE_CS            (1 << 4)
  91 /* shader logging */
  92 #define DBG_FS                  (1 << 5)
  93 #define DBG_VS                  (1 << 6)
  94 #define DBG_GS                  (1 << 7)
  95 #define DBG_PS                  (1 << 8)
  96 #define DBG_CS                  (1 << 9)
  97 /* features */
  98 #define DBG_NO_ASYNC_DMA        (1 << 10)
  99 #define DBG_HYPERZ              (1 << 11)
 100 #define DBG_NO_DISCARD_RANGE    (1 << 12)
 101 #define DBG_NO_2D_TILING        (1 << 13)
 102 #define DBG_NO_TILING           (1 << 14)
 103 #define DBG_SWITCH_ON_EOP       (1 << 15)
 104 #define DBG_FORCE_DMA           (1 << 16)
 105 /* The maximum allowed bit is 20. */
 106
 107 #define R600_MAP_BUFFER_ALIGNMENT 64
 108
 109 struct r600_common_context;
 110
 111 struct radeon_shader_binary {
 112         /** Shader code */
 113         unsigned char *code;
 114         unsigned code_size;
 115
 116         /** Config/Context register state that accompanies this shader.
 117          * This is a stream of dword pairs.  First dword contains the
 118          * register address, the second dword contains the value.*/
 119         unsigned char *config;
 120         unsigned config_size;
 121
 122         /** Constant data accessed by the shader.  This will be uploaded
 123          * into a constant buffer. */
 124         unsigned char *rodata;
 125         unsigned rodata_size;
 126
 127         /** Set to 1 if the disassembly for this binary has been dumped to
 128          *  stderr. */
 129         int disassembled;
 130 };
 131
 132 struct r600_resource {
 133         struct u_resource               b;
 134
 135         /* Winsys objects. */
 136         struct pb_buffer                *buf;
 137         struct radeon_winsys_cs_handle  *cs_buf;
 138         uint64_t                        gpu_address;
 139
 140         /* Resource state. */
 141         enum radeon_bo_domain           domains;
 142
 143         /* The buffer range which is initialized (with a write transfer,
 144          * streamout, DMA, or as a random access target). The rest of
 145          * the buffer is considered invalid and can be mapped unsynchronized.
 146          *
 147          * This allows unsychronized mapping of a buffer range which hasn't
 148          * been used yet. It's for applications which forget to use
 149          * the unsynchronized map flag and expect the driver to figure it out.
 150          */
 151         struct util_range               valid_buffer_range;
 152 };
 153
 154 struct r600_transfer {
 155         struct pipe_transfer            transfer;
 156         struct r600_resource            *staging;
 157         unsigned                        offset;
 158 };
 159
 160 struct r600_fmask_info {
 161         unsigned offset;
 162         unsigned size;
 163         unsigned alignment;
 164         unsigned pitch;
 165         unsigned bank_height;
 166         unsigned slice_tile_max;
 167         unsigned tile_mode_index;
 168 };
 169
 170 struct r600_cmask_info {
 171         unsigned offset;
 172         unsigned size;
 173         unsigned alignment;
 174         unsigned slice_tile_max;
 175         unsigned base_address_reg;
 176 };
 177
 178 struct r600_texture {
 179         struct r600_resource            resource;
 180
 181         unsigned                        size;
 182         unsigned                        pitch_override;
 183         bool                            is_depth;
 184         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 185         struct r600_texture             *flushed_depth_texture;
 186         boolean                         is_flushing_texture;
 187         struct radeon_surface           surface;
 188
 189         /* Colorbuffer compression and fast clear. */
 190         struct r600_fmask_info          fmask;
 191         struct r600_cmask_info          cmask;
 192         struct r600_resource            *cmask_buffer;
 193         unsigned                        cb_color_info; /* fast clear enable bit */
 194         unsigned                        color_clear_value[2];
 195
 196         /* Depth buffer compression and fast clear. */
 197         struct r600_resource            *htile_buffer;
 198         bool                            depth_cleared; /* if it was cleared at least once */
 199         float                           depth_clear_value;
 200
 201         bool                            non_disp_tiling; /* R600-Cayman only */
 202         unsigned                        mipmap_shift;
 203 };
 204
 205 struct r600_surface {
 206         struct pipe_surface             base;
 207
 208         bool color_initialized;
 209         bool depth_initialized;
 210
 211         /* Misc. color flags. */
 212         bool alphatest_bypass;
 213         bool export_16bpc;
 214
 215         /* Color registers. */
 216         unsigned cb_color_info;
 217         unsigned cb_color_base;
 218         unsigned cb_color_view;
 219         unsigned cb_color_size;         /* R600 only */
 220         unsigned cb_color_dim;          /* EG only */
 221         unsigned cb_color_pitch;        /* EG and later */
 222         unsigned cb_color_slice;        /* EG and later */
 223         unsigned cb_color_attrib;       /* EG and later */
 224         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 225         unsigned cb_color_fmask_slice;  /* EG and later */
 226         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 227         unsigned cb_color_mask;         /* R600 only */
 228         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 229         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 230
 231         /* DB registers. */
 232         unsigned db_depth_info;         /* R600 only, then SI and later */
 233         unsigned db_z_info;             /* EG and later */
 234         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 235         unsigned db_depth_view;
 236         unsigned db_depth_size;
 237         unsigned db_depth_slice;        /* EG and later */
 238         unsigned db_stencil_base;       /* EG and later */
 239         unsigned db_stencil_info;       /* EG and later */
 240         unsigned db_prefetch_limit;     /* R600 only */
 241         unsigned db_htile_surface;
 242         unsigned db_htile_data_base;
 243         unsigned db_preload_control;    /* EG and later */
 244         unsigned pa_su_poly_offset_db_fmt_cntl;
 245 };
 246
 247 struct r600_tiling_info {
 248         unsigned num_channels;
 249         unsigned num_banks;
 250         unsigned group_bytes;
 251 };
 252
 253 struct r600_common_screen {
 254         struct pipe_screen              b;
 255         struct radeon_winsys            *ws;
 256         enum radeon_family              family;
 257         enum chip_class                 chip_class;
 258         struct radeon_info              info;
 259         struct r600_tiling_info         tiling_info;
 260         unsigned                        debug_flags;
 261         bool                            has_cp_dma;
 262         bool                            has_streamout;
 263
 264         /* Auxiliary context. Mainly used to initialize resources.
 265          * It must be locked prior to using and flushed before unlocking. */
 266         struct pipe_context             *aux_context;
 267         pipe_mutex                      aux_context_lock;
 268
 269         struct r600_resource            *trace_bo;
 270         uint32_t                        *trace_ptr;
 271         unsigned                        cs_count;
 272 };
 273
 274 /* This encapsulates a state or an operation which can emitted into the GPU
 275  * command stream. */
 276 struct r600_atom {
 277         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 278         unsigned                num_dw;
 279         bool                    dirty;
 280 };
 281
 282 struct r600_so_target {
 283         struct pipe_stream_output_target b;
 284
 285         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 286         struct r600_resource    *buf_filled_size;
 287         unsigned                buf_filled_size_offset;
 288
 289         unsigned                stride_in_dw;
 290 };
 291
 292 struct r600_streamout {
 293         struct r600_atom                begin_atom;
 294         bool                            begin_emitted;
 295         unsigned                        num_dw_for_end;
 296
 297         unsigned                        enabled_mask;
 298         unsigned                        num_targets;
 299         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 300
 301         unsigned                        append_bitmask;
 302         bool                            suspended;
 303
 304         /* External state which comes from the vertex shader,
 305          * it must be set explicitly when binding a shader. */
 306         unsigned                        *stride_in_dw;
 307
 308         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 309         struct r600_atom                enable_atom;
 310         bool                            streamout_enabled;
 311         bool                            prims_gen_query_enabled;
 312         int                             num_prims_gen_queries;
 313 };
 314
 315 struct r600_ring {
 316         struct radeon_winsys_cs         *cs;
 317         bool                            flushing;
 318         void (*flush)(void *ctx, unsigned flags,
 319                       struct pipe_fence_handle **fence);
 320 };
 321
 322 struct r600_rings {
 323         struct r600_ring                gfx;
 324         struct r600_ring                dma;
 325 };
 326
 327 struct r600_common_context {
 328         struct pipe_context b; /* base class */
 329
 330         struct r600_common_screen       *screen;
 331         struct radeon_winsys            *ws;
 332         enum radeon_family              family;
 333         enum chip_class                 chip_class;
 334         struct r600_rings               rings;
 335         unsigned                        initial_gfx_cs_size;
 336
 337         struct u_upload_mgr             *uploader;
 338         struct u_suballocator           *allocator_so_filled_size;
 339         struct util_slab_mempool        pool_transfers;
 340
 341         /* Current unaccounted memory usage. */
 342         uint64_t                        vram;
 343         uint64_t                        gtt;
 344
 345         /* States. */
 346         struct r600_streamout           streamout;
 347
 348         /* Additional context states. */
 349         unsigned flags; /* flush flags */
 350
 351         /* Queries. */
 352         /* The list of active queries. Only one query of each type can be active. */
 353         int                             num_occlusion_queries;
 354         int                             num_pipelinestat_queries;
 355         /* Keep track of non-timer queries, because they should be suspended
 356          * during context flushing.
 357          * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
 358         struct list_head                active_nontimer_queries;
 359         unsigned                        num_cs_dw_nontimer_queries_suspend;
 360         /* If queries have been suspended. */
 361         bool                            nontimer_queries_suspended;
 362         /* Additional hardware info. */
 363         unsigned                        backend_mask;
 364         unsigned                        max_db; /* for OQ */
 365         /* Misc stats. */
 366         unsigned                        num_draw_calls;
 367
 368         /* Render condition. */
 369         struct pipe_query               *current_render_cond;
 370         unsigned                        current_render_cond_mode;
 371         boolean                         current_render_cond_cond;
 372         boolean                         predicate_drawing;
 373         /* For context flushing. */
 374         struct pipe_query               *saved_render_cond;
 375         boolean                         saved_render_cond_cond;
 376         unsigned                        saved_render_cond_mode;
 377
 378         /* MSAA sample locations.
 379          * The first index is the sample index.
 380          * The second index is the coordinate: X, Y. */
 381         float                           sample_locations_1x[1][2];
 382         float                           sample_locations_2x[2][2];
 383         float                           sample_locations_4x[4][2];
 384         float                           sample_locations_8x[8][2];
 385         float                           sample_locations_16x[16][2];
 386
 387         /* The list of all texture buffer objects in this context.
 388          * This list is walked when a buffer is invalidated/reallocated and
 389          * the GPU addresses are updated. */
 390         struct list_head                texture_buffers;
 391
 392         /* Copy one resource to another using async DMA. */
 393         void (*dma_copy)(struct pipe_context *ctx,
 394                          struct pipe_resource *dst,
 395                          unsigned dst_level,
 396                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 397                          struct pipe_resource *src,
 398                          unsigned src_level,
 399                          const struct pipe_box *src_box);
 400
 401         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 402                              unsigned offset, unsigned size, unsigned value);
 403
 404         void (*blit_decompress_depth)(struct pipe_context *ctx,
 405                                       struct r600_texture *texture,
 406                                       struct r600_texture *staging,
 407                                       unsigned first_level, unsigned last_level,
 408                                       unsigned first_layer, unsigned last_layer,
 409                                       unsigned first_sample, unsigned last_sample);
 410
 411         /* Reallocate the buffer and update all resource bindings where
 412          * the buffer is bound, including all resource descriptors. */
 413         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 414
 415         /* Enable or disable occlusion queries. */
 416         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 417
 418         /* This ensures there is enough space in the command stream. */
 419         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 420                                   bool include_draw_vbo);
 421 };
 422
 423 /* r600_buffer.c */
 424 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 425                                         struct radeon_winsys_cs_handle *buf,
 426                                         enum radeon_bo_usage usage);
 427 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 428                                       struct r600_resource *resource,
 429                                       unsigned usage);
 430 bool r600_init_resource(struct r600_common_screen *rscreen,
 431                         struct r600_resource *res,
 432                         unsigned size, unsigned alignment,
 433                         bool use_reusable_pool);
 434 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 435                                          const struct pipe_resource *templ,
 436                                          unsigned alignment);
 437
 438 /* r600_common_pipe.c */
 439 void r600_draw_rectangle(struct blitter_context *blitter,
 440                          int x1, int y1, int x2, int y2, float depth,
 441                          enum blitter_attrib_type type,
 442                          const union pipe_color_union *attrib);
 443 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 444                              struct radeon_winsys *ws);
 445 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 446 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 447 void r600_postflush_resume_features(struct r600_common_context *ctx);
 448 bool r600_common_context_init(struct r600_common_context *rctx,
 449                               struct r600_common_screen *rscreen);
 450 void r600_common_context_cleanup(struct r600_common_context *rctx);
 451 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 452 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 453                           const struct tgsi_token *tokens);
 454 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 455                               unsigned offset, unsigned size, unsigned value);
 456 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 457                                                   const struct pipe_resource *templ);
 458 const char *r600_get_llvm_processor_name(enum radeon_family family);
 459 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw);
 460
 461 /* r600_query.c */
 462 void r600_query_init(struct r600_common_context *rctx);
 463 void r600_suspend_nontimer_queries(struct r600_common_context *ctx);
 464 void r600_resume_nontimer_queries(struct r600_common_context *ctx);
 465 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 466
 467 /* r600_streamout.c */
 468 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 469 void r600_set_streamout_targets(struct pipe_context *ctx,
 470                                 unsigned num_targets,
 471                                 struct pipe_stream_output_target **targets,
 472                                 const unsigned *offset);
 473 void r600_emit_streamout_end(struct r600_common_context *rctx);
 474 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 475                                              unsigned type, int diff);
 476 void r600_streamout_init(struct r600_common_context *rctx);
 477
 478 /* r600_texture.c */
 479 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 480                                  struct r600_texture *rtex,
 481                                  unsigned nr_samples,
 482                                  struct r600_fmask_info *out);
 483 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 484                                  struct r600_texture *rtex,
 485                                  struct r600_cmask_info *out);
 486 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 487                                      struct pipe_resource *texture,
 488                                      struct r600_texture **staging);
 489 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 490                                         const struct pipe_resource *templ);
 491 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 492                                                 struct pipe_resource *texture,
 493                                                 const struct pipe_surface *templ,
 494                                                 unsigned width, unsigned height);
 495 unsigned r600_translate_colorswap(enum pipe_format format);
 496 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 497                                    struct pipe_framebuffer_state *fb,
 498                                    struct r600_atom *fb_state,
 499                                    unsigned *buffers,
 500                                    const union pipe_color_union *color);
 501 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 502 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 503
 504 /* cayman_msaa.c */
 505 extern const uint32_t eg_sample_locs_2x[4];
 506 extern const unsigned eg_max_dist_2x;
 507 extern const uint32_t eg_sample_locs_4x[4];
 508 extern const unsigned eg_max_dist_4x;
 509 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 510                                 unsigned sample_index, float *out_value);
 511 void cayman_init_msaa(struct pipe_context *ctx);
 512 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 513 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 514                              int ps_iter_samples);
 515
 516
 517 /* Inline helpers. */
 518
 519 static INLINE struct r600_resource *r600_resource(struct pipe_resource *r)
 520 {
 521         return (struct r600_resource*)r;
 522 }
 523
 524 static INLINE void
 525 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 526 {
 527         pipe_resource_reference((struct pipe_resource **)ptr,
 528                                 (struct pipe_resource *)res);
 529 }
 530
 531 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 532 {
 533         if (filter <= 1)   return 0;
 534         if (filter <= 2)   return 1;
 535         if (filter <= 4)   return 2;
 536         if (filter <= 8)   return 3;
 537          /* else */        return 4;
 538 }
 539
 540 #define COMPUTE_DBG(rscreen, fmt, args...) \
 541         do { \
 542                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 543         } while (0);
 544
 545 #define R600_ERR(fmt, args...) \
 546         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
 547
 548 /* For MSAA sample positions. */
 549 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 550         (((s0x) & 0xf) | (((s0y) & 0xf) << 4) |            \
 551         (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |     \
 552         (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |    \
 553          (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
 554
 555 #endif